Vivado Design Suite. Migration Methodology Guide. UG911 (v2013.2) June 19, 2013

Transcription

1 Vivado Design Suite Migration Methodology Guide

2 Notice of Disclaimer The information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: Copyright Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 03/20/ Initial Xilinx release for Added IP Migration information to the introduction of Chapter 4, Migrating Designs with Legacy IP to the Vivado Design Suite. Modified the formatting in Chapter 3, Migrating UCF Constraints to XDC. Added Chapter 5, Migrating from XPS to IP Integrator. Added what to expect when migrating from XPS for Zynq and for MicroBlaze processors. Added Chapter 7, Migrating ISE ChipScope Logic Analyzer to Vivado Lab Tools. Added note to ISE Speedprint Command Line Tool. Added Appendix A, Obsolete Primitives. 06/19/ Removed net weight as a constraint option. Added references to Design Analysis and Closure documentation. Added Migrating EDK IP to the Vivado Design Suite, page 64. Migration Methodology Guide 2

3 Table of Contents Revision History Chapter 1: Introduction to ISE Design Suite Migration Overview Design Flows Chapter 2: Migrating ISE Design Suite Designs to Vivado Design Suite Importing a Project Navigator Project Converting a PlanAhead Tool Project Importing an XST Project File Migrating Source Files Mapping ISE Design Suite Command Scripts Mapping Makefiles Understanding the Differences in Messages Understanding Reporting Differences Understanding Log File Differences Chapter 3: Migrating UCF Constraints to XDC Overview Differences Between XDC and UCF Constraints UCF to XDC Mapping Constraint Sequence Converting UCF to XDC in the PlanAhead Tool TimeGROUP Timing Constraints Physical Constraints Chapter 4: Migrating Designs with Legacy IP to the Vivado Design Suite Overview Migrating CORE Generator IP to the Vivado Design Suite Migrating EDK IP to the Vivado Design Suite Migration Methodology Guide 3

4 Chapter 5: Migrating from XPS to IP Integrator Overview Migrating a Zynq-7000 AP Soc Processor-Based Design Exporting a MicroBlaze Processor Design Chapter 6: Migrating ISE Simulator Tcl to Vivado Simulator Tcl Tcl Command Migration Chapter 7: Migrating ISE ChipScope Logic Analyzer to Vivado Lab Tools Introduction Legacy IP Core Support ChipScope Pro Analyzer Core Compatibility Chapter 8: Migrating Additional Command Line Tools to Vivado Introduction Migrating the ISE Partgen Command Line Tool ISE Bitgen Command Line Tool ISE Speedprint Command Line Tool ISE PROMGen Command Line Tool ISE BSDLAnno Command Line Tool Appendix A: Obsolete Primitives Introduction Appendix B: Additional Resources Xilinx Resources Solution Centers References Migration Methodology Guide 4

5 Chapter 1 Introduction to ISE Design Suite Migration Overview ISE Design Suite is an industry-proven solution for all generations of Xilinx devices, and extends the familiar design flow for projects targeting 7 series and Zynq Soc All Programmable devices. The Vivado Design Suite supports the 7 series devices including Virtex -7, Kintex -7 and Artix -7 and offers enhanced tool performance, especially on large or congested designs. Because both the ISE Design Suite and the Vivado Design Suite support 7 series devices, you have time to migrate to the Vivado Design Suite. The Vivado Design Suite provides seamless reuse of all or part of a previous design through the ability to import projects and sources into a Vivado Design Suite project, and command mapping to Tcl scripts. Migration Methodology Guide 5

6 Design Flows Design Flows You can launch the Vivado Design Suite and run the tools using different methods depending on your preference. For example, you can choose a Tcl script-based compilation style method in which you manage sources and the design process yourself, also known as Non-Project Mode. Alternatively, you can use a project-based method to automatically manage your design process and design data using projects and project states, also known as Project Mode. Either of these methods can be run using a Tcl scripted batch mode or run interactively in the Vivado IDE. For more information on the different design flow modes, see the Vivado Design Suite User Guide: Design Flows Overview (UG892) [Ref 1]. This guide covers migration considerations and procedures for both design flow modes in the Vivado Design Suite. Migration Methodology Guide 6

7 Chapter 2 Migrating ISE Design Suite Designs to Vivado Design Suite Importing a Project Navigator Project You can use the Vivado Integrated Design Environment (IDE), which is the GUI to import an XISE project file as follows: 1. Select File > New Project. 2. Select Project name and location. 3. In the New Project Wizard, select the Imported Project option. 4. Select ISE and choose the appropriate.xise file for import. IMPORTANT: Vivado Design Suite does not support older ISE Design Suite project (.ise) files. After you have imported the project file: Review the Import XISE Summary Report for important information about the imported project. Ensure the selected device meets your requirements, and if it does not, select a new device. If the ISE project does not have an equivalent supported device in Vivado, a default device is selected. Review the files in the Sources window to ensure all design files were imported properly. If the design contained a User Constraints File (UCF), the file will appear as an unsupported constraint file. The UCF must be converted to Xilinx Design Constraints (XDC) format in order to apply any timing or physical constraints in the design. For more information, see Chapter 3, Migrating UCF Constraints to XDC. For more details on using the Vivado interface for design creation, see the Vivado Design Suite User Guide: System-Level Design Entry (UG895) [Ref 2]. For information on the next steps in design flow, see the Vivado Design Suite User Guide: Design Flows Overview (UG892) [Ref 1]. Migration Methodology Guide 7

8 Converting a PlanAhead Tool Project For information on constraints, see the Vivado Design Suite User Guide: Using Constraints (UG903) [Ref 3]. Converting a PlanAhead Tool Project To convert a PlanAhead tool project to a Vivado IDE project, open the PlanAhead project file (.ppr extension) in the Vivado IDE. When prompted, type in a new project name and location for the converted project. The project conversion effects the following changes: Targets the Vivado default 7 series device on projects with pre-7 series devices. Resets all runs. They are generated after implementing the design in the tool. Replaces run strategies with Vivado default strategies. Moves UCF files to an Unsupported Constraints Folder because UCF constraints are not supported. Note: Conversion of designs with Partitions is not supported. Note: Zynq-7000 AP Soc processor designs using XPS are not supported. Importing an XST Project File If you do not have an existing or up-to-date ISE Project Navigator (.xise) project file or PlanAhead tool (.ppr) project file, a you can use the Xilinx Synthesis Technology (XST) project file to import initial settings for a Vivado project. To import an XST project file: 1. Select File > New Project. 2. Select Project name and location. 3. In the New Project Wizard, select Imported Project. 4. Select XST, and select the appropriate project file with a.xst extension. After you have imported the project file: Review the Import XST Summary Report for important information about the imported project. Ensure the selected device meets your requirements, and if it does not, select a new device. If the XST project does not have an equivalent supported device in Vivado, a default device is selected. Review the files in the Sources view to ensure all design files were imported properly. Migration Methodology Guide 8

9 Migrating Source Files For information on the next steps in design flow, see the Vivado Design Suite User Guide: System-Level Design Entry (UG895) [Ref 1]. Migrating Source Files When you import a project or convert a project into the Vivado IDE, as specified above, you can also add all source files that are supported in Vivado Design Suite to the Vivado project. IP: You can migrate existing ISE Design Suite projects and IP to Vivado Design Suite projects and IP. The Vivado Design Suite can use ISE Design Suite IP during implementation. For more information, see Chapter 4, Migrating Designs with Legacy IP to the Vivado Design Suite. Source files: You can add all source files, with the exception of Schematic (SCH) and Architecture Wizard (XAW) source files, from an existing ISE Design Suite project to new project in the Vivado Design Suite. For example, you can add CORE Generator tool project files (.xco file extension) and netlist files (.ngc file extension) as design sources. Constraints: User Constraint Format (UCF) files used for the design or IP must be converted to Xilinx Design Constraints (XDC) format for use with Vivado Design Suite. For more information about UCF to XDC migration, see Chapter 3, Migrating UCF Constraints to XDC in this guide. CAUTION! Do not migrate from ISE Design Suite and Vivado Design Suite in the middle of a current ISE Design Suite project because design constraints and scripts are not compatible between the environments. Migration Methodology Guide 9

10 Mapping ISE Design Suite Command Scripts Mapping ISE Design Suite Command Scripts This section covers the Vivado Design Suite non-project design flow mode only, and is intended for those who plan to use Tcl scripting with the Vivado tool. You can use Tcl scripts to migrate your ISE Design Suite scripts to implement your FPGA design. Similar to the ISE Design Suite, the compilation flow in the Vivado Design Suite translates the design, maps the translated design to device-specific elements, optimizes the design, places and routes the design, and then generates a BIT file for programming. Table 2-1 shows the main differences between the two design flows. Table 2-1: ISE Design Suite versus Vivado Design Suite Design Flow ISE Design Suite Vivado Design Suite Separate command line applications XCF/NCF/UCF/PCF constraints Design constraints (timing or physical) only applied at beginning of the flow Multiple database files (NGC, NGD, NCD) required Reports generated by applications Table 2-2, page 11 shows the mapping of ISE Design Suite commands to corresponding Vivado Design Suite Tcl commands. You can run the Tcl commands using any of the following: In the Vivado IDE Tcl Console At the Tcl Prompt (vivado -mode tcl) Tcl commands in a shell. XDC timing and physical constraints Constraints (timing or physical) can be applied, changed, or removed at any point in the flow. A single design database (checkpoint with a.dcp extension) written out on-demand at any point in the flow. Reports generated on-demand at any point in the flow, where applicable. Through a batch script (vivado -mode batch -source my.tcl) Migration Methodology Guide 10

11 Mapping ISE Design Suite Command Scripts Table 2-2: ISE Design Suite Commands and Vivado Design Suite Tcl Commands ISE Design Suite Command Vivado Design Suite Tcl Command xst ngdbuild map par trce xpwr drc netgen bitgen read_verilog read_vhdl read_xdc synth_design Note: The commands must be run in this order. read_edif read_xdc link_design Note: You need these commands only if you are importing from third-party synthesis. If using synth_design, omit these steps. opt_design power_opt_design (optional) place_design phys_opt_design (optional) route_design report_timing report_timing_summary read_saif report_power report_drc write_verilog write_vhdl write_sdf write_bitstream Migration Methodology Guide 11

12 Mapping ISE Design Suite Command Scripts ISE and the Vivado Design Suite use different algorithms; consequently, a one-to-one mapping is not always possible between the two tool flows. Table 2-3 provides a mapping of frequently-used options between the two implementation flows. Table 2-3: ISE to Vivado Implementation Flow Mappings ISE Vivado ngdbuild -p partname ngdbuild -a (insert pads) ngdbuild -u (unexpanded blocks) ngdbuild -quiet map -detail map -lc auto map -logic_opt map -mt map -ntd map -ol map -power map -u par -pl par -rl par -mt par -k (keep existing placement and routing) par -nopad par -ntd link_design -part synth_design -no_iobuf (opposite) Allowed by default, generates critical warnings. link_design -quiet opt_design -verbose happens automatically in place_design opt_design, phys_opt_design place_design automatically runs MT with four cores in Linux or two cores in Windows place_design -non_timing_driven place_design -effort_level power_opt_design link_design -mode out_of_context, opt_design -retarget (skip constant propagation and sweep) place_design -effort_level route_design -effort_level route_design automatically runs MT with four cores in Linux or two core in Windows Default behavior for route_design report_io generates pad report route_design -no_timing_driven Migration Methodology Guide 12

13 Mapping ISE Design Suite Command Scripts Retrieving Tcl Command Information For information about additional Tcl commands available to use for design implementation and analysis, please refer to the Vivado Design Suite Tcl Command Reference Guide (UG835). To get help at the Tcl command prompt, type: help <command> <command> -help For help with a category of Tcl commands, type: help (lists the categories) help -category <category> Note: The interactive help has an auto-complete feature and is not case-sensitive, so the following categories are the same in Tcl: end, EndGroup. To save time, you can use all lower-case and auto-complete when getting help on commands or categories (for example, type end rather than endgroup). Command Line Examples Following is an example of a typical ISE Design Suite command line run that can be put in a run.cmd file. This is followed by the same run using Vivado Design Suite Tcl commands that can be put into a run.tcl file. Example 1: Mapping ISE Design Suite Commands to Vivado Design Suite Tcl Commands ISE Design Suite Command Line xst -ifn design_top.xst #-ifn (input file name with project settings and options) ngdbuild -sd.. -dd. -p xc7v585tffg uc design_top.ucf design_top.ngd #-sd (search directory), -dd (destination directory), -p (part), -uc (UCF #file) map -xe c -w -pr b -ol high -t 2 design_top_map.ncd design_top.pcf #-xe c (extra effort), -w (overwrite existing file), -pr b (push registers #into IOBs), -ol (overall effort), -t (placer cost table) par -xe c -w -ol high -t 2 design_top_map.ncd design_top.ncd #-xe c (extra effort), -w (overwrite existing file), -ol (overall effort), -t #(placer cost table) trce -u -e 10 design_top.ncd design_top.pcf #-u (report uncovered paths), -e (generate error report) bitgen w design_top.ncd design_top.pcf Migration Methodology Guide 13

14 Mapping ISE Design Suite Command Scripts Equivalent Vivado Design Suite Tcl Command set design_name design_top #read inputs read_verilog { $design_name.v source2.v source3.v } read_vhdl -lib mylib { libsource1.vhdl libsource2.vhdl } read_xdc $design_name.xdc #run flow and save the database synth_design -top $design_name -part xc7v585tffg write_checkpoint -force ${design_name}_post_synth.dcp opt_design place_design write_checkpoint -force ${design_name}_post_place.dcp report_utilization file post_place_util.txt route_design #Reports are not generated by default report_timing_summary file post_route_timing.txt #Save the database after post route write_checkpoint -force ${design_name}_post_route.dcp #Check for DRC report_drc -file post_route_drc.txt # Write Bitstream write_bitstream -force ${design_name}.bit Example 2: Vivado Design Suite Tcl Commands for Third-Party Synthesis (starting from EDIF) set design_name design_top #read inputs read_edif { source1.edf source2.edf $design_name.edf } read_xdc $design_name.xdc link_design part xc7v585tffg top $design_name #Reports are not generated by default report_timing_summary file post_synth_timing_summ.txt opt_design place_design write_checkpoint -force ${design_name}_post_place.dcp report_utilization file post_place_util.txt route_design #Reports are not generated by default report_timing_summary file post_route_timing.txt _summ.txt #Save the database after post route Migration Methodology Guide 14

15 Mapping Makefiles write_checkpoint -force ${design_name}_post_route.dcp #Check for DRC report_drc -file post_route_drc.txt # Write Bitstream write_bitstream -force ${design_name}.bit Mapping Makefiles A makefile is a text file that is referenced by the make command and controls how the make command compiles and links a program. The makefile consists of rules for when to carry out an action and contains information such as source-level and build-order dependencies. To determine the sequence of the compilation commands, the makefile checks the timestamps of dependent files. The following example shows how to write makefiles. Example: Mapping an ISE Design Suite Makefile to Vivado Design Suite Makefile Sample Makefile used in the ISE Design Suite DESIGN = test DEVICE = xc7v585tffg UCF_FILE =../Src/${DESIGN}.ucf EDIF_FILE =../Src/${DESIGN}.edf # Make all runs to place & route all : place_n_route # bitstream : Creates device bitstream bitstream :./${DESIGN}.bit # place_n_route: Stops after place and route for analysis prior to bitstream generation place_n_route : ${DESIGN}.ncd # translate: Stops after full design elaboration for analysis and floorplanning prior to place and route step translate : ${DESIGN}.ngd # Following executes the ISE run ${DESIGN}.bit : ${DESIGN}.ncd bitgen -f ${DESIGN}.ut ${DESIGN}.ncd Migration Methodology Guide 15

16 Mapping Makefiles ${DESIGN}.ncd : ${DESIGN}_map.ncd par -w -ol high ${DESIGN}_map.ncd ${DESIGN}.ncd ${DESIGN}.pcf ${DESIGN}_map.ncd : ${DESIGN}.ngd map -w -ol high -o ${DESIGN}_map.ncd ${DESIGN}.ngd ${DESIGN}.pcf ${DESIGN}.ngd : ${EDIF_FILE} ${UCF_FILE} ngdbuild -uc ${UCF_FILE} -p ${DEVICE} ${EDIF_FILE} ${DESIGN}.ngd # Clean up all the files from the Vivado run clean : rm -rf *.ncd *.ngd *.bit *.mrp *.map *.par *.bld *.pcf *.xml *.bgn *.html \ *.lst *.ngo *.xrpt *.unroutes *.xpi *.txt *.pad *.csv *.ngm xlnx_auto* \ _xmsgs *.ptwx # Tar and compress all the files tar : tar -zcvf ${DESIGN}.tar.gz *.ncd *.ngd *.mrp *.map *.par *.bld *.pcf *.bgn \ Makefile Equivalent Makefile Used in the Vivado Design Suite DESIGN = test DEVICE = xc7v585tffg XDC_FILE =../Src/${DESIGN}.xdc EDIF_FILE =../Src/${DESIGN}.edf # Make all runs to place & route all : place_n_route # bitstream : Creates device bitstream bitstream :./${DESIGN}.bit # place_n_route: Stops after place and route for analysis prior to bitstream generation place_n_route :./${DESIGN}_route.dcp # translate: Stops after full design elaboration and initial optimization for analysis and floorplanning prior to place and route step translate :./${DESIGN}_opt.dcp # Following calls Tcl files for each desired portion of the Vivado run # Design checkpoint files and bit file used for dependency management Migration Methodology Guide 16

17 Mapping Makefiles./${DESIGN}.bit :./run_vivado_place_n_route.tcl./${design}_route.dcp vivado -mode batch -source run_vivado_bitstream.tcl -tclargs ${DESIGN}./${DESIGN}_route.dcp :./run_vivado_place_n_route.tcl./${design}_opt.dcp vivado -mode batch -source run_vivado_place_n_route.tcl -tclargs \ ${DESIGN}./${DESIGN}_opt.dcp :./run_vivado_opt.tcl ${EDIF_FILE} ${XDC_FILE} vivado -mode batch -source run_vivado_opt.tcl -tclargs ${DESIGN} ${DEVICE} ${EDIF_FILE} ${XDC_FILE} # Clean up all the files from the Vivado run clean : rm -f *.jou *.log *.rpt *.dcp *.bit *.xml *.html # Tar and compress all the files tar : tar -zcvf ${DESIGN}.tar.gz *.jou *.log *.rpt *.dcp *.tcl Makefile Associated Tcl Files for Vivado Makefile run_vivado_opt.tcl # Gathering TCL Args set DESIGN [lindex $argv 0] set DEVICE [lindex $argv 1] set EDIF_FILE [lindex $argv 2] set XDC_FILE [lindex $argv 3] # Reading EDIF/NGC file read_edif../src/${design}.edf # Linking Design link_design -part ${DEVICE} -edif_top_file../src/${design}.edf # Running Logic Optimization opt_design # Adding Constraints read_xdc ${XDC_FILE} # Saving Run write_checkpoint -force./${design}_opt.dcp Migration Methodology Guide 17

18 Mapping Makefiles # Creating opt reports report_utilization -file ${DESIGN}_utilization_opt.rpt report_timing_summary -max_paths 10 -nworst 1 -input_pins - report_io -file ${DESIGN}_io_opt.rpt report_clock_interaction -file ${DESIGN}_clock_interaction_opt.rpt exit run_vivado_place_n_route.tcl # Gathering TCL Arg set DESIGN [lindex $argv 0] read_checkpoint./${design}_opt.dcp # Placing Design place_design write_checkpoint -force./${design}_place.dcp # Routing Design route_design # Saving Run write_checkpoint -force./${design}_route.dcp # Creating route reports report_timing_summary -max_paths 10 -nworst 1 -input_pins - report_drc -file ${DESIGN}_drc_route.rpt exit run_vivado_bitstream.tcl # Gathering TCL Arg set DESIGN [lindex $argv 0] read_checkpoint./${design}_route.dcp # Create bitstream write_bitstream -force ${DESIGN}.bit exit Note: This flow exits and reenters Vivado for the defined steps in the makefile. While this allows greater run control from the make infrastructure, it is not the most efficient in execution time because you must exit and restart the software, and the reload the design for each defined step. Building this entire run in Tcl could be more efficient in runtime as the design can remain in memory from step to step if that is more desired than having makefile control. Migration Methodology Guide 18

19 Understanding the Differences in Messages Understanding the Differences in Messages The Vivado Design Suite uses the same ISE Design Suite concept of Info, Warning, and Error with unique identifying numbers for messages (for example, ngdbuild:604). Applications have messages with unique identifying numbers (HDL-189). Additionally, the Vivado Design Suite includes two new message types: Status and Critical Warning. Status provides information about the current tool process. Critical Warnings in Vivado Design Suite are equivalent to Errors in the ISE Design Suite, except the Vivado design process is not stopped. Critical Warnings in the design are upgraded to Error at the bitstream generation (write_bitstream) stage, which stops the design process. RECOMMENDED: Xilinx recommends that you resolve any Critical Warnings before moving forward with your design. Table 2-4 shows the five message types in the Vivado Design Suite, indicates whether use intervention is required, and describes the message purpose. Table 2-4: Vivado Design Suite Message Types Type Intervention? Purpose STATUS No Provides general status of the process and feedback to the user regarding design processing. A STATUS message is the same as an INFO message, excluding the severity and message ID tag. INFO No Provides general status of the process and feedback to the user regarding design processing. An INFO message is the same as a STATUS message but includes a severity and message ID tag for filtering or searching. WARNING Optional Indicates that design results may be sub-optimal because constraints or specifications may not be applied as intended. The processing will continue to completion and valid results will be generated. CRITICAL WARNING Recommended Indicates a problem that will likely result in improperly functioning hardware and result in an ERROR later in the flow. The processing continues until an ERROR is encountered. ERROR Yes Indicates a problem that renders design results unusable and cannot be resolved without user intervention. Further processing is not possible. Migration Methodology Guide 19

20 Understanding Reporting Differences Understanding Reporting Differences In the ISE Design Suite, reports are automatically generated when each application is run through the design flow. This includes but is not limited to the following:.syr for xst.bld for ngdbuild.mrp for map.par for par.twr for trce.pwr for xpwr In the Vivado Design Suite, you can generate reports at any design stage. The benefits of on-demand report generation are: Better runtime: You can better manage runtime by generating reports only when needed. More available reports: At any point in the design flow, you can generate a report, making more reports available to you. For example, you can generate a utilization report for your design post-synthesis, post-optimization or post-route to see current information. When you use Project Mode in the Vivado IDE, a fixed set of reports is automatically generated and can be accessed from the Reports window. When you use Non-Project Mode with Tcl commands or a script, you must add Tcl reporting commands to generate reports at stages where you require them while the design is in memory. Specific report_* commands report different types of information, for example, utilization, timing, and DRC results. By default, the report output is sent to the tool transcript and the vivado.log file, but it can also be directed to a file. For a list of reports and their descriptions, type help -category report at the Tcl Command prompt. Migration Methodology Guide 20

21 Understanding Log File Differences Table 2-5 shows the relationship between ISE Design Suite report information and Vivado Design Suite reporting commands. Table 2-5: ISE Design Suite Reports and Vivado Design Suite Reports ISE Design Suite Information (Report) Vivado Design Suite Command Utilization Information (.syr,.mrp,.par) I/O Information (.pad) Timing Information (.par,.twr) Power Information (.pwr) report_utilization, report_clock_utilization report_io report_timing, report_timing_summary report_power Understanding Log File Differences The ISE Design Suite tools generate status and output information as a part of the individual command log files. For instance, the output status and progress of the Map executable is placed into the.map file where the output of PAR is placed in the.par file. The Vivado Design Suite uses a single log file to capture all tool commands and output. The file is named vivado.log by default, which you can change by using the vivado log option. The Vivado Design Suite log file displays flow progress using phases. Each phase has a name and number and a single-line performance summary. Following is an example: report_timing: Time (s): cpu = 00:03:57 ; elapsed = 00:03:55. Memory (MB): peak = ; gain = Where: cpu is total run time for all processors. elapsed is the actual time spent running the process. peak is the maximum memory usage up to that particular design step. gain is the incremental contribution of a design step to the peak memory usage. For example, report_timing added MB to the peak memory usage in the example above. Migration Methodology Guide 21

22 Chapter 3 Migrating UCF Constraints to XDC Overview The Vivado Integrated Design Environment (IDE) does not support the User Constraint File (UCF) constraints used in the ISE Design Suite. You must migrate the designs with UCF constraints to the Xilinx Design Constraint (XDC) format. For information on XDC constraints, see the Vivado Design Suite User Guide: Using Constraints (UG903) [Ref 3]. For information on UCF constraints, see the Constraints Guide (UG625) [Ref 4]. For information on timing see: Vivado Design Suite Tutorial: Design Analysis and Closure Techniques (UG938) [Ref 9] Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906) [Ref 8] As with UCF, XDC consists of: Timing constraints, for which XDC timing constraints are based on the Synopsys Design Constraint (SDC) Physical constraints IMPORTANT: This method is good for migrating physical constraints, such as I/Os; timing constraints are often better recreated from scratch. Differences Between XDC and UCF Constraints The fundamental differences between XDC and UCF constraints are: XDC is a sequential language, with clear precedence rules. UCF constraints are typically applied to nets, for which XDC constraints are typically applied to pins, ports, and cell objects. UCF PERIOD constraints and XDC create_clock command are not always equivalent and can lead to different timing results. Migration Methodology Guide 22

23 UCF to XDC Mapping UCF by default does not time between asynchronous clock groups, while in XDC, all clocks are considered related and timed unless otherwise constrained (set_clock_groups). In XDC, multiple clocks can exist on the same object. UCF to XDC Mapping Table 3-1, shows the main mapping between UCF constraints to XDC commands. Table 3-1: UCF to XDC Mapping UCF TIMESPEC PERIOD OFFSET = IN <x> BEFORE <clk> OFFSET = OUT <x> BEFORE <clk> FROM:TO TS_ *2 FROM:TO TIG NET clk_p LOC = AD12 NET clk_p IOSTANDARD = LVDS SDC create_clock create_generated_clock set_input_delay set_output_delay set_multicycle_path set_max_delay set_false_path set_property LOC AD12 [get_ports clk_p] set_property IOSTANDARD LVDS [get_ports clk_p] Constraint Sequence Whether you use one or more XDC files for your design, Xilinx recommends that you organize your constraints in the following sequence: ## Timing Assertions Section # Primary clocks # Virtual clocks # Generated clocks # Clock Groups # Input and output delay constraints ## Timing Exceptions Section (sorted by precedence) # False Paths # Max Delay / Min Delay # Multicycle Paths # Case Analysis # Disable Timing Migration Methodology Guide 23

24 Converting UCF to XDC in the PlanAhead Tool ## Physical Constraints Section # located anywhere in the file, preferably before or after the timing constraints # or stored in a separate XDC file Converting UCF to XDC in the PlanAhead Tool The PlanAhead tool assists in converting UCF constraints to XDC when you open an ISE Design Suite or PlanAhead tool project that contains UCF constraints. When a design is loaded into the database, you can use the write_xdc command to convert a large percentage of the UCF constraints. You need to manually verify the output file, and you will most likely need to manually convert some constraints to XDC to ensure that all the design constraints are correct. The Tcl command write_xdc requires that a synthesized netlist be open and one or more UCF files loaded. From the PlanAhead tool, do the following: 1. Open your project that contains UCF constraints. 2. Click Open Synthesized Design. 3. In the Tcl Console, type: write_xdc filename.xdc. The write_xdc command is not a file converter. The command writes out the constraints that were successfully applied to the design as an XDC file. The output XDC file contains: A comment with the file and line number from the UCF for each converted UCF. A comment for each conversion not done. IMPORTANT: Pay attention to Critical Warnings that indicate which constraints were not successfully converted. This conversion is only a starting point for migration to XDC-based constraints. RECOMMENDED: Xilinx recommends that XDC timing constraints be created without using the conversion process, because fundamental differences between UCF and XDC make automation less than optimal. You can use the PlanAhead tool for converting UCF is best for physical constraints and basic timing constraints. Timing constraints for simple clock definitions and IO delays typically translate well. Migration Methodology Guide 24

25 TimeGROUP IMPORTANT: Xilinx recommends that you manually convert timing exceptions. Many will not translate and others can produce sub-optimal results. Fundamental differences between the timer in the Vivado IDE (XDC/SDC) and the timer in ISE Design Suite (UCF) make direct translation impossible. For that reason the UCF constraint must be re-evaluated and a new approach might be required with XDC. Conversion can be done with an elaborated RTL design; however, many objects referenced in a typical UCF will not exist at that stage and thus will not be applied to the database. Only constraints that are successfully applied to the database can be written out as XDC. Thus simple clock and IO delay constraints typically can be translated from an elaborated RTL design. TimeGROUP You can use Tcl variables with timing exceptions to accomplish the same effect as an INST/TNM and a TIMESPEC. The following example illustrates the point. : INST "DUT/BLOCK_A/data_reg[*] TNM = "from_data_reg_0"; INST "DUT/BLOCK_A/addr_reg[*] TNM = "from_data_reg_0"; INST "DUT/BLOCK_B/data_sync[*] TNM = "to_data_reg_0"; INST "DUT/BLOCK_B/addr_sync[*] TNM = "to_data_reg_0"; TIMESPEC "TS_MCP" = FROM "from_data_reg_0" TO "to_data_reg_0" TS_FSCLK * 3; Tcl Equivalent: set from_data_reg_0 [get_cells {DUT/BLOCK_A/data_reg[*] DUT/BLOCK_A/addr_reg[*]}]; set to_data_reg_0 [get_cells {DUT/BLOCK_B/data_sync[*] DUT/BLOCK_B/addr_sync[*]}]; set_multicycle_path -setup 3 -from $from_data_reg_0 -to $to_data_reg_0; set_multicycle_path -hold 2 -from $from_data_reg_0 -to $to_data_reg_0; Timing Constraints The following ISE Design Suite timing constraints can be represented as XDC timing constraints in the Vivado Design Suite. Each constraint description contains a UCF example and the equivalent XDC example. Migration Methodology Guide 25

26 Timing Constraints UCF and XDC differ when creating clocks on a net that is not directly connected to the boundary of the design (such as port). In XDC, when defining a primary clock with create_clock on a net the source point is the driving pin of the net. The clock insertion delay before that point is ignored. This can be a problem when timing the clock with another related clock; the skew will not be accurate. The create_clock must be used where the clock trees originate; not in the middle of the design (for example, input port or GT clock output pin). Only generated clocks should be created in the middle of the design. Clock Constraints Period NET "clka" TNM_NET = "clka"; TIMESPEC "TS_clka" = PERIOD "clka" ns HIGH 50.00%; create_clock -name clka -period waveform { } [get_ports clka] Period Constraints with Uneven Duty Cycle NET "clka" TNM_NET = "clka"; TIMESPEC "TS_clka" = PERIOD "clka" ns HIGH 40.00%; create_clock -name clka -period waveform { } [get_ports clka] Generated Clocks Constraints NET "gen_clk" TNM_NET = "gen_clk"; TIMESPEC "TS_gen_clk" = PERIOD "gen_clk" "TS_clka" * HIGH 50.00%; create_generated_clock -source [get_ports clka] -name gen_clk -multiply_by 2 [get_ports gen_clk] Period Constraints with LOW Keyword NET "clka" TNM_NET = "clka"; TIMESPEC "TS_clka" = PERIOD "clka" ns LOW 50.00%; create_clock -name clka -period waveform { } [get_ports clka] Net PERIOD Constraints NET "clk_bufg" PERIOD = 10 ns; Migration Methodology Guide 26

27 Timing Constraints Net PERIOD Constraints OFFSET IN create_clock -name clk_bufg -period 10 -waveform {0 5} [get_pins clk_bufg/o} Note: Unless there is specific reason to define the clock on bufg/o, define it at an upstream top-level port. BEFORE AFTER OFFSET = IN 8 BEFORE clka; set_input_delay -clock clka 2 [all_inputs] Note: This assumes the clock period is 10 ns. OOFFSET = IN 2 AFTER clka; set_input_delay -clock clka 2 [all_inputs] Note: This assumes the clock period is 10 ns. BEFORE an Input Port Net NET enable OFFSET = IN 8 BEFORE clka; set_input_delay 2 [get_ports enable] BEFORE an Input Port Bus Note: This assumes the clock period is 10 ns. INST "processor_data_bus[*]" TNM = "processor_bus"; TIMEGRP "processor_bus" OFFSET = IN 8ns BEFORE "clka"; set_input_delay 2 [get_ports {processor_data_bus[*]}] Note: Offset is applied to ports only. To TIMEGROUP INST "input_ffs[*]" TNM = "input_ffs"; OFFSET = IN 8ns BEFORE "clka" TIMEGRP "input_ffs"; Manual conversion is required. For more information, see TimeGROUP, page 25. FALLING/RISING Edge OFFSET = IN 8ns BEFORE "clka" FALLING; set_input_delay -clock clka 2 [all_inputs] Note: This assumes the clock period is 10 ns. Migration Methodology Guide 27

28 . Timing Constraints LOW/HIGH Keyword OFFSET OUT OFFSET = IN 8ns BEFORE "clka" HIGH; Requires manual conversion. Note: HIGH/LOW keywords are precursors to RISING/FALLING. RISING/FALLING is the preferred method. VALID Keyword OFFSET = IN 1ns VALID 2ns BEFORE clka; set_input_delay -clock clka -max 9 [all_inputs] set_input_delay -clock clka -min 1[all_inputs] Note: This assumes the clock period is 10 ns AFTER BEFORE Output Net OFFSET = OUT 12 AFTER clkc; set_output_delay -clock clkc 8 [all_outputs] Note: This assumes the clock period is 20 ns. OFFSET = OUT 8 BEFORE clkc; set_output_delay -clock clkc 8 [all_outputs] Note: This assumes the clock period is 20 ns NET out_net OFFSET = OUT 12 AFTER clkc; set_output_delay 8 [get_port out_net] Note: This assumes the clock period is 20 ns Group of Outputs TIMEGRP outputs OFFSET = OUT 12 AFTER clkc; set_output_delay -clock clkc 8 [get_ports outputs*] Note: This assumes the clock period is 20 ns. From a TIMEGROUP OFFSET = OUT 1.2 AFTER clk TIMEGRP from_ffs; Manual conversion is required. Migration Methodology Guide 28

29 Timing Constraints FALLING/RISING Edges OFFSET = OUT 12 AFTER clkc FALLING; set_output_delay -clock clkc -clock_fall 8 [all_outputs] LOW Keyword OFFSET = OUT 12 AFTER clkc LOW; Requires manual conversion. Note: HIGH/LOW keywords are precursors to RISING/FALLING. RISING/FALLING is the preferred method. REFERENCE_PIN TIMEGRP mac_ddr_out; OFFSET = OUT AFTER clk REFERENCE_PIN clk_out RISING; Requires manual conversion. Note: REFERENCE_PIN acts as a reporting switch to instruct TRACE to output a bus skew report. The Vivado Design Suite does not support this feature. From:To Constraints Generally, UCF From:To constraints are converted to either set_max_delay or set_min_delay XDC constraints, with the -from, -to and -through design-dependent arguments. The intent of UCF constraints is to use the equivalent XDC constraints. While most UCF constraints are net-based, XDC constraints must be constructed to ports and pins. Helpful XDC commands for these constraints are: all_fanout, get_cells, and get_pins as well as the -from, -to, and -through arguments. Assigning Timing Group to an Area Group TIMEGRP clock_grp = AREA_GROUP clock_ag; The Vivado Design Suite does not support this constraint in XDC. EXCEPT TIMEGRP my_group = FFS EXCEPT your_group; The Vivado Design Suite does not support this constraint in XDC Migration Methodology Guide 29

30 Timing Constraints Between Groups TIMESPEC TS_TIG = FROM reset_ff TO FFS TIG; Manual conversion is required. Construct a set_false_path that covers the desired paths. By Net By Instance By Pin NET reset TIG; set_false_path -through [get_nets reset] A better approach is to find the primary reset port and use: set_false_path -from [get_ports reset_port] INST reset TIG; set_false_path -from [get_cells reset] set_false_path -through [get_cells reset] set_false_path -to [get_cells reset] PIN ff.d TIG; set_false_path -to [get_pins ff/d] set_false_path -from [get_pins ff/q] set_false_path -through [get_pins lut/i0] Specific Time Constraints NET reset TIG = TS_fast TS_even_faster; The Vivado Design Suite does not support this constraint in XDC. Note: Constraint-specific TIG tries to disable timing through the net, but only for analysis of the two referenced constraints MAXSKEW MAXDELAY NET local_clock MAXSKEW = 2ns; The Vivado Design Suite does not support this constraint in XDC. NET local_clock MAXDELAY = 2ns; The Vivado Design Suite does not support this constraint in XDC. Migration Methodology Guide 30

31 Physical Constraints Physical Constraints Following are the ISE Design Suite physical constraints that can be represented as XDC constraints in the Vivado Design Suite. Each constraint description contains: Target object type Constraint value type UCF example Equivalent XDC example Placement-Related Constraints AREA_GROUP Cells String INST bmg0 AREA_GROUP = AG1; create_pblock ag1; add_cells_to_pblock [get_pblocks ag1] [get_cells [list bmg0]] AREA_GROUP RANGE SLICE Area groups and Pblocks SLICE_XnYn[:SLICE_XnYn] AREA_GROUP AG1 RANGE = SLICE_X0Y44:SLICE_X27Y20; resize_pblock [get_pblocks ag1] -add {SLICE_X0Y44:SLICE_X27Y20} RAMB18 Area groups and Pblocks RAMB18_XnYn:RAMB18_XnYn AREA_GROUP AG1 RANGE = RAMB18_X0Y86:RAMB18_X3Y95; resize_pblock [get_pblocks ag1] -add {RAMB18_X0Y86:RAMB18_X3Y95} Migration Methodology Guide 31

32 Physical Constraints RAMB36 CLOCKREGION (1) Area groups and Pblocks RAMB36_XnYn:RAMB36_XnYn AREA_GROUP AG1 RANGE = RAMB36_X0Y11:RAMB36_X3Y18; resize_pblock [get_pblocks ag1] -add {RAMB36_X0Y11:RAMB36_X3Y18} Area groups and Pblocks CLOCKREGION_XnYn area_group ag1 range = CLOCKREGION_X0Y0; resize_pblock [get_pblocks ag1] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0} CLOCKREGION (2) Area groups and Pblocks CLOCKREGION_XnYn[:CLOCKREGION_XnYn] area_group ag1 range = CLOCKREGION_X0Y0:CLOCKREGION_X1Y0; resize_pblock [get_pblocks ag1] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0} CLOCKREGION (3) Area groups and Pblocks CLOCKREGION_XnYn,CLOCKREGION_XnYn,... area_group ag1 range = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0; resize_pblock [get_pblocks ag1] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} Migration Methodology Guide 32

33 Physical Constraints DSP48 Area groups and Pblocks DSP48_XnYn:DSP48_XnYn AREA_GROUP D1 RANGE = DSP48_X2Y0:DSP48_X2Y9; resize_pblock [get_pblocks D1] -add {DSP48_X2Y0:DSP48_X2Y9} BUFGCTRL BUFHCE BUFR Area groups and Pblocks BUFGCTRL_XnYn:BUFGCTRL_XnYn AREA_GROUP ag1 range = BUFGCTRL_X0Y24:BUFGCTRL_X0Y31; resize_pblock [get_pblocks ag1] -add {BUFGCTRL_X0Y24:BUFGCTRL_X0Y31} Area groups and Pblocks BUFHCE_XnYn:BUFHCE_XnYn AREA_GROUP ag1 range = BUFHCE_X0Y72:BUFHCE_X1Y77; resize_pblock [get_pblocks ag1] -add {BUFHCE_X0Y72:BUFHCE_X1Y77} Area groups and Pblocks BUFR_XnYn:BUFR_XnYn AREA_GROUP ag1 range = BUFR_X0Y20:BUFR_X1Y23; resize_pblock [get_pblocks ag1] -add {BUFR_X0Y0:BUFR_X1Y2} BUFIO Area groups and Pblocks BUFIO_XnYn:BUFIO_XnYn AREA_GROUP ag1 range = BUFIO_X0Y8:BUFIO_X0Y11; resize_pblock [get_pblocks ag1] -add {BUFIO_X0Y8:BUFIO_X0Y11} Migration Methodology Guide 33

34 Physical Constraints IOB Range IN_FIFO Area groups and Pblocks IOB_XnYn:IOB_XnYn AREA_GROUP ag1 range = IOB_X0Y341:IOB_X1Y349; resize_pblock [get_pblocks ag1] -add {IOB_X0Y341:IOB_X1Y349} Area groups and Pblocks IN_FIFO_XnYn:IN_FIFO_XnYn AREA_GROUP ag1 range = IN_FIFO_X0Y24:IN_FIFO_X1Y27; resize_pblock [get_pblocks ag1] -add {IN_FIFO_X0Y24:IN_FIFO_X1Y27} OUT_FIFO Area groups and Pblocks OUT_FIFO_XnYn:OUT_FIFO_XnYn AREA_GROUP ag1 range = OUT_FIFO_X0Y24:OUT_FIFO_X1Y27; resize_pblock [get_pblocks ag1] -add {OUT_FIFO_X0Y24:OUT_FIFO_X1Y27} ILOGIC OLOGIC Area groups and Pblocks ILOGIC_XnYn:ILOGIC_XnYn AREA_GROUP ag1 range = ILOGIC_X0Y76:ILOGIC_X0Y79; resize_pblock [get_pblocks ag1] -add {ILOGIC_X0Y76:ILOGIC_X0Y79} Area groups and Pblocks OLOGIC_XnYn:OLOGIC_XnYn AREA_GROUP ag1 range = OLOGIC_X0Y76:OLOGIC_X0Y79; resize_pblock [get_pblocks ag1] -add {OLOGIC_X0Y76:OLOGIC_X0Y79} Migration Methodology Guide 34

35 Physical Constraints LOC IOB Port nets IOB site NET p[0] LOC = H1; set_property PACKAGE_PIN H1 [get_ports p[0]] TIP: To assign pins in the Vivado Design Suite, use the PACKAGE_PIN port property, and not the LOC property which is used for cells. SLICE (1) SLICE (2) RAMB18 RAMB36 Cells Site range INST a_reg[*] LOC = SLICE_X25Y*; The Vivado Design Suite does not support this constraint in XDC. Cells SLICE_XnYn INST a_reg[0] LOC = SLICE_X4Y4; set_property LOC SLICE_X4Y4 [get_cells a_reg[0]] Cells RAMB18_XnYn INST ram0 LOC = RAMB18_X0Y5; set_property LOC RAMB18_X0Y5 [get_cells ram0] Cells RAMB36_XnYn INST ram0 LOC = RAMB36_X0Y0; set_property LOC RAMB36_X0Y0 [get_cells ram0] Migration Methodology Guide 35

36 Physical Constraints DSP48 Cells DSP48_XnYn INST dsp0 LOC = DSP48_X0Y10; set_property LOC DSP48_X0Y10 [get_cells dsp0] BUFGCTRL BUFHCE BUFR BUFIO Cells BUFGCTRL_XnYn INST cb[0] LOC = BUFGCTRL_X0Y24; set_property LOC BUFGCTRL_X0Y24 [get_cells cb[0]] Cells BUFHCE_XnYn INST cb[0] LOC = BUFHCE_X0Y72; set_property LOC BUFHCE_X0Y72 [get_cells cb[0]] Cells BUFR_XnYn INST cb[0] LOC = BUFR_X0Y20; set_property LOC BUFR_X0Y20 [get_cells cb[0]] Cells BUFIO_XnYn INST cb[0] LOC = BUFIO_X0Y8; set_property LOC BUFIO_X0Y8 [get_cells cb[0]] Migration Methodology Guide 36

37 Physical Constraints IOB Cells IOB_XnYn INST ib[0] LOC = IOB_X0Y341; set_property LOC IOB_X0Y341 [get_cells ib[0]] IN_FIFO OUT_FIFO ILOGIC OLOGIC Cells IN_FIFO_XnYn INST infifo_inst LOC = IN_FIFO_X0Y24; set_property LOC IN_FIFO_X0Y24 [get_cells infifo_inst] Cells OUT_FIFO_XnYn INST outfifo_inst LOC = OUT_FIFO_X0Y24; set_property LOC OUT_FIFO_X0Y24 [get_cells outfifo_inst] Cells ILOGIC_XnYn INST ireg LOC = ILOGIC_X0Y76;k set_property LOC ILOGIC_X0Y76 [get_cells ireg] Cells OLOGIC_XnYn INST oreg LOC = OLOGIC_X0Y76 set_property LOC OLOGIC_X0Y76 [get_cells oreg] Migration Methodology Guide 37

38 Physical Constraints IDELAY Cells IDELAY_XnYn INST idelay0 LOC = IDELAY_X0Y21; set_property LOC IDELAY_X0Y21 [get_cells idelay0] IDELAYCTRL Cells IDELAYCTRL_XnYn INST idelayctrl0 LOC = IDELAYCTRL_X0Y0; set_property LOC IDELAYCTRL_X0Y0 [get_cells idelayctrl0] BEL A5LUT, B5LUT, C5LUT, D5LUT Cells A5LUT, B5LUT, C5LUT, D5LUT INST a0 BEL = A5LUT; set_property BEL A5LUT [get_cells a0] A6LUT, B6LUT, C6LUT, D6LUT Cells A6LUT, B6LUT, C6LUT, D6LUT INST a0 BEL = D6LUT; set_property BEL D6LUT [get_cells a0] AFF, BFF, CFF, DFF Cells AFF, BFF, CFF, DFF INST a_reg[0] BEL = CFF; set_property BEL CFF [get_cells a_reg[0]] Migration Methodology Guide 38

39 Physical Constraints A5FF, B5FF, C5FF, D5FF Cells A5FF, B5FF, C5FF, D5FF INST a_reg[0] BEL = B5FF; set_property BEL B5FF [get_cells a_reg[0]] F7AMUX, F7BMUX Cells F7AMUX, F7BMUX INST m0 BEL = F7BMUX; set_property BEL F7BMUX [get_cells m0] IOB TRUE FALSE FORCE FF cells TRUE INST a1_reg[*] IOB = TRUE; set_property IOB TRUE [get_cells b1_reg[*]] FF cells FALSE INST b1_reg[*] IOB = FORCE; set_property IOB TRUE [get_cells a1_reg[*]] FF cells FORCE INST q_reg[*] IOB = FALSE; set_property IOB TRUE [get_cells q_reg[*]] Note: The Vivado Design Suite does not support this constraint in XDC. Use TRUE instead. Migration Methodology Guide 39

40 Physical Constraints H_SET Cells Tool-generated string N/A N/A Note: For more information, see Relative Location (RLOC) in the Constraints Guide (UG625). In the Vivado Design Suite, H_SET cells have a property called RPM. U_SET RLOC RLOC_ORIGIN Cells String INST u0 U_SET = h0; (usually set in UCF) The Vivado Design Suite does not support this constraint in XDC. U_SET must be placed in HDL code as an attribute. For more information, see Relative Location (RLOC) in the Constraints Guide (UG625). Cells XnYn INST u0 RLOC = X2Y1; The Vivado Design Suite does not support this constraint in XDC. RLOC must be placed in HDL code as an attribute. For more information, see Relative Location (RLOC) in the Constraints Guide (UG625). Cells XnYn INST u0 RLOC_ORIGIN = X144Y255; The Vivado Design Suite does not support this constraint in XDC. RLOC_ORIGIN must be placed in HDL code as an attribute. For more information, see Relative Location (RLOC) in the Constraints Guide (UG625). Migration Methodology Guide 40

41 Physical Constraints RPM_GRID USE_RLOC RLOC_RANGE BLKNM HBLKNM Cells GRID INST u0 RPM_GRID = GRID; The Vivado Design Suite does not support this constraint in XDC. RPM_GRID must be placed in HDL code as an attribute. For more information, see Relative Location (RLOC) in the Constraints Guide (UG625). Cells TRUE, FALSE INST u0 USE_RLOC = FALSE; The Vivado Design Suite does not support this constraint in XDC. Cells XnYn:XnYn INST u0 RLOC_RANGE = X1Y1:X3Y3; The Vivado Design Suite does not support this constraint in XDC. Create a Pblock with the desired range, and add the RPM cells to the Pblock. Cells String INST u0 BLKNM = blk0; The Vivado Design Suite does not support this constraint in XDC. Cells, Nets String INST u0 HBLKNM = blk0; The Vivado Design Suite does not support this constraint in XDC. Migration Methodology Guide 41

42 Physical Constraints XBLKNM Cells, Nets String INST u0 XBLKNM = blk0; The Vivado Design Suite does not support this constraint in XDC. Use BEL PROHIBIT to keep out unrelated logic. HLUTNM LUTNM USE_LUTNM LUT cells String UCF is not allowed, only HDL. set_property HLUTNM h0 [get_cells {LUT0 LUT1}] LUT cells String UCF is not allowed, only HDL. set_property LUTNM h0 [get_cells {LUT0 LUT1}] LUT cells TRUE, FALSE INST lut0 USE_LUTNM = FALSE; The Vivado Design Suite does not support this constraint in XDC. Migration Methodology Guide 42

43 Physical Constraints CLOCK_DEDICATED_ROUTE TRUE(1) TRUE(1) FALSE(1) FALSE(2) BACKBONE(1) Nets TRUE net clk0 CLOCK_DEDICATED_ROUTE = TRUE; set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets clk0] Pins TRUE PIN clkbuf0.o CLOCK_DEDICATED_ROUTE = TRUE; set_property CLOCK_DEDICATED_ROUTE TRUE [get_pins clkbuf0/o] Nets FALSE NET clk0 CLOCK_DEDICATED_ROUTE = FALSE; set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk0] Pins FALSE PIN clkbuf0.o CLOCK_DEDICATED_ROUTE = FALSE; set_property CLOCK_DEDICATED_ROUTE FALSE [get_pins clkbuf0/o] Nets BACKBONE NET clk0 CLOCK_DEDICATED_ROUTE = BACKBONE; set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk0] Migration Methodology Guide 43

44 Physical Constraints BACKBONE(2) Pins BACKBONE PIN clkbuf0.o CLOCK_DEDICATED_ROUTE = BACKBONE; set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins clkbuf0/o] I/O-Related Constraints HIODELAY_GROUP IODELAY_GROUP IDELAY and IDELAYCTRL cells String INST idelay0 HIODELAY_GROUP = group0; set_property HIODELAY_GROUP group0 [get_cells idelay0] IDELAY and IDELAYCTRL cells String INST idelay0 IODELAY_GROUP = group0; set_property IODELAY_GROUP group0 [get_cells idelay0] DCI_VALUE I/O buffer cells Integer. Resistance in Ohms INST a_ibuf[0]_inst DCI_VALUE = 75; set_property DCI_VALUE 75 [get_cells {a_ibuf[0]_inst}] DIFF_TERM I/O buffer cells Boolean INST a_ibuf[0]_inst DIFF_TERM = TRUE; set_property DIFF_TERM true [get_cells {a_ibuf[0]_inst}] Migration Methodology Guide 44

45 Physical Constraints DRIVE Inout and output buffer cells Integer: 2, 4, 6, 8, 12, 16, 24 INST q_obuf[0]_inst DRIVE = 24; set_property DRIVE 24 [get_ports q[0]] LVTTL allows a value of 24. IOSTANDARD SLEW FAST SLOW Constraint Values I/O buffer cells I/O standard string INST q_obuf[0]_inst IOSTANDARD = LVCMOS25; set_property IOSTANDARD LVCMOS25 [get_ports q[0]] For more information, see the Constraints Guide (UG625) Inout and output buffer cells SLOW or FAST INST q_obuf[0]_inst SLEW = FAST; set_property SLEW FAST [get_ports q[0]] Inout and output buffer cells N/A INST q_obuf[0]_inst FAST; set_property SLEW FAST [get_ports q[0]] Inout and output buffer cells N/A INST q_obuf[0]_inst SLOW; set_property SLEW SLOW [get_ports q[0]] Migration Methodology Guide 45

46 Physical Constraints PORTS IN_TERM OUT_TERM IOBDELAY BOTH Ports NONE UNTUNED_SPLIT_40 UNTUNED_SPLIT_50 UNTUNED_SPLIT_60 NET a[0] IN_TERM = UNTUNED_SPLIT_50; set_property IN_TERM UNTUNED_SPLIT_50 [get_ports [list clk]] Ports NONE UNTUNED_25 UNTUNED_50 UNTUNED_75 net q[0] OUT_TERM = UNTUNED_50; set_property OUT_TERM UNTUNED_50 [get_ports q[0]] Port nets NONE net b[0] IOBDELAY = NONE; set_property IOBDELAY NONE [get_nets b[0]] Note: You cannot set IOBDELAY on ports. However, you can set IOBDELAY on cells such as input buffers. Port nets BOTH net b[0] IOBDELAY = BOTH; set_property IOBDELAY BOTH [get_nets b[0]] Note: You cannot set IOBDELAY on ports. However, you can set IOBDELAY on cells such as input buffers. Migration Methodology Guide 46

47 Physical Constraints IBUF Port nets IBUF net b[0] IOBDELAY = IBUF; set_property IOBDELAY IBUF [get_nets b[0]] Note: You cannot set IOBDELAY on ports. However, you can set IOBDELAY on cells such as input buffers. IFD Port nets IFD net b[0] IOBDELAY = IFD; set_property IOBDELAY IFD [get_nets b[0]] Note: You cannot set IOBDELAY on ports. However, you can set IOBDELAY on cells such as input buffers KEEPER Port nets TRUE FALSE YES NO NET n1 KEEPER = TRUE; set_property KEEPER true [get_ports n1] PULLDOWN Port nets TRUE FALSE YES NO NET n1 PULLDOWN = TRUE; set_property PULLDOWN true [get_ports n1] Migration Methodology Guide 47

48 Physical Constraints PULLUP Port nets TRUE FALSE YES NO NET n1 PULLUP = TRUE; set_property PULLUP true [get_ports n1] VCCAUX_IO Ports NORMAL HIGH DONTCARE NET d[0] VCCAUX_IO = HIGH; set_property VCCAUX_IO HIGH [get_ports d[0]] Miscellaneous Net-Related Constraints KEEP Nets TRUE FALSE net x_int KEEP = TRUE; set_property DONT_TOUCH true [get_nets x_int] SAVE NET FLAG Nets N/A net x_int S; set_property DONT_TOUC true [get_nets x_int] Migration Methodology Guide 48

49 Physical Constraints KEEP_HIERARCHY Cells TRUE FALSE YES NO INST u1 KEEP_HIERARCHY = TRUE; set_property DONT_TOUCH true [get_cells u1] LOCK_PINS LUT cell CSV string: I[0-5]:A[6-1] INST LUT1 LOCK_PINS = I3:A6, I2:A5; set_property LOCK_PINS {I3:A6 I2:A5} [get_cells LUT1] ROUTE Nets Directed Routing String (DIRT) NET n85 ROUTE={2;1;-4!-1;-53320;...16;-8!}; set_property FIXED_ROUTE {EE2BEG0 NR1BEG0 CLBLL_LL_AX} [get_nets n85] Note: ISE Design Suite directed routing strings and Vivado Design Suite net route properties are incompatible. Vivado uses a unique, un-encoded format Migration Methodology Guide 49

50 Physical Constraints Configuration-Related Constraints CONFIG PROHIBIT Pin site Sites Pin site CONFIG PROHIBIT = K24, K26, K27, K28; set_property PROHIBIT true [get_sites {K24 K26 K27 K28}] Bank number RAM(1) RAM(2) Sites Bank number CONFIG PROHIBIT = BANK34, BANK35, BANK36; set_property PROHIBIT true [get_sites -of [get_iobanks ]] Sites RAMs CONFIG PROHIBIT = RAMB18_X0Y0; set_property PROHIBIT true [get_sites RAMB18_X0Y0] Sites RAMs CONFIG PROHIBIT = RAMB18_X0Y1, RAMB18_X0Y3, RAMB18_X0Y5; set_property PROHIBIT true [get_sites {RAMB18_X0Y1 RAMB18_X0Y3 RAMB18_X0Y5}] Note: The comma-separated list shown here uses RAM sites but can use any supported site type. Migration Methodology Guide 50

51 Physical Constraints RAM(3) Sites RAMs CONFIG PROHIBIT = RAMB36_X1Y1:RAMB36_X2Y2; set_property PROHIBIT true [get_sites -range {RAMB36_X1Y1 RAMB36_X2Y2}] RAM(4) DSP48 SLICE ILOGIC Sites RAMs CONFIG PROHIBIT = RAMB36_X3Y*; set_property PROHIBIT true [get_sites RAMB36_X3Y*] Sites DSP48s CONFIG PROHIBIT = DSP48_X0Y*; set_property PROHIBIT true [get_sites DSP48_X0Y*] Sites Slices CONFIG PROHIBIT = SLICE_X0Y0:SLICE_X47Y49; set_property PROHIBIT true [get_sites -range {SLICE_X0Y0 SLICE_X47Y49}] Sites ILOGIC CONFIG PROHIBIT = ILOGIC_X0Y0:ILOGIC_X0Y49; set_property PROHIBIT true [get_sites -range {ILOGIC_X0Y0 ILOGIC_X0Y49}] Migration Methodology Guide 51

52 Physical Constraints OLOGIC Sites OLOGIC CONFIG PROHIBIT = OLOGIC_X0Y0:OLOGIC_X0Y49; set_property PROHIBIT true [get_sites -range {OLOGIC_X0Y0 OLOGIC_X0Y49}] BUFGCTRL Sites BUFGCTRL CONFIG PROHIBIT = BUFGCTRL_X0Y0:BUFGCTRL_X0Y15; set_property PROHIBIT true [get_sites -range {BUFGCTRL_X0Y0 BUFGCTRL_X0Y15}] BUFR BUFIO BUFHCE Sites BUFR CONFIG PROHIBIT = BUFR_X0Y0:BUFR_X0Y3; set_property PROHIBIT true [get_sites -range {BUFR_X0Y0 BUFR_X0Y3}] Sites BUFIO CONFIG PROHIBIT = BUFIO_X0Y0:BUFIO_X0Y3; set_property PROHIBIT true [get_sites -range {BUFIO_X0Y0 BUFIO_X0Y3}] Sites BUFHCE CONFIG PROHIBIT = BUFHCE_X0Y0:BUFHCE_X1Y11; set_property PROHIBIT true [get_sites -range {BUFHCE_X0Y0 BUFHCE_X1Y11}] Migration Methodology Guide 52

53 Physical Constraints CONFIG INTERNAL_VREF_BANK Voltage I/O bank Voltage CONFIG INTERNAL_VREF_BANK14 = 0.75; set_property INTERNAL_VREF 0.75 [get_iobanks 14] NONE I/O bank NONE CONFIG INTERNAL_VREF_BANK0 = NONE; reset_property INTERNAL_VREF [get_iobanks 0] CONFIG DCI_CASCADE I/O banks Bank sequence CONFIG DCI_CASCADE = ; set_property DCI_CASCADE {15 14} [get_iobanks 17] CONFIG CONFIG_MODE M_SERIAL S_SERIAL Global M_SERIAL CONFIG CONFIG_MODE = M_SERIAL; set_property CONFIG_MODE M_SERIAL [current_design] Global S_SERIAL CONFIG CONFIG_MODE = S_SERIAL; set_property CONFIG_MODE S_SERIAL [current_design] Migration Methodology Guide 53

54 Physical Constraints B_SCAN Global B_SCAN CONFIG CONFIG_MODE = B_SCAN; set_property CONFIG_MODE B_SCAN [current_design] B_SCAN+READBACK Global B_SCAN+READBACK CONFIG CONFIG_MODE = B_SCAN+READBACK; set_property CONFIG_MODE B_SCAN+READBACK [current_design] M_SELECTMAP Global M_SELECTMAP CONFIG CONFIG_MODE = M_SELECTMAP; set_property CONFIG_MODE M_SELECTMAP [current_design] M_SELECTMAP+READBACK Global M_SELECTMAP+READBACK CONFIG CONFIG_MODE = M_SELECTMAP+READBACK; set_property CONFIG_MODE M_SELECTMAP+READBACK [current_design] S_SELECTMAP Global S_SELECTMAP CONFIG CONFIG_MODE = S_SELECTMAP; set_property CONFIG_MODE S_SELECTMAP [current_design] Migration Methodology Guide 54

55 Physical Constraints S_SELECTMAP+READBACK Global S_SELECTMAP+READBACK CONFIG CONFIG_MODE = S_SELECTMAP+READBACK; set_property CONFIG_MODE S_SELECTMAP+READBACK [current_design] S_SELECTMAP16 Global S_SELECTMAP16 CONFIG CONFIG_MODE = S_SELECTMAP16; set_property CONFIG_MODE S_SELECTMAP16 [current_design] S_SELECTMAP16+READBACK Global S_SELECTMAP16+READBACK CONFIG CONFIG_MODE = S_SELECTMAP16+READBACK; set_property CONFIG_MODE S_SELECTMAP16+READBACK [current_design] S_SELECTMAP32 Global S_SELECTMAP32 CONFIG CONFIG_MODE = S_SELECTMAP32; set_property CONFIG_MODE S_SELECTMAP32 [current_design] S_SELECTMAP32+READBACK Global S_SELECTMAP32+READBACK CONFIG CONFIG_MODE = S_SELECTMAP32+READBACK; set_property CONFIG_MODE S_SELECTMAP32+READBACK [current_design] Migration Methodology Guide 55

56 Physical Constraints SPIx1 Global SPIx1 CONFIG CONFIG_MODE = SPIx1; set_property CONFIG_MODE SPIx1 [current_design] SPIx2 SPIx4 Global SPIx2 CONFIG CONFIG_MODE = SPIx2; set_property CONFIG_MODE SPIx2 [current_design] Global SPIx4 CONFIG CONFIG_MODE = SPIx4; set_property CONFIG_MODE SPIx4 [current_design] BPI8 Global BPI8 CONFIG CONFIG_MODE = BPI8 ; set_property CONFIG_MODE BPI8 [current_design] BPI16 Global BPI16 CONFIG CONFIG_MODE = BPI16; set_property CONFIG_MODE BPI16 [current_design] Migration Methodology Guide 56

57 Physical Constraints POST_CRC Commands CONFIG POST_CRC DISABLE HALT CONTINUE Global ENABLE CONFIG POST_CRC = ENABLE; set_property POST_CRC ENABLE [current_design] Global DISABLE CONFIG POST_CRC = DISABLE; set_property POST_CRC DISABLE [current_design] Global HALT CONFIG POST_CRC_ACTION = HALT; set_property POST_CRC_ACTION HALT [current_design] Global CONTINUE CONFIG POST_CRC_ACTION = CONTINUE; set_property POST_CRC_ACTION CONTINUE [current_design] Migration Methodology Guide 57

58 Physical Constraints CORRECT_AND_CONTINUE Global CORRECT_AND_CONTINUE CONFIG POST_CRC_ACTION = CORRECT_AND_CONTINUE; set_property POST_CRC_ACTION CORRECT_AND_CONTINUE [current_design] CORRECT_AND_HALT Global CORRECT_AND_HALT CONFIG POST_CRC_ACTION = CORRECT_AND_HALT; set_property POST_CRC_ACTION correct_and_halt [current_design] CONFIG POST_CRC_FREQ Global Integer; frequency in MHz CONFIG POST_CRC_FREQ = 50; set_property POST_CRC_FREQ 50 [current_design] ENABLE DISABLE Global ENABLE CONFIG POST_CRC_INIT_FLAG = ENABLE; set_property POST_CRC_INIT_FLAG ENABLE [current_design] Global DISABLE CONFIG POST_CRC_INIT_FLAG = DISABLE; set_property POST_CRC_INIT_FLAG DISABLE [current_design] Migration Methodology Guide 58

59 Physical Constraints FIRST_READBACK Global FIRST_READBACK CONFIG POST_CRC_SOURCE = FIRST_READBACK; set_property POST_CRC_SOURCE FIRST_READBACK [current_design] PRE_COMPUTED Global PRE_COMPUTED CONFIG POST_CRC_SOURCE = PRE_COMPUTED; set_property POST_CRC_SOURCE PRE_COMPUTED [current_design] CONFIG VCCOSENSEMODEn VCCOSENSEMODEn I/O bank OFF, ALWAYSACTIVE, FREEZE CONFIG VCCOSENSEMODE15 = ALWAYSACTIVE; set_property VCCOSENSEMODE ALWAYSACTIVE [get_iobanks 15] CONFIG VREF CONFIG VREF Global Pin site CONFIG VREF = E11, F11; set_property VREF {E11 F11} [current_design] Migration Methodology Guide 59

60 Physical Constraints DEFAULT Commands Note: DEFAULT is not supported. I/O ports must be individually configured. DEFAULT FLOAT DEFAULT KEEPER Global Boolean DEFAULT FLOAT = TRUE; The Vivado Design Suite does not support this constraint in XDC. Global Boolean DEFAULT KEEPER = TRUE; The Vivado Design Suite does not support this constraint in XDC. DEFAULT PULLDOWN Global Boolean DEFAULT PULLDOWN = TRUE; The Vivado Design Suite does not support this constraint in XDC. DEFAULT PULLUP Global Boolean DEFAULT PULLUP = TRUE; The Vivado Design Suite does not support this constraint in XDC. Migration Methodology Guide 60

61 Chapter 4 Migrating Designs with Legacy IP to the Vivado Design Suite Overview Vivado Design Suite lets you migrate IP designs from the CORE Generator tool. You can also migrate IP to the latest version in the Vivado Design Suite. IMPORTANT: The Vivado Integrated Development Environment (IDE) requires that IP, instantiation, and port names are all lowercase. You must rename any uppercase or mixed-case filenames to lowercase. You can reuse IP in the Vivado Design Suite from the following sources: ISE Design Suite project using CORE Generator IP PlanAhead tool project using CORE Generator IP IP from a CORE Generator project IP from the Vivado IDE ADD IP option (.xci files) IP from the Embedded Development Kit (EDK) using the Package IP wizard. IMPORTANT: Before migrating your design to Vivado Design Suite, make sure that your design uses the latest version of available IP. When migrating a project with IP (either an older Vivado project, an ISE Design Suite xise project, or ISE project) or adding IP stored externally (either from Core Generator or Vivado) into Vivado, the IP can be in one of the following states: IP is current. The IP can be re-customized and output products can be generated. IP is locked because the version cannot be found in the catalog and there is an upgrade path available. If you do not wish to upgrade then there are two possible scenarios: If the output products were present when adding/importing they are available and can be used by Vivado. Migration Methodology Guide 61

62 Overview You cannot re-customize or generate any additional output products. If the output products required for synthesis (RTL) or implementation (NGC) are present you can proceed. Note: Simulation targets are required for behavioral simulation. If the output products are not present you cannot regenerate them in Vivado. You must either go back to the version of the software in which you created the IP and generate them, or upgrade to the latest version because there is an upgrade path. IP is locked because the version cannot be found in the catalog and there is no upgrade path available. There are two possible scenarios: If the output products were present when adding/importing they are available and can be used by Vivado. You cannot re-customize or generate any additional output products. If the output products required for synthesis (RTL) or implementation (netlist) are present you can proceed. Note: Simulation targets are required for behavioral simulation. If the output products are not present you cannot regenerate them. You would need to either go back to the version of the software you used to create the IP and generate them or recreate the IP using currently available IP in Vivado. This might require interface and design changes. TIP: When working with IP it is recommended that you keep the IP in a remote location outside of a project. This makes IPs more portable and easier to maintain. When customizing IP you should generate the output products. This would be an NGC for Core Generator and the synthesis, simulation, testbench, example, and possible other products for Vivado. This will allows you to have a usable IP for synthesis and/or implement even if the IP is removed from Vivado or if the IP requires an update in Vivado before re-customizing or generation can be done. Migration Methodology Guide 62

63 Migrating CORE Generator IP to the Vivado Design Suite Migrating CORE Generator IP to the Vivado Design Suite CORE Generator IP can be migrated to Vivado Design Suite in two steps: 1. Migrating a design using CORE Generator IP 2. Migrating IP to the latest version Step 1: Migrating Design Using CORE Generator IP Sources You can migrate a project with IP to Vivado Design Suite. To do so, you can do one of the following: Import an ISE Design Suite project into Vivado Design Suite project (see Importing a Project Navigator Project) Convert PlanAhead tool project to Vivado Design Suite project (see Converting a PlanAhead Tool Project) Add the IP core source files (.xco files) from a CORE Generator project to a Vivado Design Suite project Step 2: Migrating IP to Latest Version Use the latest version of IP in your design. To migrate IP, update your current IP as follows: 1. In the Sources window, click the IP Sources tab. 2. Right-click on an IP core source. 3. Select Upgrade IP from the popup menu. Note: You can re-customize IP after you upgrade the IP to the latest version. IMPORTANT: For IP that is no longer available in the IP catalog, you can continue to reuse existing IP netlists and sources, such as NGC netlist, simulation files, with Vivado synthesis and implementation flows. Migration Methodology Guide 63

64 Migrating EDK IP to the Vivado Design Suite Migrating EDK IP to the Vivado Design Suite You can convert an XPS processor core, or Pcore, to a Vivado Design Suite native IP for use in the IP integrator. To do so, you must manually run the Tools > Package IP. This process will create an IP-XACT definition file, component.xml, using the Package IP wizard. You can complete this through the Manage IP flow, working directly with the Pcore, or within your design project. For a complete procedure see "Lab 5: Converting Legacy EDK IP to use in IP Integrator" in the Vivado Design Suite Tutorial: Embedded Hardware Design (UG940) [Ref 10]. Migration Methodology Guide 64

65 Chapter 5 Migrating from XPS to IP Integrator Overview The Vivado Design Suite IP integrator lets you "stitch " together a design containing Xilinx IPs or your custom IP using a GUI environment. IMPORTANT: The Vivado IP integrator is the replacement for Xilinx Platform Studio (XPS) for embedded processor designs, including designs targeting Zynq devices and MicroBlaze processors. XPS only supports designs targeting MicroBlaze processors, not Zynq devices. Both IP integrator and XPS are available from the Vivado IDE. Just as you could use the ISE Design Suite Xilinx Platform Studio (XPS), you can use the IP Integrator in the Vivado Integrated Development Environment (IDE) to put together an embedded processor design for a Zynq All Progammable SoC or a Microblaze processor, and any associated peripherals. Note: This document contains information about the new Vivado IP integrator environment, which is a licensed early access feature in the release. Please contact your field applications engineer to obtain a license. You can migrate the following types of design types into the Vivado IP integrator: Zynq-7000 AP SoC processor-based designs Microblaze processor-based designs Custom IPs created in ISE or PlanAhead software IMPORTANT: Before migrating your design into the Vivado IDE, make sure that your design uses the latest version of IP available in the CORE Generator IP catalog. Migration Methodology Guide 65

66 Migrating a Zynq-7000 AP Soc Processor-Based Design Migrating a Zynq-7000 AP Soc Processor-Based Design You can migrate a Zynq-7000 processor-based design into the Vivado IDE using the following steps. 1. In XPS, open the design in XPS and click Export as shown in Figure 5-1. X-Ref Target - Figure 5-1 Figure 5-1: Zynq Configuration Window in XPS with Export Option 2. In the Export Zynq Processing System Configurations dialog box browse to, or type in the location in the Export Configuration to file field. You can also type in a brief description of the Zynq design in the Description of the configuration field as shown in Figure 5-2, page 67. Migration Methodology Guide 66

67 Migrating a Zynq-7000 AP Soc Processor-Based Design X-Ref Target - Figure 5-2 Figure 5-2: Export Configuration to File Dialog Box The XPS Export command generates an XML file. The following is an example of XML file generated for a Zynq-7000 processor from the Export command: Zynq Subsystem Configuration. </description> <Projinfo Part="xc7z030fbg676-1" DeviceSize="xc7z030" Package="fbg676" Speed="-1" /> <set param="pcw::i2c0::i2c0::io" value="mio " /> <set param="pcw::spi0::spi0::io" value="mio " /> <set param="pcw::i2c0::peripheral::enable" value="1" /> <set param="pcw::uart1::peripheral::enable" value="1" /> <set param="pcw::i2c1::peripheral::enable" value="1" /> <set param="pcw::i2c1::i2c1::io" value="mio " /> <set param="pcw::spi0::peripheral::enable" value="1" /> <set param="pcw::sd0::peripheral::enable" value="1" /> <set param="pcw::qspi::peripheral::enable" value="1" /> <set param="pcw::uart0::uart0::io" value="mio " /> <set param="pcw::uart0::peripheral::enable" value="1" /> <set param="pcw::mio::mio[1]::iotype" value="lvcmos 3.3V" /> <set param="pcw::mio::mio[0]::iotype" value="lvcmos 3.3V" /> <set param="pcw::usb0::peripheral::enable" value="1" /> <set param="pcw::uiparam::ddr::row_addr_count" value="14" /> <set param="pcw::uiparam::ddr::freq_mhz" value="500" /> <set param="pcw::wdt::wdt::io" value="mio " /> <set param="pcw::wdt::peripheral::enable" value="1" /> <set param="pcw::pjtag::pjtag::io" value="mio " /> <set param="pcw::pjtag::peripheral::enable" value="1" /> <set param="pcw::uiparam::ddr::partno" value="mt41k128m16 JT-125" /> <set param="pcw::uiparam::ddr::dqs_to_clk_delay_3" value="-0.058" /> <set param="pcw::uiparam::ddr::dqs_to_clk_delay_2" value="-0.008" /> <set param="pcw::uiparam::ddr::dqs_to_clk_delay_1" value="-0.004" /> <set param="pcw::uiparam::ddr::dqs_to_clk_delay_0" value="-0.005" /> <set param="pcw::uiparam::ddr::t_faw" value="40.0" /> <set param="pcw::uiparam::ddr::t_ras_min" value="35.0" /> <set param="pcw::uiparam::ddr::t_rc" value="48.75" /> <set param="pcw::uiparam::ddr::cwl" value="6" /> <set param="pcw::uiparam::ddr::speed_bin" value="ddr3_1066f" /> Migration Methodology Guide 67

68 Migrating a Zynq-7000 AP Soc Processor-Based Design <set param="pcw::uiparam::ddr::dram_width" value="16 Bits" /> <set param="pcw::gpio::v2.00.a::c_en_emio_gpio" value="0" /> <set param="pcw:gpio::emio_gpio::width" value="64" /> <set param="pcw::preset::fpga::speed" value="-1" /> <set param="pcw::preset::fpga::partnumber" value="xc7z030fbg676-1" /> <set param="pcw::ddr::v4.00.a::c_s_axi_hp3_highaddr" value="0x1fffffff" /> <set param="pcw::ddr::v4.00.a::c_s_axi_hp3_baseaddr" value="0x " /> <set param="pcw::ddr::v4.00.a::c_s_axi_hp2_highaddr" value="0x1fffffff" /> <set param="pcw::ddr::v4.00.a::c_s_axi_hp2_baseaddr" value="0x " /> <set param="pcw::ddr::v4.00.a::c_s_axi_hp1_highaddr" value="0x1fffffff" /> <set param="pcw::ddr::v4.00.a::c_s_axi_hp1_baseaddr" value="0x " /> <set param="pcw::ddr::v4.00.a::c_s_axi_hp0_highaddr" value="0x1fffffff" /> <set param="pcw::ddr::v4.00.a::c_s_axi_hp0_baseaddr" value="0x " /> <set param="pcw::uiparam::ddr::board_delay3" value="0.1" /> <set param="pcw::uiparam::ddr::board_delay2" value="0.082" /> <set param="pcw::uiparam::ddr::board_delay1" value="0.076" /> <set param="pcw::uiparam::ddr::board_delay0" value="0.075" /> <set param="pcw::uiparam::ddr::train_data_eye" value="1" /> <set param="pcw::uiparam::ddr::train_read_gate" value="1" /> <set param="pcw::uiparam::ddr::train_write_level" value="1" /> <set param="pcw::gpio::peripheral::enable" value="1" /> <set param="pcw::can::peripheral::freqmhz" value="100" /> <set param="pcw::spi::peripheral::freqmhz" value=" " /> <set param="pcw::fpga3::peripheral::freqmhz" value=" " /> <set param="pcw::fpga2::peripheral::freqmhz" value=" " /> </project> 3. Open the Vivado IDE, and create a new project using the same project settings as the ISE or PlanAhead project. a. Create a new project, for example zynq migration using the RTL project type. b. This example uses the board option Zynq702 to match to previous project. c. In the Vivado IP integrator, create a block design: for example, zynq subsystem. d. Add the Zynq Processing System7. e. Re-customize the design. The available configuration presets provides three option: - templates - Add exported xml - IO peripheral that were enable in previous project show all options are enabled. - Verify that the Zynq Processing System 7 was configured just as the previous project in ISE/planAhead. RECOMMENDED: This is an excellent time to see if you have the Vivado IP integrator license properly installed. In the Project Manager, you will see an IP integrator heading. If you do not see the IP integrator heading, the IP integrator license is missing or installed incorrectly. After the Vivado IDE IP integrator reads the XML file, it re-generates the appropriate constraints files. Migration Methodology Guide 68

69 Exporting a MicroBlaze Processor Design Processor Core (pcore IPs that were packaged in ISE/planAhead) can be migrated by re-packaging them into Vivado. See the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 7] for more information about designing with IP. Exporting a MicroBlaze Processor Design In XPS, a Microprocessor Hardware System (MHS) file describes the MicroBlaze configuration. IMPORTANT: You cannot migrate XMP files or MHS files for MicroBlaze designs. To migrate a MicroBlaze design, you must manually re-enter the properties within the MHS into the Vivado IP integrator. Look at the MHS and create a block diagram using the MHS as the map of parameters within the Vivado IP integrator. The following is an example code snippet of an MHS file: PORT processing_system7_0_mio = processing_system7_0_mio, DIR = IO, VEC = [53:0] PORT processing_system7_0_ps_srstb = processing_system7_0_ps_srstb, DIR = I PORT processing_system7_0_ps_clk = processing_system7_0_ps_clk, DIR = I, SIGIS = CLK PORT processing_system7_0_ps_porb = processing_system7_0_ps_porb, DIR = I PORT processing_system7_0_ddr_clk = processing_system7_0_ddr_clk, DIR = IO, SIGIS = CLK PORT processing_system7_0_ddr_clk_n = processing_system7_0_ddr_clk_n, DIR = IO, SIGIS = CLK PORT processing_system7_0_ddr_cke = processing_system7_0_ddr_cke, DIR = IO PORT processing_system7_0_ddr_cs_n = processing_system7_0_ddr_cs_n, DIR = IO PORT processing_system7_0_ddr_ras_n = processing_system7_0_ddr_ras_n, DIR = IO PORT processing_system7_0_ddr_cas_n = processing_system7_0_ddr_cas_n, DIR = IO PORT processing_system7_0_ddr_web_pin = processing_system7_0_ddr_web, DIR = O PORT processing_system7_0_ddr_addr = processing_system7_0_ddr_addr, DIR = IO, VEC = [14:0] PORT processing_system7_0_ddr_odt = processing_system7_0_ddr_odt, DIR = IO PORT processing_system7_0_ddr_drstb = processing_system7_0_ddr_drstb, DIR = IO, SIGIS = RST PORT processing_system7_0_ddr_dq = processing_system7_0_ddr_dq, DIR = IO, VEC = [31:0] BEGIN processing_system7 PARAMETER INSTANCE = processing_system7_0 PARAMETER HW_VER = 4.00.a PARAMETER C_DDR_RAM_HIGHADDR = 0x3FFFFFFF PARAMETER C_USE_M_AXI_GP0 = 0 PORT MIO = processing_system7_0_mio PORT PS_SRSTB = processing_system7_0_ps_srstb PORT PS_CLK = processing_system7_0_ps_clk PORT PS_PORB = processing_system7_0_ps_porb PORT DDR_Clk = processing_system7_0_ddr_clk PORT DDR_CKE = processing_system7_0_ddr_cke PORT DDR_CS_n = processing_system7_0_ddr_cs_n PORT DDR_RAS_n = processing_system7_0_ddr_ras_n END You might also want to check the XPS GUI to look at the interconnect of various components and replicate them accordingly in the IP integrator. Migration Methodology Guide 69

70 Chapter 6 Migrating ISE Simulator Tcl to Vivado Simulator Tcl Tcl Command Migration The following table lists the ISE Simulator (ISim) Tcl commands and the equivalent Tcl commands in the Vivado simulator. Table 6-1: ISE Simulator (ISim) Tcl to Vivado Tcl Mappings ISim Tcl Vivado Design Suite Tcl bp add <file_name> <line_number> bp clear bp del <index> [<index> ] bp list bp remove <file_name> <line_number> describe <name> dump dump p <process_scope_name> isim condition add <condition_expression> <command> [-label <label_name>] isim condition remove [<label_names> ] [<indexlist> ] [-all] isim condition list isim force add <object_name> <value> [-radix <radix>] [-time <time_offset>] { [ -value <value> [-radix <radix>] -time <time_offset>] } <[-cancel <time_offset>] [-repeat <time_offset>] isim force remove add_bp file_name line_number remove_bps remove_bp indexlist report_bps remove_bps [get_bps filter {file_name==<file_name> && line_number == <line_number>}] describe name report_values report_values process_scope_name/* add_condition [-label name] <condition_expression> <command> remove_conditions [names_indices_objects ] report_conditions add_force [-radix radix] [-cancel_after <time_offset>] [-repeat_every <time_duration>] <object_name> {<value> [<time>] } [{ <value> <time>} ] remove_force Migration Methodology Guide 70

71 Tcl Command Migration Table 6-1: isim get <property> Properties: arraydisplaylength, radix, userunit, maxtraceablesize, ltrace, ptrace isim set <property> <value> properties: arraydisplaylength, radix, userunit, maxtraceablesize, ltrace, ptrace onerror {tcl_commands} put [ radix <radix>] name value quit [-f -force] [-s -sim] restart resume run [all continue <time> <unit>] saif open [-scope <path_name>] [-file <file_name>] [-level <nesting_level>] [-allnets] saif_close scope [<path>] sdfanno show time show port show scope show signal show variable show constant get_property property_name [current_sim] Properties: array_display_limit, radix, time_unit, trace_limit, line_tracing, process_tracing set_property property_name property_value [current_sim] Properties: array_display_limit, radix, time_unit, trace_limit, line_tracing, process_tracing onerror {tcl_commands} set_value [ radix radix] Design_object value quit [-f -force] restart resume run [-all] [time unit] open_saif file_name; log_saif hdl_objects close_saif [SaifObj] current_scope hdl_scope SDF annotation an option for the simulation xelab (elaborator) command. sdfanno is no longer supported. current_time report_objects [get_objects * filter {type == port}] report_scope report_objects [get_objects * filter {type == signal}] report_objects [get_objects * filter {type == variable}] report_objects [get_objects * filter {type == constant}] show child [-r] report_scopes [get scopes r *] show driver <hdl_object_name> show load <hdl_object_name> show value [-radix <radix>] <hdl_object_name> step ISE Simulator (ISim) Tcl to Vivado Tcl Mappings (Cont d) ISim Tcl Vivado Design Suite Tcl test [-radix radix] <hdl_object_name> <test_value> report_drivers hdl_object (not supported) report_readers hdl_object (not supported) report_value [-radix radix] hdl_object step [-over] No longer supported. Use Tcl built-in command as follows: expr {[get_value radix radix hdl_object] == test_value} Migration Methodology Guide 71

72 Tcl Command Migration Table 6-1: vcd dumpfile <file_name> vcd dumpvars m <hdl_scope_name> [-l <level>] vcd dumplimit <size> vcd dumpon vcd dumpoff vcd dumpflush ISE Simulator (ISim) Tcl to Vivado Tcl Mappings (Cont d) ISim Tcl Vivado Design Suite Tcl wave log [-r] name open_vcd file_name log_vcd hdl_objects limit_vcd [VCDObject] filesize start_vcd [VCDObject] stop_vcd [VCDObject] flush_vcd [VCDObject] log_wave hdl_objects Migration Methodology Guide 72

73 Chapter 7 Migrating ISE ChipScope Logic Analyzer to Vivado Lab Tools Introduction This chapter describes the Vivado Design Tool lab tools, how these tools relate to the ISE Design Suite ChipScope Logic Analyzer tools, and how you can migrate IP cores from the ISE Chipscope environment into the Vivado lab tools. Vivado lab tools is the term that represents all of the programming and debugging tools that are available in the Vivado Design Suite. The features that are included in the Vivado lab tools include: Vivado device programmer Vivado logic analyzer Vivado serial I/O analyzer Table 7-1, page 74 provides the Vivado Integrated Design Environment (IDE) nomenclature, and lists what ISE tool the Vivado lab tools replaces. Migration Methodology Guide 73

74 Introduction Table 7-1: Vivado IDE Feature, Description, and ISE Tool Replacement Vivado IDE Feature Descriptions Replaces ISE Tool Vivado device programmer Vivado logic analyzer Vivado serial I/O analyzer The Vivado device programmer feature represents the functionality in the Vivado IDE that is used to program and configure Xilinx FPGA devices. This feature also programs any non-volatile (NV) memory storage devices that are attached to Xilinx FPGA devices. NV memory devices store configuration information used to program Xilinx FPGA devices. Vivado logic analyzer feature represents the functionality in the Vivado IDE that is used for logic debugging and validation of a design running in Xilinx FPGA devices in hardware. The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including: ILA 2.0 (and later versions) VIO 2.0 (and later versions) Vivado serial I/O analyzer feature represents the functionality in the Vivado IDE that is used for debugging and validating the high-speed serial I/O links of Xilinx FPGA devices in hardware. The Vivado serial I/O analyzer is used to interact with the serial I/O debug LogiCORE IP cores, including: IBERT 7 Series GTZ 3.0 (and later) IBERT 7 Series GTH 3.0 (and later) IBERT 7 Series GTX 3.0 (and later) IBERT 7 Series GTP 3.0 (and later) Replaces the impact device programmer tool. ChipScope Logic Analyzer Migration Methodology Guide 74

75 Legacy IP Core Support Legacy IP Core Support Xilinx recommends that you move to the new Vivado debug IP cores; however, you can still use many of the ChipScope Pro debug cores with the Vivado design tools (and beyond). There are important caveats that you must follow: The ChipScope Pro debug IP cores are not available in the Vivado IP catalog. These cores are only available from the IDS 14.5 CORE Generator tool. The ChipScope Pro debug IP core XCO files are not compatible with the Vivado tools. IMPORTANT: Do not add an XCO file to a Vivado project. In a Vivado project, add the following to a project: The NGC file generated from the core The XDC file The Synthesis template file (.V or.vhd, depending on the HDL language) Set the USED_IN_SYNTHESIS property to false for the ChipScope debug core XDC files. Set the SCOPE_TO_REF property to the appropriate cell name. The following is an example for a design that contains the icon_v1_06a, ila_v1_05a, and the vio_v1_05a ChipScope Pro debug IP cores: set_property USED_IN_SYNTHESIS false [get_files icon_v1_06a.xdc ila_v1_05a.xdc vio_v1_05a.xdc] set_property SCOPE_TO_REF {ila_v1_05a} [get_files ila_v1_05a.xdc] The legacy ChipScope Pro debug IP cores, listed in Table 7-2, require the ChipScope Pro Analyzer tool for interaction during run-time debugging and are NOT compatible with the Vivado lab tools. Table 7-2: Legacy Cores, Compatibility, and New Vivado Debug IP Cores Legacy ChipScope Pro Debug IP Core and Version Compatible with Vivado (and later) Agilent Trace Core 2 (ATC2), v1.05a No N/A AXI ChipScope Monitor, v3.05a Yes N/A Integrated Bit Error Ratio Tester (IBERT) 7 Series GTH, v2.01a No New Compatible Vivado Debug IP Core Integrated Bit Error Ratio Tester (IBERT) 7 Series GTH, v3.0 (or later) Migration Methodology Guide 75

76 ChipScope Pro Analyzer Core Compatibility Table 7-2: Legacy Cores, Compatibility, and New Vivado Debug IP Cores (Cont d) Legacy ChipScope Pro Debug IP Core and Version Integrated Bit Error Ratio Tester (IBERT) 7 Series GTP, v2.00a Integrated Bit Error Ratio Tester (IBERT) 7 Series GTX, v2.02a Integrated Bit Error Ratio Tester (IBERT) Spartan6 GTP, v2.02a Integrated Bit Error Ratio Tester (IBERT) Virtex5 GTX, v2.01a Integrated Bit Error Ratio Tester (IBERT) Virtex6 GTX, v2.03a Integrated Bit Error Ratio Tester (IBERT) Virtex6 GTH, v2.06a Compatible with Vivado (and later) No No No No No No Integrated Bit Error Ratio Tester (IBERT) 7 Series GTP, v3.0 (or later) Integrated Bit Error Ratio Tester (IBERT) 7 Series GTX, v3.0 (or later) N/A N/A N/A N/A Integrated Controller (ICON), v1.06a Yes N/A New Compatible Vivado Debug IP Core Integrated Logic Analyzer (ILA), v1.05a Yes Integrated Logic Analyzer (ILA), v2.0 (or later) Virtual Input/Output (VIO), v1.05a Yes Virtual I/O (VIO), v2.0 (or later) ChipScope Pro Analyzer Core Compatibility The following subsections describe the compatibility of the ChipScope Pro Analyzer with new Vivado bebug IP cores. ILA and VIO Debug IP Cores You must use the Vivado logic analyzer to interact with the ILA v2.0 (or later) and/or VIO v2.0 (or later) debug IP cores. Table 7-3 shows the logic debug IP core compatibility with run-time tools. Table 7-3: Debug IP Core and Run-time Tool Requirements Debug IP Core and Version Run-time Tool Requirement AXI ChipScope Monitor, v3.05a (or earlier) Integrated Controller (ICON), v1.06a (or earlier) Integrated Logic Analyzer (ILA), v1.05a (or earlier) Integrated Logic Analyzer (ILA), v2.0 (or later) ChipScope Pro Analyzer ChipScope Pro Analyzer ChipScope Pro Analyzer Vivado logic analyzer Migration Methodology Guide 76

77 ChipScope Pro Analyzer Core Compatibility Table 7-3: Virtual Input/Output (VIO), v1.05a (or earlier) Virtual Input/Output (VIO), v2.0 (or later) IBERT 7 Series GTH/GTP/GTX/GTZ v3.0 (or later) Debug IP Cores You must use the Vivado serial I/O analyzer to interact with the IBERT 7 Series GTH/GTP/GTX/GTZ v3.0 (or later) debug IP cores. Table 7-4 shows the serial I/O debug IP core compatibility with run-time tools. Table 7-4: Debug IP Core and Run-time Tool Requirements (Cont d) Debug IP Core and Version Run-time Tool Requirement ChipScope Pro Analyzer Vivado logic analyzer IBERT 7 Series Debug IP Cores and Run-Time Tool Requirements Debug IP Core and Version Run-time Tool Requirement Integrated Bit Error Ratio Tester (IBERT) 7 Series GTH, v2.01a (or earlier) Integrated Bit Error Ratio Tester (IBERT) 7 Series GTH, v3.0 (or later) Integrated Bit Error Ratio Tester (IBERT) 7 Series GTP, v2.00a (or earlier) Integrated Bit Error Ratio Tester (IBERT) 7 Series GTP, v3.0 (or later) Integrated Bit Error Ratio Tester (IBERT) 7 Series GTX, v2.02a Integrated Bit Error Ratio Tester (IBERT) 7 Series GTX, v3.0 (or later) Integrated Bit Error Ratio Tester (IBERT) 7 Series GTZ, v2.0 ChipScope Pro Analyzer Vivado serial I/O analyzer ChipScope Pro Analyzer Vivado serial I/O analyzer ChipScope Pro Analyzer Vivado serial I/O analyzer ChipScope Pro Analyzer or Vivado serial I/O analyzer Combining legacy ChipScope Pro and Vivado Debug IP Cores within a Design You can combine legacy ChipScope cores with Vivado core using the following rules: You can either instantiate Vivado debug IP cores in your HDL code or you can insert the ILA v2.0 core into the Vivado design netlist. Note: Note that the dbg_hub core that connects your Vivado debug IP cores to the JTAG infrastructure is automatically inserted into your design. You must instantiate the legacy ChipScope Pro debug IP cores into your HDL code. Note: Debug core insertion into the Vivado design netlist is not supported for legacy ChipScope Pro debug IP cores. You must instantiate an ICON core in your design that is used to connect the other legacy ChipScope Pro debug IP cores to the JTAG chain infrastructure. IMPORTANT: Make sure that the ICON and dbg_hub cores do not use the same JTAG user scan chain; doing so produces errors during write_bitstream DRC checking. Migration Methodology Guide 77

78 ChipScope Pro Analyzer Core Compatibility Figure 7-1 is an annotated screen capture that shows how to change the JTAG user scan chain of the dbg_hub core: X-Ref Target - Figure 7-1 Figure 7-1: Steps for Changing JTAG User Scan Chain of dbg_hub Migration Methodology Guide 78