IDEA! Avnet SpeedWay Design Workshop

Transcription

1 The essence of FPGA technology IDEA! 2

2 ISE Tool Flow Overview Design Entry Synthesis Constraints Synthesis Simulation Implementation Constraints Floor-Planning Translate Map Place & Route Timing Analysis Delay Simulation Silicon 5

3 Support Across The Board Avnet Speedway Design Workshop Improving Performance Workshop Fundamental Timing Constraints V9_2_2_0

4 What Needs Constraining? Internal clock speed for one or more clocks I/O speed Logic using multi-cycle clocks Pad to Pad timing Pad Locations & Logic Locations I/O Speed Clk & CE Speed I/O Speed X CLK Y Z<0:9> D Q D Q Logic Locations 1 Level of Logic 2 Levels of Logic OUT1 OUT2 Pin Locations Pin Locations Pin 2 Pin Speed 29

5 Most Common Timing Constraints PERIOD Constrain all paths, sync element to sync element OFFSET Constrain I/O paths, ie. pad to sync element, sync element to pad (these are not covered by PERIOD constraints) FROM-TO Specify Slow/Fast paths and Multi-Cycle paths FROM-THRU-TO Constrain specific path thru logic between sync elements TIG (Timing Ignore) Remove slow or static paths from Timing Analysis 30

6 Timing Constraint Precedence Within a particular source Highest Priority TIG (Timing Ignores) FROM-THRU-TO specs FROM-TO specs OFFSET specs Lowest Priority PERIOD specs 32

7 Constraint Entry Methods Constraint Editor Preferred method Tools manage constraint syntax Text Editor User must manage syntax PACE Physical constraints only 33

8 Xilinx Constraints Editor (Old style) Clock Timing IO Timing PAD to PAD Timing Generated UCF Constraints: PERIOD, OFFSET, PAD TO PAD 34

9 New Constraints editor GUI (9.2 ->) 35

10 PERIOD Constraint ADATA FLOP1 D Q FLOP2 FLOP3 OUT1 CLKA BUFG BUS [7..0] FLOP4 FLOP5 OUT2 CLKB CDATA G = Unconstrained Data Path = Constrained Data Path Period = 10 ns HIGH = 45% LOW = 55% PERIOD accounts for data path delay PERIOD accounts for duty cycle in this case 45/55 PERIOD accounts for first clock edge in this case HIGH PERIOD is specified with the clock period PERIOD accounts for clock skew on global and local clocks PERIOD accounts for clock phase including DCM phase and negative edge clocking UCF Example: NET CLKA" TNM_NET = CLKA_Group"; TIMESPEC "TS_CLKA_Group_Spec " = PERIOD CLKA_Group" 10 ns HIGH 45%; 36

11 Basic Period Report Clock names and time of active edge. Includes Clock Phase Slack equation Basic element type is listed Logic Levels Only levels of logic, not Clock to Out and Setup Updated! Web link to graphical picture of delay type! (In Timing Analyzer) Data path with Cross Probing Links to Floorplanner or Synthesis Tool (In Timing Analyzer) 37

12 OFFSET IN Constraint The OFFSET IN constraint covers paths from the input pads to synchronous elements taking clock delay into account The OFFSET IN constraint does NOT optimize paths clocked by internally generated clocks (including DCM s) OFFSET IN only covers PAD to registered element data paths OFFSET IN does not constrain the delay or skew of clock path itself ADATA FLOP1 D Q FLOP2 FLOP3 OUT1 CLKA BUFG BUS [7..0] FLOP4 FLOP5 OUT2 CLKB CDATA BUFG = Unconstrained Data Path = Constrained Data Path 44

13 OFFSET IN Constraint OFFSET IN is used to constrain input data paths OFFSET IN clock is specified to the clock PAD OFFSET IN clock can not be an internal clock DCM output OFFSET IN only covers PAD to registered element data paths OFFSET IN does not constrain the delay or skew of clock path itself 45

14 OFFSET IN BEFORE Constraint FPGA External Data T Data ø T SU / T H REG External Clock OFFSET IN BEFORE External Clock T Clk ø CLK External Data Valid Data VALID OFFSET IN BEFORE Is time data is VALID prior to capture clock VALID Duration is time data remains VALID data eye width VALID is required for hold time analysis and error reporting Without explicit VALID, implied VALID = OFFSET In this example, implied VALID is not correct Without VALID, hold time can be reported with TRCE fastpaths -fastpaths reports delays only and does not check for hold errors 46

15 OFFSET IN Report Example Slack equation Clock name and time of active edge Data Path Delay Clock Path Delay 47

16 System Synchronous Interface Source Device T CKO REG CLK T Data T DataTrace T Data FPGA T SU/ T H REG CLK DCM System Clock T SrcClk T DestClk One common system clock for both source and destination Board level skew and data path delays limits performance Typically Single Data Rate (SDR) applications 49

17 System Synchronous Inputs Transmit Edge PERIOD = 10 ns Capture Edge SysClk OFFSET IN BEFORE = 9 ns DataIn Valid Data VALID = 8 ns This example shows Data Valid Window less than PERIOD Start of data is 9 ns before the capture clock edge Data remains VALID for 8 ns OFFSET IN 9 ns VALID 8 ns BEFORE SysClk; 50

18 System Synchronous Data Sheet 51

19 OFFSET OUT Constraint The OFFSET OUT constraint covers paths from synchronous elements to output pads taking clock delay into account The OFFSET OUT constraint does NOT optimize paths clocked by internally generated clocks ADATA FLOP1 D Q FLOP2 FLOP3 OUT1 CLKA BUFG BUS [7..0] FLOP4 FLOP5 OUT2 CLKB CDATA BUFG = Unconstrained Data Path = Constrained Data Path 56

20 OFFSET OUT Constraint Defines maximum time in which data can leave the chip Used for destination device setup time verification OFFSET OUT clock is specified to the clock PAD OFFSET OUT clock can not be an internal clock Best used for system synchronous interfaces OFFSET = OUT 10 ns AFTER "SYS_Clk"; 57

21 OFFSET OUT Report Slack equation Clock name and time of active edge Clock Path Delay Data Path Delay 60

22 Constraining Specific Delays A FROM-TO constraint defines the delay between two groups of logic Logic paths typically start and stop at pads, registers, latches, RAM, multipliers, CPUs and high speed IOs (MGT) It is used to constrain the following types of paths (more details later): Multi-cycle paths --If not expected to meeting the original single cycle clock period Data paths between unrelated clocks False Paths --If paths/net that are known not to have a timing requirement No HOLD violation check is done for FROM:TO paths 62

23 Basic FROM-TO Examples A FROM-TO constraint defines the delay between two groups of logic Logic paths typically start and stop at pads, registers, latches, RAM, multipliers, CPUs and high speed IOs (MGT/GTP) UCF TIMESPEC command using default keywords TIMESPEC TS_C2S=FROM FFS TO FFS 30; TIMESPEC TS_P2S=FROM PADS TO FFS 25; TIMESPEC TS_P2P=FROM PADS TO PADS 26; TIMESPEC TS_C2P=FROM FFS TO PADS 9; TS_P2S TS_C2S D Q D Q TS_C2P OUT1 CLK OUT2 TS_P2P 63

24 FROM:TO Report Slack equation Requirement is < twice TS_clk (40ns) Data Path Delay 64

25 PAD to PAD Constraint Purely combinatorial delay paths start and end at I/O pads and are often left unconstrained by users Placing a FROM:TO constraint on pads-to-pads is necessary if there is a timing requirement TIMESPEC TS_P2P = FROM PADS TO PADS 15 ns; ADATA FLOP1 D Q FLOP2 FLOP3 OUT1 CLKA BUFG BUS [7..0] FLOP4 FLOP5 OUT2 CLKB CDATA BUFG = Unconstrained Data Path = Constrained Data Path 65

26 PAD to PAD Report Slack equation Source and Destination elements are PADS Data Path Delay 66

27 Pre-Defined Groups Timing constraints are applied to logic paths Logic paths typically start and stop at pads, and synchronous elements The tool recognizes the following keywords to define endpoints or time groups: PADS All I/O pads FFS All flip-flops LATCHES All latches RAMS All RAM elements BRAMS_PORTA All Port A Dual Block RAM elements BRAMS_PORTB All Port B Dual Block RAM elements HSIOS All High Speed I/O elements (RocketI/O) CPUS All PowerPC elements MULTS All Multiplier elements DSPS All DSP48 and derivatives (DSP48A, DSP48E) Keywords can be used globally, and to create design sub-groups 71

28 Using TNM_NET to create Groups on Nets NET clock TNM_NET=clk_group; TNM_NETis equivalent to TNM on a net except for pad nets. If you place a TNM on a pad net, it will trace backwards to the pad and not trace forward through the buffer to the next synchronous element. TNM_NET was created for this purpose. If you place a TNM_NET on a pad net, it will trace through the buffer to the next synchronous element. TNM_NETis extremely useful for synthesis designs. The ports are directly connected to pads. TNM_NET can be used in UCF or NCF only. 74

29 Auto-Related DCM Paths PERIOD constraint applied to CLKIN CLK2X Period automatically defined as related to CLK1X Cross-clock paths are automatically analyzed FROM-TO constraints are not required! 95

30 ISE Tool Flow Review Design Entry Synthesis Constraints Synthesis Simulation Implementation Constraints Floor-Planning Translate Map Place & Route Timing Analysis Delay Simulation Silicon 133

31 Source Code Changes to Improve Timing Pipeline Reduce combinatorial delays Register block outputs Register duplications In general, source code changes have greater effect in improving performance than software switches 134

32 Timing-Driven MAP MAP -timing (Use Timing-Driven Packing and Placement Algorithm) MAP runs normally, then examines timing If timing is not met, MAP tries to re-pack and place critical logic in order to meet constraints Runtime for MAP increases but this should be offset by a reduction in the PAR runtime Greatest benefit is seen in high density designs with unrelated logic packing Typical performance improvement of 5 percent is achievable Maximum performance improvement of 30 percent is possible 135

33 Timing-Driven MAP Options Other options used with -timing option Set -ol overall effort level {std med high} Extra effort -xe {n c} Register duplication: -register_duplication Allows MAP to duplicate registers to improve timing Starting placer cost table: -t {1-100} 136

34 Timing-Driven MAP Options GUI Right click Implement Design and pick Properties Pick Map Properties Pick Advanced 137

35 Timing-Driven MAP Options GUI Enable advanced placement options Check Timing Driven Packing and Placement Advanced Options enabled Set High to enable Extra Effort 138

36 Timing Constraints In order to enable timing optimization you must set Optimization Goal to Speed in XST synthesis options 205