Temperature Sensor TMP2 PMOD Part 1

Transcription

1 Temperature Sensor TMP2 PMOD Part 1 Overview of the Temperature Sensor and I 2 C Interfacing Reference Sites: Diligent Temp2 PMOD: Analog Devices ADT7420: 1

2 Up to 16-bit resolution ( C resolution). Typical accuracy better than 0.25 C. I 2 C interface with 4 selectable addresses. 240ms continuous conversion time. Support for 3.3v and 5v interfaces. No calibration required. Daisy-chain the Pmod TMP2 to other I2C devices. Two 2-pin headers for establishing the I2C address of the chip. Two 2-pin headers for controlling external devices based upon temperature thresholds defined by the user in software. 2

3 ADT7420 Temperature Sensor Functional Block Diagram Pointer register to establish which register is to be accessed. 13 or 16-bit temperature register. 40 C to +150 C range. Programmable Critical over-temperature output signal. Programmable over-temperature/under-temperature output signal (INT). Programmable hysteresis. Hardware selectable device address bits (A1 A0). 3

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5 Connection of TMP2 to MX7cK I2C Bus #1 (I2C1) 5

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7 Master Slave 1 Slave 2 Slave n... Each slave device has a unique 7-bit address. The Master controls the slaves via a 7-bit address, and once addressed, the master issues commands, such as writing to, or reading from the slave s registers. 7

8 2 Master Slave 1 Slave 2 Slave n... A transaction between the master and slave device typically occurs as follows: Master sends a control frame that addresses a particular slave device. The master then sends another frame that identifies the register within the slave the master wants to access. Finally, the master either sends data to be written into the specified register within the slave, of the slave sends data from the specified register to the master. Typical I 2 C devices have control, status, and data registers. Typically, the master would first send data to the control registers to configure the slave device for a particular mode of operation which the slave supports. Then the master may wish to view status information by reading a status register within the slave. Finally, the master may wish to write data or read data to/from the data register within the slave device. 8

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10 7-bit serial address. The five MSbs of this address for the ADT7420 are fixed to Pin A1 and Pin A0 are externally established. On the PmodTMP2 board, there are two jumpers for selecting the state of these address lines. 10

11 Bus Protocol: Transaction 1. The master sends the first frame, which is the control frame. This addresses the slave the master wants to access. 2. After the control frame, the address of the register the master wants to access is sent to the slave. 3. Following the register address frame, then either The master sends data to be written into the register, or The slave sends data from the register to the master, Depending on the state of the R/Wn bit in the previous control frame. 11

12 start Clock is normally high; the master generates and sends the clock to the slave. Initially, each device on the bus is inactive and sets their and lines to logic high. Master initiates data transfer by establishing a start bit, which is defined as a high-to-low transition on the serial data line,, while the serial clock line,, is high. The start bit indicates that the next 9 bit cells of the frame are going to follow. All slave peripherals connected to the serial bus respond to the start bit and will shift in the next eight bits, consisting of a 7-bit address (MSB first) plus a read/ write (R/W) bit. The R/W bit determines whether the next data frame is to be sent by the master and received by the slave, or sent by the slave and received by the master. 12

13 ack The peripheral with the address corresponding to the transmitted address responds by pulling line low during the low time of the ninth clock period, known as the acknowledge bit. Note: the Master will have set high during this time. Why? All other non-selected devices on the bus remain idle (i.e., their / lines will be high) while the selected device prepares for the subsequent data transmission or reception, depending on the state of the R/Wn bit. If the R/Wn bit is a 0, the master will write to the slave device next. If the R/Wn bit is a 1, the master will read from the slave device in the next frame. 13

14 Data bits are sent over the serial bus synchronously with nine clock pulses, eight bits of data followed by an acknowledge bit from the receiver of data. Transitions on the data line must occur during the low time of the clock period and remain stable during the high time. This is to differentiate between signalling of a stop/start bit and transmission of a data bit; The start bit is signalled by pulling the line from high-to-low when the clock is high; The stop bit is signalled by pulling the line from low-to-high when the clock is high. 14

15 Bus Protocol: Stop Transmission When all data bytes have been read or written, the master must assert a stop bit to terminate the current transaction. The are two scenarios: 1. In write mode, the master pulls the data line high during the high time of the 10 th clock period to assert a stop bit, which terminates the current transaction. 2. In read mode, the master must first inform the slave not to send anymore data. The master does this by pulling the data line high during the low time of the ninth clock period to assert a no acknowledge. The master generates the no acknowledge bit to signal the slave to stop sending anymore data bytes. The master then asserts a stop bit by pulling the data line low during the low time of the 10 th clock period, then high during the high time of the 10 th clock period, and this terminates the current transaction. 15