Microcontroller Systems. ELET 3232 Topic 23: The I 2 C Bus

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Tyrone Lane
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1 Microcontroller Systems ELET 3232 Topic 23: The I 2 C Bus

2 Objectives To understand the basics of the I 2 C bus To understand the format of a serial transmission between I 2 C devices To understand how AVR devices implement the I 2 C bus TWI: Two Wire Interface 11/29/2010 2

3 I 2 C Introduction Low end serial communication option Developed by Philips Short for Inter-IC (integrated circuit) bus Often used to communicate across circuit-board distances 11/29/2010 3

4 I 2 C Introduction I 2 C provides support for communication with: Slow, on-board peripheral devices that are accessed intermittently It is a simple, low-bandwidth, short-distance protocol. Most I 2 C devices operate at speeds up to 400Kbps Some operate in the low megahertz range I 2 C has a built-in addressing scheme Used to link multiple devices together 11/29/2010 4

5 I 2 C Introduction Philips originally developed I 2 C for communication between devices inside of a TV set Examples of I 2 C-compatible devices include: EEPROMs Thermal sensors Real-time clocks 11/29/2010 5

6 I 2 C Introduction I 2 C is also used as a control interface to signal processing devices For instance, it is commonly used in multimedia applications including: RF tuners Video decoders and encoders Audio processors Philips, National Semiconductor, Xicor, Siemens, and other manufacturers offer hundreds of I 2 C-compatible devices. 11/29/2010 6

7 I 2 C Introduction I 2 C is appropriate for interfacing to devices on a single board Can be stretched across multiple boards inside a closed system, but not much further. An example: A host CPU on a main embedded board using I 2 C to communicate with user interface devices located on a separate front panel board. A second example: SDRAM DIMMs: can feature an I 2 C EEPROM containing parameters needed to correctly configure a memory controller for that module 11/29/2010 7

8 SDA and SCL I 2 C is a two-wire serial bus Central Microcontroller SDA SCL Peripheral Device #1 Peripheral Device #2 Peripheral Device #3 Peripheral Device #4 The two I 2 C signals are serial data (SDA) and serial clock (SCL) 11/29/2010 8

9 SDA and SCL SDA and SCL support serial transmission of 8-bit Central Microcontroller SDA SCL Peripheral Device #1 Peripheral Device #2 Peripheral Device #3 Peripheral Device #4 bytes of data-7-bit device addresses plus control bits-over the two-wire serial bus. 11/29/2010 9

10 SDA and SCL The device that initiates communication is the master Central Microcontroller SDA SCL Peripheral Device #1 Peripheral Device #2 Peripheral Device #3 Peripheral Device #4 The master normally controls the clock signal. A device being addressed by the master is called a slave 11/29/

11 Masters and Slaves An I 2 C slave can hold off the master during a transaction Uses what's called clock stretching (the slave keeps SCL pulled low until it's ready to continue) Most I 2 C slave devices don't use this feature, but every master should support it. The I 2 C protocol supports multiple masters Most system designs include only one There may be one or more slaves on the bus Both masters and slaves can receive and transmit data bytes 11/29/

12 Masters and Slaves Each I 2 C-compatible slave device comes with a predefined device address The lower bits of which may be configurable at the board level This limits the number of identical slave devices on an I 2 C bus without contention The limit set by the number of user-configurable address bits (typically two bits, allowing up to four identical devices) 11/29/

13 Masters and Slaves The master transmits the device address of the intended slave at the beginning of every transaction Each slave is responsible for monitoring the bus and responding only to its own address There are four potential modes of operation for a given bus device, although most devices only use a single role and its two modes: master transmit master node is sending data to a slave master receive master node is receiving data from a slave slave transmit slave node is sending data to a master slave receive slave node is receiving data from the master 11/29/

14 Masters and Slaves The master begins the communication by issuing the start condition (S) initially in master transmit mode The master then sends a unique 7-bit slave device address, with the most significant bit (MSB) first 11/29/

15 Masters and Slaves The eighth bit after the start, (read/not-write), specifies whether the slave is now to receive (0) or to transmit (1) data This is followed by an ACK bit issued by the receiver, acknowledging receipt of the previous byte. 11/29/

16 Masters and Slaves Then the transmitter (slave or master, as indicated by the R/W bit) transmits a byte of data starting with the MSB. At the end of the byte, the receiver (whether master or slave) issues a new ACK bit. This 9-bit pattern is repeated if more bytes need to be transmitted 11/29/

17 Masters and Slaves When the master is done transmitting all of the data bytes it wants to send in a write transaction (slave receiving), it monitors the last ACK and then issues the stop condition (P) 11/29/

It does not sends and ACK bit for the final byte it receives, it issues the

18 Masters and Slaves In a read transaction (slave transmitting) The master acknowledges all bytes it receives (sends and ACK bit) except the last one It does not sends and ACK bit for the final byte it receives, it issues the stop condition This tells the slave that its transmission is done. 11/29/

19 How does the AVR implement I 2 C protocols? 11/29/

TWI: Two Wire Interface The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines: One for clock (SCL) and one for data (SDA).

20 TWI: Two Wire Interface The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines: One for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. The bus drivers of all TWI-compliant devices are open-drain or opencollector. This implements a wired-and function which is essential to the operation of the interface. 11/29/

21 TWI: Two Wire Interface Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high. The only exception to this rule is for generating start and stop conditions. 11/29/

22 TWI: Two Wire Interface The master initiates and terminates a data transmission The transmission is initiated when the master issues a START condition on the bus It is terminated when the master issues a STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other master should try to seize control of the bus. 11/29/

23 Start/Stop/Repeated Start A special case occurs when a new START condition is issued between a START and STOP condition. Referred to as a REPEATED START condition Used when the master wishes to initiate a new transfer without relinquishing control of the bus. After a REPEATED START, the bus is considered busy until the next STOP. START (and REPEATED START) and STOP conditions are signaled by changing the level of the SDA line when the SCL line is high 11/29/

24 Addresses All address packets are 9 bits long: 7 address bits One Read/Write control bit If Read/Write = 1, a read operation will be performed If Read/Write = 0, a write operation will be performed One acknowledge bit When a slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle 11/29/

25 Typical Data Transmission A transmission consists of a START condition, a SLA+R/W, one or more data packets, and a STOP condition SLA = Slave Address An empty message, consisting of a START followed by a STOP condition is illegal. 11/29/

26 Using the TWI 11/29/

27 Interrupt Based The AVR TWI: Byte-oriented Interrupt based Interrupts are issued after all bus events: Ex: reception of a byte or transmission of a START condition. Two Control bits enable interrupts: TWI Interrupt Enable (TWIE) bit in TWCR Global Interrupt Enable bit in SREG If both are enabled: assertion of the TWINT flag will generate an interrupt request If the TWIE bit is cleared (disabled), the application must poll the TWINT flag in order to detect actions on the TWI bus 11/29/

28 Interrupt Based When the TWINT flag is asserted (high), the TWI has finished an operation and awaits application response The TWI Status Register (TWSR) contains a value indicating the current state of the TWI bus The TWINT flag is set in the following situations: After the TWI has transmitted a START/REPEATED START condition After the TWI has transmitted SLA+R/W After the TWI has transmitted an address byte After the TWI has lost arbitration After the TWI has been addressed by own slave address or general call After a STOP or REPEATED START has been received while still addressed as a slave After the TWI has received a data byte When a bus error has occurred due to an illegal START or STOP condition 11/29/

29 TWI Bit Rate Register TWBR selects the division factor for the bit rate generator The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes 11/29/

30 TWI Control Register The TWCR is used to control the operation of the TWI Enables the TWI Initiates a master access by applying a START condition to the bus Generates a receiver acknowledge Generates a stop condition Controls halting of the bus while the data to be written to the bus are written to the TWDR Indicates a write collision if a data write is attempted to the TWDR while the register is inaccessible 11/29/

31 TWI Control Register TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector (the ISR) While the TWINT flag is set, the SCL low period is stretched 11/29/

32 TWI Control Register TWINT: TWI Interrupt Flag The TWINT flag must be cleared through software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag. 11/29/

33 TWI Control Register TWEA: TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse If a one is written to the TWEA bit, the ACK pulse is generated on the TWI bus if the following conditions are met: The device s own slave address has been received A general call has been received, while the TWGCE bit in the TWAR is set A data byte has been received in Master Receiver or Slave Receiver mode By writing a 0 to the TWEA bit, the device can be virtually disconnected from the Two-wire Serial Bus (temporarily) Address recognition can then be resumed by writing the TWEA bit to one again 11/29/

34 TWI Control Register TWSTA: TWI START Condition Bit The application writes a 1 to the TWSTA bit when it desires to become a master on the Two-wire Serial Bus The TWI hardware checks if the bus is available, and generates a START condition on the bus if it is free If the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status TWSTA must be cleared by software when the START condition has been transmitted 11/29/

35 TWI Control Register TWSTO: TWI STOP Condition Bit Writing a 1 to the TWSTO bit generates a STOP condition When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically 11/29/

36 TWI Control Register TWWC: TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWI Data Register (TWDR) when TWINT is low This flag is cleared by writing data to the TWDR Register when TWINT is high 11/29/

37 TWI Control Register TWEN: TWI Enable Bit The TWEN bit enables TWI operation and activates the TWI interface. When a one is written to TWEN, the TWI takes control over the I/O pins connected to the SCL and SDA pins If this a 0 is written tot his bit, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation 11/29/

38 TWI Control Register TWIE: TWI Interrupt Enable When a one is written to this bit, and the I-bit in SREG (Global Interrupt enable) is set, interrupts are enabled for the TWI Whenever the TWINT flag is high, a TWI interrupt request is generated 11/29/

39 TWI Status Register TWSR: TWS (7-3): TWI Status These 5 bits reflect the status of the TWI logic and the Two-Wire Serial Bus The TWSR contains both the 5-bit status value and the 2-bit prescaler value The application designer should mask the prescaler bits to zero when checking the Status bits This makes status checking independent of prescaler setting 11/29/

40 TWI Status Register TWS: TWPS (1-0): TWI Prescaler Bits These bits can be read and written They control the bit rate prescaler (see slide 29) 11/29/

41 TWI Data Register TWDR: In Transmit mode, TWDR contains the next byte to be transmitted In receive mode, the TWDR contains the last byte received It is not writable when the TWI interrupt flag (TWINT) is set This occurs while the TWI is in the process of shifting a byte 11/29/

42 TWI Address Register (slave) TWAR: The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes The LSB of TWAR is used to enable recognition of the general call address ($00) There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address If a match is found, an interrupt request is generated. 11/29/

43 Using the TWI Step 1: ldi r16,(1<<twint) (1<<TWSTA) (1<<TWEN) out TWCR, r16 TWCR = (1<<TWINT) (1<<TWSTA) (1<<TWEN); Sends the START condition 11/29/

44 Using the TWI Step 3a: wait1: in r16,twcr sbrs r16,twint rjmp wait1 while (!(TWCR & (1<<TWINT))); Waits for TWINT flag set to be set. This begins the process that indicates that the START condition has been transmitted 11/29/

45 Using the TWI Step 3a: in r16,twsr andi r16, 0xF8 cpi r16, START brne ERROR if ((TWSR & 0xF8)!= START) ERROR(); Checks the value of TWI Status Register and masks the prescaler bits. If status is different from the START condition go to ERROR 11/29/

46 Using the TWI Step 3b: ldi r16, SLA_W out TWDR, r16 ldi r16, (1<<TWINT) (1<<TWEN) out TWCR, r16 TWDR = SLA_W; TWCR = (1<<TWINT) (1<<TWEN); Loads SLA_W (Slave Address + Write) into the TWDR Register and clears TWINT bit in the TWCR to start transmission of the slave address 11/29/

47 Using the TWI Step 5a: wait2: in r16,twcr sbrs r16,twint rjmp wait2 while (!(TWCR & (1<<TWINT))); Waits for TWINT flag set to be set. This begins the process that indicates that the SLA+W has been transmitted, and ACK/NACK has been received. 11/29/

48 Using the TWI Step 5a: in r16,twsr andi r16, 0xF8 cpi r16, MT_SLA_ACK brne ERROR if ((TWSR & 0xF8)!= MT_SLA_ACK) ERROR(); Checks the value of TWI Status Register and masks the prescaler bits. If the status is different from MT_SLA_ACK go to ERROR 11/29/

49 Using the TWI Step 5b: ldi r16, DATA out TWDR, r16 ldi r16, (1<<TWINT) (1<<TWEN) out TWCR, r16 TWDR = DATA; TWCR = (1<<TWINT) (1<<TWEN); Loads the DATA that will be written to the slave into TWDR Register and then clears the TWINT bit in TWCR to start transmission of data 11/29/

50 Using the TWI Step 7a: wait3: in r16,twcr sbrs r16,twint rjmp wait3 while (!(TWCR & (1<<TWINT))); Waits for TWINT flag set. This begins the process that indicates that the DATA has been transmitted, and ACK/NACK has been received. 11/29/

51 Using the TWI Step 7a: in r16,twsr andi r16, 0xF8 cpi r16, MT_DATA_ACK brne ERROR if ((TWSR & 0xF8)!= MT_DATA_ACK) ERROR(); Checks the value of TWI Status Register and masks the prescaler bits. If the status is different from MT_DATA_ACK go to ERROR 11/29/

52 Using the TWI Step 7b: ldi r16,(1<<twint) (1<<TWEN) (1<<TWSTO) out TWCR, r16 TWCR = (1<<TWINT) (1<<TWEN) (1<<TWSTO); Transmits the STOP condition 11/29/

53 Summary We discussed: The basics of the I 2 C bus The format of a serial transmission between I 2 C devices How AVR devices implement the I 2 C bus We looked in detail at TWI: Two Wire Interface on the ATmega128 11/29/

ATmega640/1280/1281/2560/2561

ATmega640/1280/1281/2560/2561 ATmega64/28/28/256/256 Assembly Code Example () USART_MSPIM_Transfer: ; Wait for empty transmit buffer sbis UCSRnA, UDREn rjmp USART_MSPIM_Transfer ; Put data (r6) into buffer, sends the data out UDRn,r6