AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface

Transcription

1 AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface Subscribe Send Feedback Latest document on the web: PDF HTML

2 Contents Contents 1 RapidIO II Reference Design for Avalon -ST Pass-Through Interface Introduction Requirements Software Requirements Hardware Requirements Features of the RapidIO II Reference Design for the Avalon-ST Pass- Through Interface Downloading and Installing the Reference Design Walkthrough Hardware Setup Programming the FPGA Running the Design System Console User Interface Commands Register Address Map Document Revision History for RapidIO II Reference Design for the Avalon-ST Pass- Through Interface

3 1 RapidIO II Reference Design for Avalon -ST Pass- Through Interface 1.1 Introduction The RapidIO II reference design for the Avalon Streaming (Avalon-ST) pass-through interface demonstrates the use of the Avalon-ST pass-through interface to implement NWRITE transactions using the RapidIO II IP. You can use the Avalon-ST pass-through interface of the RapidIO II IP to implement RapidIO transaction types not available by our logical layer (for example, message passing and data streaming). Additionally, you can use this interface to implement custom functions not specified by the RapidIO protocol but applicable to a specific system. The Avalon-ST pass-through interface is an optional interface that is generated when you select the Avalon-ST pass-through interface in the Transport and Maintenance page of the RapidIO II IP parameter editor. Figure 1. RapidIO II Avalon-ST Pass-Through Interface Reference Design Block Diagram System Console JTAG Client Decode Traffic Generator Traffic Checker Statistics Module Status Packet Error- Monitoring Signals Avalon-MM Avalon-ST Register-Access Pass-Through Avalon-MM RX/TX Serial Transceiver Access Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

4 The RapidIO II reference design for Avalon-ST pass-through interface includes a traffic generator. The traffic generator initiates NWRITE RapidIO transactions and drives the RapidIO II IP Avalon-ST source. The design also includes a traffic checker which sinks the RapidIO transactions and is connected to the RapidIO II IP Avalon-ST sink. Related Links 1.2 Requirements RapidIO II IP Core User Guide Software Requirements Intel Quartus Prime Pro Edition 17.1 RapidIO II IP License Note: You need the license only if you compile the design or target the design to your device. Alternatively, you can use the free Intel FPGA IP Evaluation Mode feature to evaluate licensed Intel FPGA IP cores in simulation and hardware before purchase Hardware Requirements Intel Stratix 10 GX FPGA Development Board (1SG280LU3F50E3VGS1 with L-Tile transceivers (1) ) FMC Loopback Card Intel FPGA Download Cable II Power Supply Related Links Intel Stratix 10 FPGA Development Kit Features of the RapidIO II Reference Design for the Avalon-ST Pass-Through Interface The reference design has the following features: 4x Mode Gbaud MHz Reference Clock Avalon-ST Pass-Through Interface 1.3 Downloading and Installing the Reference Design You can download the reference design from the Design Store. You must have a myaltera account to gain access to the Design Store. (1) You can target a different device but this will require you to make modifications to the.qsf file. 4

5 1. Download the platform archive file srio2_s10_avst_6g_de.par from the Design Store to your chosen directory. 2. Open the Intel Quartus Prime software, click File Open Project. 3. Browse to select the srio2_s10_avst_6g_de.par file. 4. Click Open. 5. The Open Design Template window appears. For Project name, enter srio2_s10_avst_6g_de. Figure 2. Open Design Template 6. Click OK. After you open the srio2_s10_avst_6g_de.par file in the Intel Quartus Prime software, you can see the following directory structure. Figure 3. Directory Structure for the Reference Design Example <location of the downloaded.par file> Components ip output_files rtl system_console jtag_timing_template.sdc atx_pll xcvr_rst_ctl client_decode srio srio.ip sri2_s10_avst_6g_de.sof top_srio.v traffic_gen.v traffic_chk.v stats.v basic.tcl lpbk_ctl.tcl main_run.tcl srio_task.tcl srio2_s10_avst_6g_de.par srio2_s10_avst_6g_de.qpf srio2_s10_avst_6g_de.qsf ip atx_pll.ip top_srio.sdc srio2.stp xcvr_rest_ctl.ip client_decode.qsys Table 1. Reference Design Files File Name srio2_s10_avst_6g_de.qpf srio2_s10_avst_6g_de.qsf jtag_timing_template.sdc Description Intel Quartus Prime project file containing the list of all the revisions in the project. Intel Quartus Prime settings file containing the assignments and settings for the project. Defines the timing constraints for JTAG. srio2_s10_avst_6g_de.sof Pre-generated programming file. continued... 5

6 File Name Description top_srio.v traffic_gen.v traffic_chk.v stats.v top_srio.sdc srio2.stp ip/srio srio.ip components/atx_pll components/xcvr_rst_ctl components/client_decode components/ip atx_pll.ip xcvr_rst_ctl.ip client_decode.qsys basic.tcl lpbk_ctl.tcl main_run.tcl srio_tasks.tcl Top-level design file. Traffic generator module. Traffic checker module. Statistics collecting module. Top-level timing constraints file. Pre-populated Signal Tap file. RapidIO II IP sub folder contains all of the required synthesis files for the core. RapidIO II IP variation file that contains the parameterization of an IP core in your project. Contains all the necessary synthesis files for the ATX PLL. Contains all the necessary synthesis files for the Transceiver Reset Controller. Contains all the necessary synthesis files for the Client Decode Platform Designer based subsystems. Contains all of the Client Decode underlying sub IP block IP variation files. Created during the Client Decode system generation and this file is required to compile the design. Intel Stratix 10 ATX PLL IP variation file. Intel Stratix 10 Transceiver Reset Controller IP variation file. Platform Designer subsystems contains a JTAG Master and several Avalon-MM bridges used to decode the JTAG Avalon- MM address for the different Avalon-MM slave interface. Defines basic register read and write procedures. Defines TX to RX PMA buffer serial loopback control. Contains main call to the other.tcl files. Defines the majority of the RapidIO II related functions and procedures for controlling the traffic generator/checker and the statistics collector. 1.4 Walkthrough To run the design, you must have the Intel Stratix 10 GX FPGA development kit and you must have installed the Intel Quartus Prime Pro Edition 17.1 software to your computer. 6

7 Follow these steps to run the design: Hardware Setup Perform the following steps to setup the hardware for the reference design: 1. Insert the FMC Loopback Card to the FMC port on the Intel Stratix 10 GX FPGA development board. 2. Connect the Intel FPGA Download Cable II to the Intel Stratix 10 GX FPGA development board and to your host computer. 3. Connect the power adapter shipped with the development board to the power supply jack. 4. Set the DIP switches of the Intel Stratix 10 GX FPGA development board as specified below: Table 2. DIP Switch Control Settings DIP Switch Schematic Signal Name Setting SW8 1 I2C_SDA ON 2 I2C_SCL ON 3 FPGA_PWRGD OFF SW4 1 RZQ_B2M OFF 2 SI516_FS OFF SW3 1 CLK0_OEn OFF 2 CLK0_RSTn OFF 3 FACTORY_LOAD OFF SW2 1 PCIE_PRSNT2n_x16 OFF 2 PCIE_PRSNT2n_x8 OFF 3 PCIE_PRSNT2n_x4 OFF 4 PCIE_PRSNT2n_x1 OFF SW6 1 S10JTAG_BYPASSn OFF 2 M5JTAG_BYPASSn OFF 3 FAJTAG_BYPASSn ON SW1 1 MSEL2 ON 2 MSEL1 ON 7

8 Figure 4. DIP Switches Bottom View Figure 5. DIP Switches Top View ON 5. Turn on the power for the Intel Stratix 10 GX FPGA development board. The hardware systems is now ready for programming. 8

9 1 RapidIO II Reference Design for Avalon -ST Pass-Through Interface Figure 6. Reference Design Hardware Setup Power Cable FMC Loopback Card Intel FPGA Download Cable II Related Links Intel Stratix 10 FPGA Development Kit Default Switch and Jumper Settings Programming the FPGA You can program the FPGA by using any of the following methods: Using a Nios II Command Shell Perform the following steps to program the FPGA using a Nios II command shell: 1. On the Windows start menu, click All Programs > Quartus installation directory > NIOS II Command Shell <vesrion number>, to start a Nios II command shell. 2. Type the following command at the Nios II command shell: nios2-configure-sof -c USB-BlasterII [USB-1] -d 2 sri02_s10_avst_6g_de.sof Using the Programmer Perform the following steps to program the FPGA using the Programmer: 1. Launch the Intel Quartus Prime software. 2. Before you begin the FPGA configuration, ensure the following: a. The Intel FPGA Download Cable II driver is installed on the host computer. b. The board is powered. 9

10 c. No other application is accessing the JTAG chain. 3. Connect the Intel FPGA Download Cable II between your host computer USB port and the USB port on the development board. 4. On the Tools menu, click Programmer. 5. Click Auto Detect to display the devices in the JTAG chain and select a device. 6. Right click and select Change File. Then, select the srio2_s10_avst_6g_de.sof file from the project directory and click Open. 7. Turn on the Program/Configure option for the srio2_s10_avst_6g_de.sof file. 8. Click Start to download the srio2_s10_avst_6g_de.sof file to the FPGA. Configuration is complete when the progress bar reaches 100% Running the Design When the board is set up and the FPGA is programmed, you can start running the design: 1. Invoke the system console. This can be done at the Nios II command shell or from the Intel Quartus Prime software GUI. 2. In the command window, change your directory to system_console by typing the following command : cd system_console 3. Execute the following commands at the system console: source main_run.tcl cfig link cstats stats start stats 4. The traffic generator module starts to generate RapidIO NWRITE transactions with a default payload of 64 bytes. The default number of NWRITE transactions is 0xFFFFFFFF (4,294,967,295 decimal). You can stop the traffic generator by entering the stop command. The generated RapidIO transactions are being received at the traffic checker module since all the traffic is looped back through the FMC Loopback Card. You can view the transactions transmitted and received counts as well as other statistics by entering the link and the stats commands at the system console. 10

11 Figure 7. Link Command Execution 11

12 Figure 8. Stats Command Execution 5. Use Signal Tap to view the packet exchange. This reference design includes the Signal Tap file srio2.stp which monitors the gen_tx and the gen_rx interfaces of the RapidIO Avalon-ST pass-through interface. The figures below shows the Signal Tap activity. Figure 9. auto_signaltap_1 12

13 Figure 10. auto_signaltap_2 Related Links System Console User Interface Commands on page System Console User Interface Commands Please refer to the below table for the description of the user interface commands: Table 3. System Console User Interface Commands Command Description r rc ds es link cfig start stop send cstats stats reinit Toggles the RapidIO II IP reset input signal. Resets the Rapid IO II IP core. Toggles the Transceiver Reset Controller reset input signal. Resets the transceiver PCS and PMA. Disables the scrambler and descrambler in the RapidIO II IP core. Use for diagnosis purpose. Enables the scrambler and descrambler. Reports the status of the RapidIO link. Enables the Input and Output ports and disables Destination ID checking, randomly accepting all incoming request packets. Programs the number of packets to be transmitted to 0xFFFFFFFF and enables the traffic generator. The generator stops after transmitting 0xFFFFFFFF packets. Stops the traffic generator. Takes an integer value representing the number of packets to send. For an example, send 100: Generates 100 packets. Clear statistics counters. Report statistics counters. Toggles the PORT_DIS bit of register 0x15C causing an internal re-initialization of the RapidIO II IP. Helps in diagnosing link up issues. f4x Forces the RapidIO II IP into 4x mode. continued... 13

14 Command Description f2x f1x lps lpc lpt Forces the RapidIO II IP into 2x mode. Forces the RapidIO II IP into 1x mode. Loop back set, programs the transceivers into serial loopback, TX to RX at the PMA output buffers. Clears loop back. Clears the transceiver loopback and then sets it again, toggling serial loopback in the PMA output buffers Register Address Map Table 4. Register Address Map Module Base Address Offset Description Transceiver Reconfiguration Port at RapidIO II IP 0x0000_0000 Full transceiver PCS and PMA registers Please refer to the Logical View Register Map of L-Tile transceivers. Traffic Generator 0x0004_0000 0x0000 Main control [0]- Start traffic [4]- Stop traffic 0x0004 0x0008 0x000c 0x0010 0x0014 0x0018 0x001c Packet size [31:0]- Payload byte size. The default value is 64. Header size [31:0]- Packet header size in bytes. The default value is 12. IPG size [31:0]- Intel Packet Gap in cycles. IDLE cycles inserted bt the Traffic Generator between the packets at the Avalon-ST interface. The default value is 8. Packets to transmit [31:0]- Packets to be generated. Source ID [15:0]- Source ID value to be used in composed packets. The default value is 0xCCCC. Destination ID [15:0]- Destination ID value to be used in composed packets. The default value is 0x5555. Starting address [31:0]- Starting address use for NWRITE transactions to be generated. 0x0020 Priority continued... 14

15 Module Base Address Offset Description [1:0]- Priority to be used for NWRITE transactions to be generated. 0x0024 0x0028 RapidIO II IP Reset Control. [0]- Resets the RapidIO II IP. Transceiver PCS/PMA Reset Control [0]- Resets the transceiver PCS/PMA. Statistics Module 0x0005_0000 0x0000 Main Control [0]- Clears statistics 0x0004 0x0008 0x000c 0x0010 0x0014 0x0018 0x001c 0x0020 0x0024 0x0028 0x002c 0x0030 0x0034 0x0038 0x003c 0x0040 0x0044 0x0048 0x004c 0x0050 0x0054 Transmitted packet count Packets cancelled by transmit side Packet Accepted Control Symbols transmitted Packets-Retrys Control Symbols transmitted Packets-Not-Accepted Control Symbols transmitted Packet Accepted Control Symbols received Packet Retrys Control Symbols received Packets-Not-Accepted Control Symbols received Packet CRC Errors received Packets dropped by the Transport Layer Control Symbol Errors Base Device ID (small) programmed Base Device ID (large) programmed Port Initialized Link Initialized Port Ok Port Error Four Lanes aligned Two Lanes aligned TX Analogreset (one bit per lane) TX Digitalreset (one bit per lane) continued... 15

16 Module Base Address Offset Description 0x0058 0x005c 0x0060 0x0064 0x0068 0x006c 0x0070 RX Analogreset (one bit per lane) RX Digitalreset (one bit per lane) RX is LockedToData (one bit per lane) RX Sync Status RX Signal Detect Reset Controller TX Ready (one bit per lane) Reset Controller RX Ready (one bit per lane) Traffic Checker 0x0006_0000 0x0000 Main control [0]- Clears statistics 0x0004 0x0008 0x000c 0x0010 0x0014 0x0018 0x001c 0x0020 0x0024 0x0028 0x002c 0x0030 0x0034 0x0038 0x003c 0x0040 NREADs count NWRITEs count NWRITE_Rs count SWRITEs count Flow Control Types count Maintenance Read Request types Maintenance Write Requests types Maintenance Read Response types Maintenance Write Response types Maintenance Port Writes Data Stream Types count Doorbell Request Types Message Type count Response Types No Payload Message Response Types Response Types with Payload RapidIO II IP Register Access 0x0007_0000 Please refer to the Software Interface section in the RapidIO II IP core user guide Related Links Software Interface Logical View of the L-Tile ES-1 Transceiver Registers 16

17 1.5 Document Revision History for RapidIO II Reference Design for the Avalon-ST Pass-Through Interface Date Version Changes December Initial release. 17