Reconfigurable Backplane Topology

Transcription

1 Technical report, IDE0605, January 2006 Reconfigurable Backplane Topology Master s Thesis in Computer System Engineering Gunda Rajendra Prasad, Thenmatam Ajay Kumar, Kurapati Srinivasa Rao School of Information Science, Computer and Electrical Engineering Halmstad University i

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3 Reconfigurable Backplane Topology Master s thesis in Computer System Engineering School of Information Science, Computer and Electrical Engineering Halmstad University Box 823, S Halmstad, Sweden January 2006 iii

4 Description of cover page picture: Reconfigurable Backplane Topology. iv

5 Preface and Acknowledgement This thesis is a part of the work required for the fulfillment of our Master s degree in Computer Systems Engineering in January 2006, which was carried out in the CC-Lab, Halmstad University. We would like to thank our supervisors, Professor Magnus Jonsson and Mattias Weckstén, without whose continuous valuable guidance and patience this work would not have been achieved. We also wish to thank Thomas Munther for his kind suggestions to solve some Matlab problems. Gunda Rajendra Prasad, Thenmatam Ajay Kumar & Kurapati Srinivasa Rao Halmstad University, January v

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7 Abstract In the field of embedded computer and communication systems, the demands for the interconnection networks are increasing rapidly. To satisfy these demands much advancement has been made at the chip level as well as at the system level and still the research works are going on, to make the interconnection networks more flexible to satisfy the demands of the real-time applications. This thesis mainly focuses on the interconnection between the nodes in an embedded system via a reconfigurable backplane. To satisfy the project goals, an algorithm is written for the reconfigurable topology that changes according to the given traffic specification like throughput. Initially the connections are established between pairs of nodes according to the given throughput demands. By establishing all the connections, a topology is formed. Then a possible path is chosen for traversing the data from source to destination nodes. Later the algorithm is implemented by simulation and the results are shown in a tabular form. Through some application examples, we both identify problems with the algorithm and propose an improvement to deal with such problems. vii

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9 Table of Contents Preface and Acknowledgements... v Abstract vii 1. Introduction Goals Project Background Related Work SUNMAP Modular Interconnection System between PCB and Backplane Dynamic Reconfiguration Tutorial Background Reconfigurability Backplane Routers Topology Reconfigurable Topology System Architecture Algorithm Pseudo code Description of Algorithm Flow Chart Simulation Results Result of Example Result of Example Solution for Islands Conclusions and Future Work Conclusions Future Work References ix

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11 1. Introduction In embedded computer and communication systems, interconnection networks play an important role in deciding the overall performance. The network performance depends on the interconnection between the nodes, if at all the network cannot provide sufficient performance, the data will not arrive in time. The capacity demand for interconnection networks increase with the computing power of the nodes and additional pressure is placed on the communication network. In order to improve the performance and avoid communication bottleneck, an interesting solution is to make a reconfigurable interconnection topology. For example it changes network topology according to the communication requirements of a given program, it meets the future capacity demands for the interconnection network, and reduces the cost and the physical complexity of the interconnection networks. The concept of reconfigurable computer architectures was introduced by Gerald Estrin and his group at the University of California at Los Angeles in 1960 s [1]. Though reconfigurable computer architectures evolved long time ago, there were no success in building a reconfigurable computer and reconfigurable communication system. But since the last decade, the technology changed drastically and reconfigurable computing can be rarely seen [2]. Now a days different kinds of applications are used by parallel computers like weather forecast systems, radar signal processing systems, database systems, Web servers and data centers, etc. To satisfy these specific applications embedded computer and communication systems requires a high performance interconnection network. Generally regular topologies are widely used but to achieve flexibility, reliability, high performance and reconfigurability irregular or arbitary topologies with switch-based networks are efficient, to use [3]. Our thesis shows how to meet the demands of some of these applications according to the given communication requirements. The formed topology is a irregular/arbitary topology and we mainly focuses on interconnection between the nodes on printed circuit boards (PCBs) via backplane. A backplane is nothing but a switch-based network. 1.1 Goals The main aims of our project Reconfigurable Backplane Topology are to assume a backplane with reconfigurable topology that interconnects boards, each with a routing or switching chip, and to develop a simulator or a tool that chooses a topology of the backplane for a given traffic specification (throughput). To achieve these goals, one of our approaches has been to write an algorithm to choose the reconfigurable topology, which changes according to the given traffic specification like throughput. Another goal has been to implement the algorithm by simulation. 1

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13 2. Project Background This project is part of the Reconfigurable System Architecture project, which was started in January 2003 and it is the extension of the FASE (FPGA-based Application-Specific Embedded Processing) project and ended in Dec The research is performed at Halmstad University, Sweden (centre for Research on Embedded Systems). The Companies that are involved in this project are Ericsson, Ericsson Microwave Systems, HMS Industrial Networks AB, Innovative Team, and Combitech Systems, in addition to some co-operation with MIT, USA, and PACT Technologies, Germany. The main goal of this project has been to identify and evaluate different ways of utilising reconfigurability and modular approaches in the design of embedded computer and communication systems, and to calculate the efficiency of the system in specific embedded applications. A sub goal is to investigate how system architecture can make use of reconfigurability at all levels to gain flexibility and cost efficiency for industrial applications [4]. Sacki Agelis has studied in his thesis, for the degree of Licentiate of Computer Engineering, reconfigurable optical interconnection networks for high-performance systems. He focused on the different possible ways of interconnecting PCBs and a backplane by using optics in switches and routers. He has also shown how the interconnection network can be adapted (reconfigured) according to the demands of the currently executed application in radar signal processing embedded in a high-performance parallel computer system [2]. 3

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15 3. Related Work In this section, we describe different methods, which improve the performance of an interconnection network. 3.1 SUNMAP The important phase in the design of Network on Chips (NoCs) is the mapping of cores onto the most suitable topology for a particular application, for which, a tool called SUNMAP was designed [5]. Moreover, it selects the best toplogy automatically for a given application and maps the different cores on to the topology. Sunmap examines different design objectives, such as minimizing average communication delay, area, power dissipation subject to bandwidth and area restrication. It also supports different routing functions such as dimension ordered, minimumpath, traffic splitting and chooses the best topology from the library of available topologies for the given application. There are different types of standard topologies, like direct topologies and indirect topologies onto which an application can be mapped. Some of the direct topologies are Mesh, Torus, and Hypercube, in which a switch is connected to a single core. In indirect topologies a set of cores are connected to the switch, like 3-Stage Clos and Butterfly. SUNMAP has an interface to the xpipescompiler, which is a tool for instantiating network components (switches, links, network interfaces) using a library of composable SystemC soft macros [5]. After topology selection and mapping, the SystemC generates automatically, and describes interconnections between the network components and the cores. Figure 1: Design Flow of SUNMAP The above figure shows the design flow of SUNMAP, which consists of three phases. The routing function, design objective, and mapping different topologies with the topology library, are choosen in the first phase. To obtain feasible mapping, the area and bandwidth constraints are evalutated. In our thesis throughput demand of a given application is taken as a constraint while assigning physical links between the node pairs. The formed topology is an irregular topology but not fixed topology, whereas SUNMAP chooses a direct topology or indirect topology, which are fixed topologies from the topology library according to the area and bandwidth of the given 5

16 application as a constraint. The main advantage compared to the SUNMAP is that our algorithm supports a reconfigurable topology by which the interconnection network achieves a high flexibility and high performance. The area-power libraries and floorplanning are built in SUNMAP. The floorplanning finds the relative positions of the modules and it also finds the exact positions, area and size of the modules. The area-power libraries are used to find various switch configurations for different technology. In the second phase, the best topology is chosen with the help of area-power libraries and floorplanner by evaluating different topologies for several design objectives. In the third phase, the tool generates SystemC description of the network components using the xpipes compiler and xpipes architecture [5]. The above description briefly covers the SUNMAP, which is a tool used for selecting the best topology for a given application and producing a mapping of cores on to that toplogy [5][6]. 3.2 Modular interconnection system between PCB and backplane Agelis et.al presents a description of the interconnection of different nodes or modules in a printed circuit board (PCB) and backplane. They show an architecture design similar to the one used in our master s thesis. Thus we present a summary of their description from the collected source [7], which examines the building of a modular system by using optical interconnection network. The system contains some modules that are placed on a printed circuit board, where the modules are connected to each other by using an optical communication interface with a simple electronic router. The optical switching uses micro-electro mechanical system (MEMS) technology where packet switching over reconfigurable topologies is possible. The main advantages of optical interconnection is that it allows higher throughputs, increases I/O density, improves electromagnetic compatibility and simplifies cable solutions compared to traditional electrical solutions. Each single PCB consists of six modules on each side and each module has four optical channels connected to the switch on that PCB side, while the other side of the PCB has an identical interconnection architecture. Each module contains memory, one or several processing units and other necessary devices to handle basic control flows and power dependencies. Each module also has four vertical cavity surface-emitting lasers (VCSEL), four photo-detectors and one electronic router, which are used to communicate between the modules. A VCSEL converts an electrical signal to a light beam and transmits through a fiber link to the MEMS switch, where it is switched to the required destination and hits the photo-detector in the receiving module. Then it converts the light signal to an electrical signal. The message or data is transferred from the source to the destination address with the help of the electronic router present in a module. The topology can be reconfigured by using the state of popup mirrors in less than a millisecond. Some of the topologies that can be embedded on a PCB are mesh and ring. If it uses a ring topology, it can form a 10 Gbit/sec unidirectional ring with four fibers combined together and another possible configuration is to construct two rings, one 5 Gbit/sec in each direction (if each optical channel is assumed to have a bit rate of 2.5 Gbit/sec). Traffic can always be routed with the help of an electronic router present in each module to the final destination by passing several modules in the topology. Here source routing and cut-through switching are assumed. In cut-through switching, only the header of the packet is stored but not the whole packet as long as the output port is free. In [7], a complete interconnection system is described for both inter-pcb and intra-pcb communication. The main advantage of this 6

17 communication system is that it supports both reconfigurable topology and electronic routing to offer high flexibility and high performance simultaneously. In our thesis interconnection between the PCBs (intra-pcb communications) is described. Our algorithm also supports the reconfigurable topology and changes the topology according to the throughput and channel capacity, due to this the interconnection network achieves high flexibility and high performance. 3.3 Dynamic reconfiguration One of the advanced feature of a multicomputer is dynamic reconfiguration of the interconnection network, which reduces the communication overhead. The goal of the dynamic reconfiguration is to increase the multicomputer performance by means of minimizing the traffic of messages through the network. Here an algorithm for the dynamic reconfiguration of the network is described. In [8], a centralized switch control is choosen for dynamic network reconfiguration, where a master node (the system controller) controls the reconfiguration by means of a control bus. The network configuration protocol works in the following way: When a node decides that it is necessary to reconfigure the network, it sends a signal to the system controller through the control bus. Then the system controller sends the signal to all the nodes telling that they should stop sending messages to each other because the network reconfiguration is in process. To minimize the reconfiguration time and to decrease the cost, the nodes are ordered to stop transmitting the messages even to the intermediate nodes. The node that made the request sends the reconfiguration data to the system controller to carry out the reconfiguration. Then the system controller modifies the interconnection network topology according to the specific application. After establishing the new configuration, the system controller sends this configuration to all the nodes and allows node communication again. This protocol is easily implementable by using the control bus available in the SN 1000 architecture, which does not add message traffic to the network. Thus it is clear that every node sends reconfiguration requests to the system controller, which may lead to communication overhead. For moderate systems up to 64 nodes, the system control will not represent a bottleneck. But for larger systems, the supernode architecture requires a two-level switch and more than a single control bus. The algorithm used for the dynamic reconfiguration of the interconnection network is two parts: one for the system controller and another one for the remaining nodes. These algorithms are introduced by the system controller or the nodes in the run-time kernel. Initially the algorithm is developed and executed in each node, which is the main and most difficult part. Then the algorithm is executed on the system controller. The algorithm has the following properties: local reconfiguration, preserves the topology, is based on a cost function, produces a small alteration in the network and uses two thresholds for network reconfiguration [8]. The main idea of the algorithm is described as follows: when the traffic between a pair of nodes is extreme in degree. Then the algorithm will try to put the source node close to the destination node by exchanging the positions of the source node and its neighbour or the destination node and one of 7

18 its neighbors. However, the implementation of this algorithm is distributed, where each node taking into account the information recorded locally [8]. The main difference is that the algorithm used in our thesis chooses the path between the source node and the destination node according to the minimum number of hops and keeping the throughput as a constraint, whenever the traffic between the pair of nodes is extreme in degree. The algorithm reduces the total message traffic in the network and in the message traffic through the most saturated nodes. Thus we can say that the overall behaviour of the algorithm is good, and it improves the performance of multi-computers. 8

19 4. Tutorial background Some basic definitions and terms that are included in our project are discussed below: 4.1 Reconfigurability Reconfigurability which is in many devices, is the main factor responsible for many successful results, like the field programmable device, which is said to be successful by combining user programmability, its operating speed and rapidly increasing logic integration. Its categories are the static and dynamically reconfigurable logic, which introduce new characteristics in the digital systems by extending its digital space. Dynamically reconfigurable logic implementations in the applications, which are widely used, depend on the development of new technologies and CAD Tools. Though it is a quite simple technique conceptually, it is somewhat difficult to be implemented despite the fact that its advantages are appreciable. Its new developments include field programmable logic, FPGA s etc. The main motivation for the using of the dynamically reconfigurable logic is the adequate use of the algorithms by implementing them on stored program computers which increase the logical capabilities of the programmable devices and map active logic to FPGA resources at any given time. In the dynamically reconfigurable logic, the adaptation of top-down and bottom-up approaches are common. The top-down approach is used for finding out the problems encountered in the dynamically reconfigurable designs and the bottom-up approach is used to realise whether it is a dynamically reconfigurable application or not [9]. 4.2 Backplane A basic backplane is a circuit board, which has different pins that are connected to the different connectors in parallel to each other to form a computer bus, which transfers the data or power within the components in a computer or different computers. It acts like a backbone to connect different printed circuit board cards together to form a complete computer system. The backplane bus is the main system bus that connects together some components like CPU, memory, I/O, peripherals, and networking devices. But to keep up the demands of today s high-performance of CPUs and their interconnection requirements, we need a new generation of backplane to meet the present requirement [10]. 4.3 Routers A router is a networking device that transfers data packets to their destinations by a process called routing. According to the OSI seven layered protocol stack, routers appear in the 3 rd layer of the stack i.e. in the networking layer and are mostly associated with the Internet Protocol (IP) in the TCP/IP protocol stack. In the earlier days of computer development, the general purpose computers were used as routers for forwarding the data packets, but now highly specialized computers have been developed with additional hardware for high speed routing and for other extra functions like IPSec (IP security) encryption. A router maintains a routing table, which stores a list of the best routes (or next hops) that are efficient for certain destinations and their routing metrics [11]. 9

20 4.4 Topology Topology is the branch of mathematics concerned with the study of topological spaces, in which the main concepts are convergence, connectivity and continuity. The collection of two or more nodes connected together by links to form a network is called network topology. The main things to consider while constructing a physical topology are distances between the nodes, physical interconnections, transmission rate, and/or signal types [1]. Some different types of network topologies are mesh topology, ring topology, star topology, tree topology and fully connected topology. A hybrid topology is a combination of two or more network topologies Reconfigurable topology The reconfigurable topology architecture contains a programmable switch that allows selecting a physical topology according to the logical topology matching of the application communication patterns. The main advantage of assuming a reconfigurable topology is that a single architecture acts as a special-purpose architecture that supports the communications patterns of particular algorithms or algorithm steps efficiently [12]. 10

21 5. System Architecture The system architecture in our thesis is mainly considered with the interconnection between the nodes (PCB) and the backplane. Interconnection between the nodes within the PCB (intra-pcb) and between PCBs (inter-pcb) and backplane are shown in Figure 2. But our algorithm is used for interconnection between the nodes (inter-pcb). Consider there are N printed circuit boards (PCBs) and each PCB has M sub-nodes.the sub-nodes are represented by A i, where i = 1, 2, 3 M and PCBs are represented by B j where j = 1, 2, 3 N. Figure 2: Interconnection between the nodes (PCB) and the Backplane 11

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23 6. Algorithm As we move our steps ahead towards the goal: As a first step of our project, we had written an algorithm that solves our tasks. Initially we represented our algorithm as a pseudo code, then it is described in text and it is also shown as flow chart. Finally we described how it is implemented by simulation in MATLAB. The full algorithm is implemented but more like in a simulation environment instead of the form of a practical tool. 6.1 Pseudo code Step 1: 1. Initialization. Input: G TH is the given throughput for a node pair (i, j), which is stored in a Two dimensional array (input [N] [N] = G TH ). CC is the channel capacity for a physical link. N is the maximum number of nodes (PCBs). M is the number of ports on the switch for a node, which is stored in an array (Ports [N] =M). Output: Assigned links between the nodes and available throughputs are shown in a Two dimensional array and ports left are shown in one dimensional array. 2. K = (N*M)/2; / * K is the total number of physical links */ W ij =1 (initially); /* W ij is a variable */ 3. Assigning physical links between the node pairs. while (( K!= 0) && (W ij > 0)) [W ij, indices] = max (input [N] [N]); /* W ij is the maximum throughput value which is chosen from the given input data, while the indices gives i, j (nodes) */ if ((ports(i)!=0) && (ports(j)!=0)) connect (i, j); /* a physical link is assigned between a node pair (i, j) */ W ij = W ij - CC; ports (i) = ports(i) - 1; ports (j) = ports(j) - 1; K = K-1; else temp [i] [j] = W ij ; /* temp[n] [N] is a temporary array which stores the W ij value for corresponding node pairs, whose ports is equal to zero */ input [i] [j] = input[i] [j] -W ij ; /* remove the W ij value from the input array */ end if end while 4. To add all the possible physical links between the nodes until K becomes zero While (K! = 0) [a, i] = max (ports (N)); /* a is the maximum value and i (node) is the indices of the ports [N] left array */ for r = 1 to M 13

24 for k2 = 1 to N if (ports(k2) = = r) j = k2; /* j (node) is the index of the ports [N] array */ if ((i!= j) && ((Ports (i)!= 0)&& (Ports (j)!= 0))) connect (i, j); /* a physical links is assigned between a node pair (i, j) */ ports (i) = ports (i) - 1; ports (j) = ports (j) - 1; K = K-1; A TH [N] [N] =A TH [N] [N] + CC; end if end if end for end for end while 5. A TH [N] [N] = input [N] [N] + temp [N] [N]; /* A TH [N] [N] is a output array (which stores the throughput values reduced from the G TH by CC) after establishing all the available physical links */ Step 2: Input: Assigned links between the nodes and available throughputs (A TH [N] [N]) are shown in two dimensional arrays which are taken from step 1. For source node (i) and destination node (j). G TH is the given throughput for a node pair (i, j). Output: A possible path from a given source to destination, considering the throughput. 1. Choosing a possible path using breadth first search: this algorithm run for all pairs of source (i) and destination (j) nodes with a throughput demand left in the A TH [N] [N] array. queue Q = new queue; Q.enqueue (i); /* insert the source node into the queue */ while (!Q. isempty ( )) v = Q.dequeue ( ); /* remove the node from queue as first in first out */ u = first successor (v); /* first successor means first adjacent node of v */ while (u!= null) if (G TH < = A TH ) Q.enqueue (u); end if if ((G TH < = A TH [v] [u] ) && ( u = = j)) return path; end if u = next successor (v); end while end while 14

25 6.2 Description of algorithm Here the algorithm has been categorized into two steps: In the first step, we establish connections between the nodes with higher throughput demands and then algorithm checks whether the total number of physical links become zero or not. If the total number of physical links did not become zero then it will assign the physical links between the maximum number of ports left nodes to the minimum number of ports left nodes until it becomes zero and, in the second step, we choose a possible number of paths between the nodes for transferring the data. Initially the given throughput data is stored in a two dimensional array from which we choose the maximum throughput demand value W ij, and then remove that particular value from the two dimensional array for assigning a link between those nodes. W ij is the throughput demand between the source node (i) and the destination node (j), for which a connection has to be established. Before establishing a connection between the nodes, each time it checks the condition while (K= ((N*M)/2) && (W ij > 0)) where K is the total number of links that are available for establishing the connections between the node pairs. Here N is the total number of nodes that are present in a communication system or architecture and M is the number of ports for each node, and the total number of links available would be half of the total number of nodes multiplied by the ports, which is assigned to a constant K. After establishing a connection between those nodes, it decrement the throughput value by the Channel Capacity (CC). Again, that decremented throughput value will be added into the array and once again, the whole process of selecting a maximum throughput value W ij will be continued. This process continues, until the given throughput is less than zero or the total number of links K becomes zero. The decremented throughput value is stored in the two dimensional array as the Available Throughput value A TH (which is considered as constraint to be checked while choosing possible paths in step 2). Each time, after establishing a connection between a pair of nodes, the total number of links is decremented by 1 and the port value of the source and the destination nodes are decremented by 1 and given throughput is decremented by channel capacity (CC). Also the number of allocated links (N A ) of the source node and the destination node are incremented by 1. After establishing the connection between the nodes according to the given throughput then it will check whether K is equal to zero or not. If K is equal to zero then algorithm will stop, otherwise it will check the port left record. Then the algorithm establishes the connections between the maximum number of port left node to the minimum number of port left node until K becomes zero. This is clearly shown in the section 6.1, 4th step. All the details like assigning the number of physical links between the nodes and Available Throughput values (A TH ) are stored in a two dimensional array and number of ports left for a node are stored in an array. Collection of all these different arrays is called a record, which is maintained in order to find a possible path for transferring the data in the step 2 of algorithm. 15

26 Record: Source i Destination j Given Throughput G TH Assigned Links N A Assigned Ports P A i j Ports Left i P L j Available Throughput A TH = = = -0.1 In the above example Given Throughput G TH is an extra column, which is shown as a record. But actually the Given Throughput data is stored in the two dimensional array as input. The second step of our algorithm is to find possible paths in a formed topology by using breadth first search. The path is chosen according to the minimum number of hops and Available Throughput in a topology. Choosing a possible path The breadth first search (BFS) algorithm takes the source node as a root node. From that node it will travel to all the successors of a root node before visiting any of those successors and it also checks the Available Throughput, whether the source node is equal to the destination node or not. So, breadth first traversal tends to create very wide short trees. The algorithm for finding possible paths is described as follows: node queue is initially taken, which is empty. Queue is one data structure in which we store nodes temporarily as first-in-first-out. Breadth first search starts the traversing by taking the source node as a root node. It checks whether the source node is NULL or not. If it is not null, the source node will be inserted into the queue, and now the queue is not empty, so first it empties the queue by taking the source node from the queue. Then, it visits all the successors of the source (root) node. By checking the condition, whether the Available Throughput is greater than or equal to the Given Throughput and if the source node is equal to the destination node or not. If this condition is satisfied, it will insert that particular node into the queue. If the node is not equal to the destination node, it will go for the next successors, otherwise, if it is equal to the destination node, then it will trace the path from the destination node to the source node and store the path in the linked list and return it. While returning the path, it considers the minimum number of hops and Available Throughput. Thus by using breadth first search, we can find possible paths from the formed topology. This is the brief description of an algorithm. The detail description is given in section 7.1 with results by taking an example. 16

27 6.3 Flow Chart Step1: Assigning physical links between the nodes 17

28 Step2: choosing a possible path 18

29 7. Simulation Results As a second step of the project, we have implemented our algorithm using MATLAB in which, we have clearly shown all the steps of the algorithm. 7.1 Result of Example 1 Given Throughput (G TH ): Figure 3: Topology as input Table 1 19

30 Step1: According to our first step, an array editor is taken, in which we are giving the input values from the Figure 3, known as Given Throughput (G TH ). The number of rows and columns are equal to the given number of nodes. In this example N = 14, which means the total number of boards/nodes are 14. In addition to this, the maximum bandwidth value and the maximum number of connections are establised in between each pair of nodes, which depend on the number of ports per each node in the architecture. The number of ports is M = 8, which means the number of ports for each node is 8. According to this, the number of connections that can be established for each node is restricted to 8 and the channel capacity is 1 unit (unit may be GB/sec or MB/sec). The maximum bandwidth available for transferring the data is 8 units per each node. Assume all the nodes are connected in a bidirectional way. To show this, we have given the same input values for both directions, for example (1, 5) = (5, 1) = 2.8 (same value) as shown in the above Table. For establishing connections between the nodes, first the process checks the maximum throughput demand value (G TH ). From the Table 1 the maximum throughput value is 2.8. After choosing a maximum throughput demand value, it establishes a connection between that pair of nodes. Then the corresponding node ports are decremented by 1 port, and at the same time the corresponding Given Throughput value is decremented by the channel capacity i.e.1 unit, which is shown in Table 2. Given Throughput (G TH ): Table 2 20

31 Table 2 shows the Given Throughput demand value (G TH ) after establishing a connection and decremented the corresponding throughput value by 1 unit. Step 2: The possible number of connections are established between the given pair of nodes in step 1. The results are shown in the Table 4. The amount of data that are remained in the Given Throughput demand value (G TH ) table is known as the Available Throughput value (A TH ) (that is show in Table 3). That is a constraint that should be checked in the second step of an algorithm when choosing the paths. Table 3 shows the Available Throughput. Based on this data, step 2 of our algorithm chooses a shortest path for the traversal of data. We used breadth first traversal, which travels in a tree (level-by-level) fashion. To choose a shortest path it checks the Available Throughput at all the levels, level-by-level and finally it chooses a shortest path from source to destination. Available throughputs are shown in the Table 3, where negative values are called Available Throughput. But ignore the negative sign and consider the value only. Since, in simulation process, after establishing each connection, the corresponding value of Given Throughput is decremented by 1 unit. At the same time the number of ports is also decremented by 1 unit (as shown in Table 6), which means one connection has been established between that pair of nodes. As this process continues, and the required number of connections are established, the value of Given Throughput is completely decremented and runs into the negative value. Available Throughput (A TH ): Table 3 21

32 Example: Given Throughput, value between one pair of nodes ((1, 5) or (5, 1)) is 2.8 and the number of connections established for that particular pair is 3, so the Available Throughput is 0.2 (2.8-3 = -0.2). Hence, ignore the negative sign and consider only the values shown in Table 3. Step 3: Table 4 shows the number of connections established between each pair of nodes. Here, the number of connections made for each pair of nodes depends on the Given Throughput value. Connections: Table 4 The number of ports assigned and left is shown in Tables 5 and 6 respectively. Here, we took a one dimensional array with an equal size of N, with 8 as the values for each node because, as we mentioned above: each node has 8 ports. And according to step 1 as and when a connection has been established between a pair of nodes, the port values are decremented by 1 unit, in the corresponding node s place. According to Table 5, values like 5, 6, 8 etc represents the number of ports assigned. In case of value 5 the number of ports left are 3 (according to Table 6) and in the same way 2 for 6 and 0 for 8. The tables Given Throughput (G TH ), Available Throughput (A TH ), Assigned links/number of connections established, and the Ports Assigned and Left, all are maintained as, records. 22

33 Assigned Ports: Ports Left: Table Table 6 Step 4: After establishing the connections between the nodes according to the Given Throughput the formed topology is shown in Figure Figure 4: Resulted topology after establishing the physical links The second step of an algorithm is to choose a shortest or possible path according to the Available Throughput value and minimum number of hops. Consider an example for choosing one possible path between source node 4 and destination node 14 and the Given Throughput 0.2 units. Figure 4 shows how the algorithm chooses a path, where the source node is taken as a root node. 23

34 (2,-0.2) 4 (1,-0.2) (2,0) (3,-0.2) (1,-0.2) (3,-0.8) (3,-0.8) 9 (1,-0.8) (1, 0) (1,-0.6) (2,-0.1) (3,-0.4) (1,-0.6) 13 (3,-0.9) (2,-0.8) 3 (3,-0.6) 11 (3,-0.7) (1,-0.5) 7 Figure 5: Topology for choosing the paths According to Figure 5, the values between each pair of nodes, given as (2, 0.2) and so on are the values which, are showing the number of links (from Table 4) and the Available Throughput (from Table 3) between that particular pair of nodes. Now the algorithm traverses by taking source node 4 as the root node. The path starts from the root node and traverses all its successor nodes in a level-by-level fashion and checks whether the Given Throughput is less than or equal to the Available Throughput. It also checks whether the node is the destination node or not at each level of its travel. If the Available Throughput satisfies the bandwidth requirement of the traversing data, it travels that path else stops its traverse along that path, at that particular stage without moving further and looks for all the other possible paths through which it can traverse. At any stage of its travel, as soon as it found its destination, the travel along all the paths stops at that level and returns the path from the source node to the destination node. Since, 14 is the destination node in this example, the tree starts its travel at the root node/source node 4. First it checks the Available Throughput value of its successors 1 and 6. Since, both the nodes satisfy the bandwidth requirement of the traversing data, the algorithm traverses those nodes. 24

35 Now the source nodes are 1 and 6, which starts their traversal from here and check their successor nodes. Node 1 checks 2, 5, 8, and node 6 checks 8 and 3, to see whether they meet the bandwidth requirement. Figure 4 shows that node 2 from 1 and node 8 from 6 doesn t meet the bandwidth requirement, so the algorithm stops its traversal along these nodes and traverse along other nodes. At this level, we can see the destination node reached from node 5, so the algorithm stops its travel here and returns the path as Hence, as Figure 5 illustrates, the bold lines indicate the path. Step 5: Result showing choosed path: Path = Result of Example 2 This example was borrowed from a published paper [13]. Figure 6 represents the data flow between the computational modules with throughput demands; this kind of application is a radar signal processing system. The 12 th node is a distribution module, while the 11 th node represents the collection module. Figure 6: Topology as input The data represented in Table 7 is taken from the above figure. According to this example the number of nodes is N = 12 and the number of physical links is M = 3, while the channel capacity of each physical link is 50 MBytes/sec or 400 MBits/sec. The given application is a directed graph. In this example also, it is shown that connections are established in the same fashion as it was done in the previous example and here the Given Throughput data is shown in Table 7, while the Available Throughput is shown in the Table 8. 25

36 Given Throughput (G TH ): Available Thorughput (A TH ): Table Table 8 26

37 According to this example, after establishing some connections between a pair of nodes the physical links/ports become zero (as shown in Table 11), as we decrement the value of ports at the corresponding nodes after each connection. We encounter the problem that a connection cannot be established for the node whose number of ports left is zero. In such cases, that data, which need a connection, must be sent by routing from other connections that are having the Available Throughput, and which satisfies its bandwidth requirement. This is done in the second step of our algorithm. Connections: Assigned Ports: Table Table 10 Ports Left: Table 11 27

38 Figure 7 is the resulted topology after assinging the physical links between the nodes. It shows two topological islands, which is the main problem in this application. (1,0MB) (2,-25MB) (1,-25MB) (1,-45MB) 7.3 Solution for Islands Figure 7: Resulted topology after establishing the physical links In the above example, we faced a problem of the formation of topological islands without any connection between them. To solve this problem one of the solutions is to increase the channel capacity from 50 MBytes/sec to 100 MBytes/sec. By increasing the channel capacity of a physical link, some nodes require only one physical link instead of two links. By this, the physical links can be saved and used for other connections. The channel capacity is changed in Example 2 to 100 Mbytes/sec and is considered as a bidirectional graph. Here we are representing it bi-directional because it will be useful for choosing the paths in step 2 of algorithm. Given Throughput is taken as input, which is shown in Table 12. The algorithm is implemented and finally the results like Available Throughput, connections between the nodes and ports left are shown in the Tables 13, 14 and 15 respectively. 28

39 Throughput(GTH) when connected Bi-directionally: Table 12 Availabe Throughput(ATH) when connected Bi-directionally: Table 13 29

40 Connections when connected Bi-directionally: Ports Left: Table Table 15 Figure 8 is the resulted topology after establishing the physical links between the nodes. It shows two topological islands, where the 10 th node is left free without any connections. 30

41 (1,-95MB) EACH 6 12 (1,-25MB) (1,-25MB) 1 2 (1,-50MB) (1,-75MB) (1,-75MB) (1,-50MB) (1,-95MB) (1,-95MB) (1,-95MB) Figure 8: Topological islands are formed after establishing the physical links. To solve the problem of topological islands, the algorithm checks for the number of ports left in Table 15. If any one of the nodes has maximum number of ports left (M = 3), it is said that the topological islands are formed. Then a physical link is established between the node with the maximum number of ports left and minimum number of ports left nodes, which is shown in the Figure 9 with dotted lines. We can see this result in Table 14 where value 1 with bold letter in the places (10, 12) and (12, 10) represents such a connection between those nodes. The 4 th step in section 6.1 performs the operation of connecting all possible links until the total number of physical links becomes zero. After performing this operation the ports left are shown in the Table 16, assigned links are shown in the Table 14 where value 1 with bold letter and the resulted topology is shown in Figure 9, where we can see that the topological islands problem was solved. Ports Left: Table 16 31

42 (1,-95MB) EACH 6 12 (1,-25MB) (1,-25MB) 1 2 (1,-50MB) (1,-50MB) (1,-100MB) (1,-75MB) (1,-75MB) (1,-100MB) (1,-100MB) (1,-100MB) (1,-95MB) (1,-95MB) (1,-95MB) 11 Figure 9: A Topology where problem of island was solved After executing step 1 of our algorithm the remaining application demands are satisfied by choosing the path in step 2. One example is considered for explaining the procedure of choosing paths by taking source node as 3 and destination node as 10 and Given Throughput (G TH ) 5MB. According to Figure 10, the values between each pair of nodes, given as (1, 50MB) and so on are the values which, are showing the number of links (from Table 14) and the Available Throughput (from Table 13) respectively, between that particular pair of nodes. Now the algorithm traverses by taking source node 3 as the root node. The path starts from the root node and traverses all its successor nodes in a level-by-level fashion and checks whether the Given Throughput is less than or equal to the Available Throughput. It also checks whether the node is the destination node or not at each level of its travel. If the Available Throughput satisfies the bandwidth requirement of the traversing data, it travels that path, otherwise it stops its traverse along that path, at that particular stage without moving further and looks for all the other possible paths through which it can traverse. At any stage of its travel, as soon as it found its destination, the travel along all the paths stops at that level and returns the path from the source node to the destination node. Since 10 is the destination node in this example, the tree starts its travel at the root node/source node 3. First it checks the Available Throughput value of its successor nodes 1, 6 and 7. Since all the successor nodes satisfy the bandwidth requirement of the traversing data, the algorithm traverses those nodes. 32