Smart Card ICs. Dr. Kaushik Saha. STMicroelectronics. CSME 2002 (Chandigarh, India) STMicroelectronics
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1 Smart Card ICs Dr. Kaushik Saha STMicroelectronics CSME 2002 (Chandigarh, India) STMicroelectronics
2 ST Products & Solutions
3 Agenda Smart cards market overview Issues in the Smartcard Business ST Solutions
4 TAM Evolution Million Units Mobile application - Smart cards IC s increase. A second boom banking schemes ID & authentication Pay-TV Mobile Pay tv & IT Others Financial Govern. & ID
5 Present Financial Cards market split Multi-appli. Market split in Mu (%) Standard : Open platform -Multos - WfSC 2 Proprietary : MPCOS - Payflex - TIBC 9 Loyalty Proprietary solution only 11 E-Purse Standard : CEPS NS* Proprietary : GeldKarte Proton - Moneo 37 Débit/Credit Standard : EMV - UKis 11 Proprietary: B0' 30 Source ST NS : Non Significant
6 Multi-application focus Multi-application means several things : By segment of market Multi-application within the same market Multi-application inter segment Through technical implementation Application in hardware (ROM) Download of applet in memory (eeprom / flash)
7 Standardization Smart card standardization is driven from two sides: the international standards organizations (ISO, ANSI, CEN, etc.). w the industry based on emerging markets and products. Eg. Visa, Mastercard and Europay jointly defined standards for debit/credit applications - EMV standard. Eg. industry driven standards PC/SC and the OpenCard Framework define guidelines and interface definitions for smart card applications.
8 Interoperability Ability to support the same functionality using different smart cards with different protocols and different data organisation. High-level abstraction of data objects and access mechanisms is required, using a common interface and with card-specific details hidden from application.
9 Security Security of a Smart Card chip results from the combination of : Technology design (hardware features) firmware (embedded software) manufacturing environments application software At each level, the concern is to achieve a maximum level of performance in terms of confidentiality, integrity and availability of confidential information The highest level of coherence has to be reached between various security mechanism
10 Common Technical Standards Any card project has to be compliant to: ISO7816 (1 to 4) for contact. ISO14443 (Part A or B) for Contactless. OS MULTOS Java Card Windows Multi applications X x x x Security Xxx Xx Xx? Interoperability NO X X X Multi-Sourcing NO Poor Xx Xx Post Issuance Writing NO NO xx Xx
11 Market Requirements for Smart cards Higher Performance Larger Memory Sizes Increased Security Memory Partitioning Cost effective Technologies Crypto Capability Contact less Solutions
12 Secure Single Chip Layout
13 STM Product Portfolio Performance Products tailored to market needs 32 bit RISCcore Direct JAVA byte code interpretation Fast crypto software computation RF capability ST22 Family EEPROM: 2Kb - 66Kb ROM: 23Kb - 96Kb RAM: 1Kb - 4Kb Crypto, RF, MMU Custom logic ST19/X Family EEPROM: ROM: RAM: Crypto, RF 512B - 16KB 6Kb - 22Kb 128B - 512B ST16 Family
14 Conventional EDP System architecture OS Service Calls (OS Specific) OS Kernel (Win, Unix) H/W (CPU, Memory, Peripherals Applications (m/c specific executable code) Application must be tailored & targetted to CPU and OS. Long Development Cycle, Non-Portability, Non-OPEN
15 JAVA Virtual Machine OS Service Calls (OS Specific) OS Kernel H/W (CPU, Memory, Peripherals Generic Service Calls Abstract Virtual Machine Java Apps (m/c independent executable code)
16 Java Benefits and Issues Java benefits Application code portability across platforms Write once, Run everywhere Security mechanisms Adapted to downloading Java issues Slow execution when implemented fully in software, 10 to 50 x slower than compiled code Memory large footprint Standardisation
17 Standard JVM SmartJ JVM JavaCard API JavaCard API HARDWARE JavaCard VM Class GC, Loader JavaCard Bytecode JavaCard JPC Interpreter Decoder JSP JavaCard Runtime Env. HSI Execution Native Decoder Unit PC SP JavaCard VM Class GC, Loader Long Bytecode Interpreter JavaCard Runtime Env. HSI JavaCard JPC Decoder Native Execution Unit JSP PC Decoder SP
18 JavaCard Hardware Execution ROM JavaCard bytecodes EEPROM RAM MPU JavaCard Decoder Native instructions Data ST22 CPU core ISO7816 ASI
19 SmartJ Architecture POWER MGMT ST22 32-bit CPU MPU RAM RAM BUS ROM BUS TIMER SECURITY RANDOM CIC ASI PERIPHERALS ISO7816 Serial CLOCK MGMT ROM EEPROM
20 CPU SmartJ Features 32-bit RISC microprocessor architecture, 24-bit linear memory addressing Hardware JavaCard -2.1 execution MHz SECURITY DES cryptography RSA and Elliptic Curve cryptography Memory Protection Unit and instruction-set security features for code/data firewalling large ROM up to 128 Kbytes large EEPROM up to 64 Kbytes
21 SmartJ Security IC hardware security DPA / SPA countermeasures Memory observation countermeasures Up to 40 MHz on-chip generation internal clock Large power supply range with on-chip regulator 2.7 to 5.5 V in 0.35 µm process 1.6 to 5.5 V in 0.18 µm process Dual execution mode Supervisor / User Specific asynchronous reset and clear all registers instructions
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