Board. IC693CPU351-DG CV3A1 R05 or later U105 U106 IC693CPU351-DG CA3A1 R02 or later U3. Upgrade Kit For Upgrading To

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1 Restarts for autonumbers that do not restart in each chapter. figure bi level 1, reset table_big level 1, reset chap_big level 1, reset app_big level 1, reset figure_ap level 1, reset table_ap level 1, reset figure level 1, reset table level 1, reset these restarts must be in the header frame of chapter 1. a:ebx, l 1 reseta a:obx:l 1, reseta a:bigbx level 1 reseta a:ftr level 1 reseta c:ebx, l 1 reset1 c:obx:l 1, reset1 c:bigbx level 1 reset1 c:ftr level 1 reset1 Reminders for autonumbers that need to be restarted manually (first instance will always be 4) let_in level 1: A. B. C. letter level 1:A.B.C. num level 1: num_in level 1: rom_in level 1: I. II. III. roman level 1: I. II. III. steps level 1: IMPORTANT PRODUCT INFORMATION Product: READ THIS INFORMATION FIRST IC693 CPU Firmware, Release 6.61, for Full Production This is a feature release of the IC693 PLC firmware. This release supports a Bumpless Run-Mode Store of a program from IC641 programming software, version 6.60 or later. This feature is described below. New Catalog Number Replaces IC693CPU351-BC, CD, DD, DE, DF Hardware and software identification for this release is summarized in the following table. Catalog Number Board Identification Board Revision EEPROM Location CV3A1 R05 or later U105 U106 CA3A1 R02 or later U3 Packaging Note Update Information The user manual is not shipped in the box with every product. User manuals are provided as a complete set in a library with IC641 Programming Software products, are available on CD-ROM, or can be ordered as individual manuals. Upgrade kits are available to upgrade existing units with release 6.52 or earlier firmware to release 6.61 firmware. This upgrade is optional. Existing units may be upgraded for a charge by ordering the field upgrade kit. Upgrade Kit For Upgrading To 44A G05 IC693CPU351-DFor earlier versions Functional Compatibility IC641 programming software version 6.60 or later must be used for the Bumpless Run Mode Store feature to be available.

2 2 Documentation The following table lists the applicable documentation for the model 351 CPU. Documentation is also available on CD-ROM, IC690CDR002*. (* current version will be shipped). Catalog Number User Manual Programmable Controller Installation Manual (for IC693 Products) Operational Notes UVEPROM Change 1. The User Program, configuration, CPU ID (used for SNP communications), and status tables will automatically be cleared when the CPU firmware in flash memory is changed using the firmware update utility. You will need to restore these if upgrading from a previous CPU version. The user program, configuration, and status tables can be restored from an IC641 programming software folder or flash memory. The SNP ID must be set separately, using IC641 programming software or the Hand- Held Programmer. FIRMWARE UPGRADE PROCEDURE 2. The Model 351 CPU operating firmware is stored in flash memory. The firmware upgrade is provided on a floppy disk and must be serially downloaded from a Personal Computer. An IBM AT compatible or better PC with a minimum 640K of RAM, one 3.5 or high density 5.25 floppy drive, MS-DOS version 3.3 or later, a hard drive, and one RS-232 serial port is required. In addition, a serial cable is required. The following serial cable kit is available: IC690ACC901 Miniconverter Kit with cable (RS-232/RS-485) Optionally, the cable can be assembled from the following parts: IC690ACC900 RS-232 to RS-485/422 Converter Unit IC693CBL Pin RS-485 Serial Cable IC690CBL Pin RS-232 Serial Cable * IC690CBL702 9-Pin RS-232 Serial Cable * * Only one of these cables is required. Selection depends on PC Serial Port Connector. Ethernet Interface Module Compatibility 3. All IC693 Ethernet Interface (IC693CMM321) modules used with release 6.5 or later of the IC693 PLC should be updated to release 1.10 or later of the IC693CMM321. IC641 TCP/IP Ethernet software requires both CPU release 6.5 or later and IC693CMM321 release 1.10 or later

3 3 Battery-Less Operation 4. When using an IC693CPU340, IC693CPU341, or IC693CPU351 CPU in a battery-less system, a standard 0.1 berg jumper should be installed across either of the two power supply battery connectors to ensure proper operation of the CPU. This jumper should not be installed if a battery is plugged into either the power supply or CPU battery connector. Retentive Warning 5. The USE WRN message may be displayed inappropriately by the Hand-Held Programmer. The program check function can be used to determine if a coil is being used multiple times. New Features and Functionality Bumpless Run Mode Store (BRMS) Currently, with an IC693 PLC in STOP mode, pressing ALT-S (holding the ALT key and S key simultaneously) while in BLOCK EDIT mode will store changes to a program to the PLC. Prior to release 6.61 of the firmware and IC641 programming software, this operation was not allowed while in RUN mode. However, this feature allows editing (changing, adding to, or deleting from) a program while ONLINE, in RUN mode, and logic equal. This will cause BLOCK EDIT mode to be entered. Upon completion of the editing, ALT-S may be pressed, and the PLC will be seamlessly updated resulting in a LOGIC EQUAL state. Only one subroutine (in this discussion of BRMS, subroutine refers to either a subroutine or the main program block unless otherwise specified) may be modified at a time, and there must be enough unused, unfragmented memory to store the subroutine that is being modified and the main program, in addition to the memory that is already being used. The requirement for the main program is because it is always restored during a BRMS, even when another subroutine is edited, because it is the block that calls the subroutine. For example, if there is a 2K byte chunk of user program memory available, then a subroutine and main program of size less than 2K may be modified and stored while in RUN mode. However, if you had a subroutine and main program that totaled 2.5K in size and added one rung to the subroutine, then it would not be possible to do an ALT-S while in RUN mode since both the old and new copies of the subroutine (and main) must be maintained for a brief period in the PLC to perform a RUN mode store. However, this 2.5K main and subroutine block with one extra rung could be stored in STOP mode, since the old copy of the subroutine (and main) will be deleted prior to storing the new subroutine, freeing up 2.5K, and since STOP mode stores also defragment the user program memory, this 2.5K will be added to the 2K that was already free, creating a 4.5K chunk of memory for the modified subroutine to be stored in. Note that stores while in RUN mode from the Program Store Screen in IC641 programming software will behave as before. That is, these stores will not be bumpless, but will pause the execution of the PLC while the store takes place. Stores of this type also defragment memory. All existing previous functionality is unchanged. The Bumpless RUN Mode Store feature is executed only by pressing ALT-S while in BLOCK EDIT and RUN Mode from the program edit screen.

4 4 ALT-S BRMS can be used on Ladder Diagram (LD) and Sequential Function Chart (SFC) programs; however, only LD rungs in pre or post processing of an SFC program may be stored via a BRMS. A new chart topology cannot be stored in RUN mode using ALT-S; a pause-mode store must be used from the utility page, or a STOP mode store. Bumpless RUN mode ALT-S stores tend to fragment user memory. That is, they produce small isolated sections of memory which are not connected to other sections of memory. As a result, it may become impossible to perform the BRMS, even though sufficient total free memory is available. The memory is reorganized and the free areas recollected when a utility page store is performed. PID Function Block Enhancement The PID function block has been enhanced since release 6.50 to make the anti-reset-windup mechanism configurable. Prior to release 6.50, all IC693 PLC CPUs back calculate the reset term whenever the output is clamped. In release 6.50, 6.60 and release 6.61 this is the default mechanism. Alternately, you can now choose to simply hold the reset term at its pre-clamp value. The advantage of the new mechanism is to reduce overshoot caused by the reset term as a result of a step change to the SP Example of PID Function Block Enhancement A process is in steady state with PV=58 degrees. A batch is turned on and SP is jumped to 200 degrees. The output clamps high and, with the default anti-reset back calculation, the reset term is driven low to prevent the output from exceeding the clamp. When the PV comes up near the SP, the reset term is large and negative because of the back-calculation. This term must be integrated out, which takes time, so the process overshoots. The new method, if configured, would simply hold the original pre-clamp reset term, presumably small, so it does not take any time to integrate it out, thereby reducing overshoot. Table 1. PID Function Block - Configuration Word PID Config Description ÁÁÁÁÁÁ Word ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ all others reserved - should be 0 bit 4 anti reset wind-up action 0 = DEFAULT back calculate result 1 = pre-clamp reset hold ÁÁÁÁÁÁ bit 3 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ deadband action 0 = deadband action not selected 1 = if error is within deadband then error = 0 else error = (error deadband) bit 2 derivative action 0 = apply differential to error term 1 = apply differential to PV ÁÁÁÁÁÁ bit 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ output polarity select 0 = do not invert CV 1 = invert CV ÁÁÁÁÁÁ bit 0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ error term select 0 = error term is SP PV 1 = error term is PV SP

5 5 Problems Resolved by This Release Write Datagram 1. A write datagram through the backplane, or Port 1 or Port 2 on the CPU 351 previously only supported one text buffer for a maximum of 62 points on a single backplane datagram. Multiple text buffers are now supported, allowing a maximum of 255 points on a single datagram. Zeroing Input Data of a Failed Module 2. When an input module (or a GBC/NBC or other module with inputs) fails with the PLC in RUN mode, the inputs are set to zero; however, previously if this occurred while the PLC was in STOP mode, the inputs would not have been zeroed. Now, if an input module fails, its inputs will be set to zero on each I/O scan, so that even if an input module fails when the PLC is in STOP mode, its inputs will be set to zero. Storing Folder to EEPROM 3. In release 6.51, storing a program to EEPROM could fail in models with EEPROM (but not flash based models). This was corrected in release Restrictions and Open Problems Bumpless Run Mode Store Over Ethernet 1. Due to an early timout on the Ethernet Interface module, attempting to do a Bumpless Run Mode Store (ALT-S) over ethernet of a block greater than 14K bytes in size may result in a loss of communications and cause the store to fail. Setting the programmer window to COMPLETE mode will avoid this problem.