OSPREY Instruction Manual

Transcription

1 Release OSPREY_IM_V1.0_ doc 27/07/12 1 of 31 Project designation OSPREY Scientific CMOS Camera Document title Instructions and manual of use This document is the property of Raptor Photonics and must not be copied, shown or in any way be communicated to persons other than those requiring the information for the execution of their duty.

2 Release OSPREY_IM_V1.0_ doc 27/07/12 2 of 31 DOCUMENT VALIDATION Name Title Date Prepared Michael Starr Raptor Photonics 2 nd May 2012 Reviewed Reviewed Reviewed Reviewed Reviewed Approved Authorized DOCUMENT CHANGE RECORD Issue Change order Date Pages affected Comment V1.0 27/07/12 Release

3 Release OSPREY_IM_V1.0_ doc 27/07/12 3 of 31 TABLE OF CONTENTS 1 SCOPE DESIGN OVERVIEW Mechanical Profile Physical Interfaces Camera link connectors (3M, Part no FR) Power (HiRose, Part no. HR10-7R-4P) Trigger In (50ohm SMA) Trigger out (50ohm SMA) Digital Video out CAMERA CONTROL DETAILS Micro reset System state FPGA control register Frame rate Exposure Trigger Modes Idle mode Internal Trigger External Trigger Snapshot trigger Trigger Abort ROI Binning Binning and ROI Unit Serial number Manufacturers Data ADC calibration data (Sensor temp) DAC calibration data SERIAL COMMUNICATION (CAMERALINK INTERFACE) Overview ETX/ERROR codes Set Commands Query Commands Serial Command Examples Set System status(enable Command Ack and Check sum mode) Get System Status Get Micro version Get FPGA version Reset camera Read Sensor PCB temperature Serial Command Error Examples Missing or wrong checksum... 27

4 Release OSPREY_IM_V1.0_ doc 27/07/12 4 of Partial host command with missing data/etx/checksum Corrupt/Unknown host command APPENDIX A - FPGA FIRMWARE UPLOAD Figure 1: Camera module (Photograph)... 5 Figure 2: SolidWorks model - camera assembley... 6 Figure 3: Mechanical profile drawing SolidWorks model... 7 Figure 4: 26 pin 3M MDR Connector... 8 Figure 5: Digital Video Timing Figure 6: External Trigger timing Figure 7: ROI size and offset... 16

5 Release OSPREY_IM_V1.0_ doc 27/07/12 5 of 31 1 SCOPE This document provides detailed instructions for the operation of the OSPREY Scientific CMOS camera. Details of the camera electrical interfaces and communication protocols are also provided. A photograph of the complete Camera module is shown below. Figure 1: Camera module (Photograph)

6 Release OSPREY_IM_V1.0_ doc 27/07/12 6 of 31 2 DESIGN OVERVIEW 2.1 Mechanical Profile Figure 2: SolidWorks model - camera assembley

7 Release OSPREY_IM_V1.0_ doc 27/07/12 7 of 31 units are in mm [ inches] Figure 3: Mechanical profile drawing SolidWorks model Feature A B C D E F G Description 12V power connector, 4 pin HiRose, Part no. HR10-7R-4P TTL Trigger input, 50ohm SMA TTL Trigger output, 50ohm SMA Not Used Camera link (Base) SDR, 3M, Part no FR 1/4" Whitworth mounting hole. Optical C-mount

8 Release OSPREY_IM_V1.0_ doc 27/07/12 8 of Physical Interfaces Camera link connectors (3M, Part no FR) The camera uses a camera link standard Shrunk Delta Ribbon ( SDR) 26 way connector. The pinout is shown below. TxOUT0_N TxOUT1_N TxOUT2_N TxCLKOUT_N TxOUT3_N TxOUT0_P TxOUT1_P TxOUT2_P TxCLKOUT_P TxOUT3_P TxOUT0_N TxOUT1_N TxOUT2_N TxCLKOUT_N TxOUT3_N SerTC_P SerTFG_N CC1_N CC2_P CC3_N CC4_P TxOUT0_P TxOUT1_P TxOUT2_P TxCLKOUT_P TxOUT3_P SerTC_N SerTFG_P CC1_P CC2_N CC3_P CC4_N GND CN2 inner_shield1 X0- X1- X2- Xclk- X3- SerTC+ SerTFG- CC1- CC2+ CC3- CC4+ inner_shield2 inner_shield3 X0+ X1+ X2+ Xclk+ X3+ SerTC- SerTFG+ CC1+ CC2- CC3+ CC4- inner_shield4 MOUNTING1 MOUNTING2 SDR26 3M_SDR_MINI_CL Figure 4: 26 pin 3M MDR Connector Power (HiRose, Part no. HR10-7R-4P) For the 12V power input connection a 4 way HiRose connector is used. The part number of this connector is HR10-7R-4P, the corresponding socket connector part number is HR10-7P-4S. The pin out of the connector is detailed in the table below. Pin Number Connection 1,2 12V 3,4 GND Unit input power specification is 12V +/- 10%. with a maximum of 3.2Watts power dissipation with the TEC cooler switched off. Additional inrush current (peak power) is required when the cooler power is switched from low to high. Peak power < 11Watts. The total, maximum steady state, unit power dissipation is 8.2Watts

9 Release OSPREY_IM_V1.0_ doc 27/07/12 9 of Trigger In (50ohm SMA) External synchronisation of the start of integration signal may be achieved using the Trigger IN connector. Input impedance = 510ohms, 200pF input capacitance. Input logic levels are; - Logic HIGH >2.31V - Logic Low <0.99V Min. pulse width = 100ns Trigger out (50ohm SMA) For all modes of the camera the Trigger output will represent the integration period of the sensor. The trigger output signal will be a TTL output pulse. The signal will remain low (0V) and then be driven high during the integration period. The source impedance will be equal to 50ohms.

10 Release OSPREY_IM_V1.0_ doc 27/07/12 10 of Digital Video out The OSPREY camera produces mono, digital video output. A pixel clock of 160MHz is used with 12bit data and 2 tap output, each tap is 80MHz i.e. Base camera link. Max. frame rate = 37.5fps for full frame read out. Logic levels are as per camera link standard. The OSPREY has 2048*2048 active pixels. Camera link signals and pixel order as shown below. FV HIGH FV PERIOD FVAL LV HIGH LVAL DVAL LV START 1 LV LOW CH1 data Pixel no CH2 data Figure 5: Digital Video Timing FV PERIOD = Frame Valid period Programmable, ( min = 1/37.5Hz = 2,133,333cnts) (80MHz count) FV HIGH = Frame Valid High = LV START + Number of lines *( LV PERIOD ) + 1

11 Release OSPREY_IM_V1.0_ doc 27/07/12 11 of 31 LV START = Line Valid Start = 4 cnts (80MHz count) Delay from rising edge of Frame Valid to Rising edge of first Line valid LV PERIOD = Line Valid period = (2048/2)+4 = 1028 cnts (80MHz count) LV HIGH = Line Valid High = (Number of columns /2) *1 binning (80MHz count) = (Number of columns ) *2 binning (80MHz count) = (Number of columns ) *4 binning(40mhz count) LV LOW = Line Valid low = LV PERIOD - LV HIGH DV START = Data Valid Start = 1 cnt (80MHz count) Delay from rising edge of Line Valid to Rising edge of first Data Valid DV HIGH = Data Valid High = = (Number of columns /2) --- 1*1 binning (80MHz count) = (Number of columns ) --- 2*2 binning (80MHz count) = (Number of columns ) --- 4*4 binning(40mhz count) Video Latency = not more than1 line period The OSPREY camera has been tested and verified on EPIX PIXCI E4 and E8 camera link frame grabber cards.

12 Release OSPREY_IM_V1.0_ doc 27/07/12 12 of 31 3 CAMERA CONTROL DETAILS 3.1 Micro reset The camera contains an internal microcontroller that is used to process serial commands from the host. The micro controller can be reset by sending a reset command. The micro will take approx. 100msec to reset. The host can poll the camera with a Get system status command. until a valid response is received. 3.2 System state The system state register is used to control the serial communications mode and enable access to the on board EPROM for programming and reading system information. The system state register may also be used to reset the FPGA or hold the FPGA in reset. Note than when reset is released the FPGA will take approx. 500msecs to reboot. Once the FPGA has booted it will take approx. 5secs for the FPGA to load and fully apply the correction map for each pixel. 3.3 FPGA control register The FPGA control register is used to switch the cooling ON/OFF The set point for the TEC cooling is +5degC at the CMOS image sensor. The TEC power is automatically adjusted to try and achieve the set point temperature, with a limit of approx. 5W drive. For low ambient temperatures or with additional heat sinking less than 5Watt may be applied to the TEC to achieve the set point. 3.4 Frame rate When internal trigger and fixed frame rate have been selected the Frame rate registers are used to select the required frame rate. A 32 bit register is used to hold the frame rate value with each count equal to 12.5nsecs (i.e. 1/80MHz). For example; 1fps = 80,000,000cnts 25fps = 3,200,000cnts 30fps = 2,666,666cnts 37.5fps = 2,133,333cnts (MAX) Should the exposure exceed the frame rate period then the exposure will dominate and the frame rate will be reduced accordingly.

13 Release OSPREY_IM_V1.0_ doc 27/07/12 13 of 31 The max frame rate that can be achieved is only dependent on the number of lines in the image. The number of lines is programmable via the ROI. Note that binning and reducing the number of columns in the ROI will not increase the max frame rate For Fixed frame rate mode to calculate the min Frame period in clock cycles. (No. Of lines)*(1028) e.g. for full frame min period = 2048* = 2,133,333 clock cycles at 80Mhz max fps = (1/80MHz)*2,133,333 = 37.5fps 3.5 Exposure The exposure registers are used to determine the exposure of the sensor under all triggering conditions. A 40 bit register is used to hold the exposure value with each count equal to 12.5nsecs (i.e. 1/80MHz). Theoretical max exposure = 3.8 hours. In practice the max exposure will be limited by the dark current of the device and at +5degC this will be approx mins. If the sensor is cooled below +5degC the max. usable exposure may be extended beyond 20mins. Once an exposure has started it cannot be interrupted by another trigger. If for example the camera is in external trigger mode, any trigger pulses applied to the camera during exposure will be ignored. An exposure may be aborted by setting the Abort bit the in trigger mode register. Once an exposure has been aborted the camera will run in the trigger mode selected by the trigger mode register. Actual exposure = Exposure register setting us ( i.e. min exposure = 23.1us) 3.6 Trigger Modes The trigger modes of the camera can be set using the internal trigger mode register. Bits are as outlined below. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Ext R/F Ext Trig en Reserved Reserved Abort Seq. trig Fix. frm en Snap Shot Note that bit3 and bit 0 are self clearing bits Idle mode If the External trigger enable, bit 6, of the Trigger mode register is set = 0 and the Sequence trigger bit 2 is set = 0, then the camera will remain in idle mode i.e. no images will be read from the sensor.

14 Release OSPREY_IM_V1.0_ doc 27/07/12 14 of Internal Trigger If the External trigger enable, bit 6, of the Trigger mode register is set = 0 and the Sequence trigger bit 2 is set = 1, then the camera will use an internal trigger to start the integration and readout of the sensor. The camera will run with continuous integration and readout of the sensor Two modes of internal trigger are available Integrate Then Read (ITR) mode and Fixed frame rate mode. If the Fixed frame rate bit 1 = 0 then ITR mode will be used to capture a continuous sequence of images. The camera will immediately trigger the start of a new integration period when the previous image has been readout. If the Fixed frame rate bit 1 = 1 then the camera will generate an internal trigger signal at a user programmable frame rate External Trigger If the External trigger enable, bit 6, of the Trigger mode register is set = 1 then the camera will use an external trigger to start the integration and readout of the sensor. If the External Rising/Falling, bit 7, is set = 1 then the rising edge of an incoming trigger pulse is used to trigger the start of integration. Else the falling edge is used to trigger the start of integration, both scenarios are depicted in the diagram below. Notes; - It is possible to overlap the readout and integration period for an external trigger signal. - Time from Signal received at camera to start of exposure = 1.125us +/-12.5ns jitter - Min exposure is 23.1us

15 Release OSPREY_IM_V1.0_ doc 27/07/12 15 of 31 EXT. TRIG (+ve) EXT. TRIG (-ve) T pw T fp T s T rd T s Wait for trig Integration Readout Wait for trig Etc. TRIG OUT T int T fp = Frame period T pw = Trigger pulse width, min width > one 40MHz clock period T s = Delay from falling edge of trigger to end of exposure and Start Readout T rd = readout time for 1 progressive frame T int = integration time of sensor Jitter performance = +/- one 40MHz clock period Figure 6: External Trigger timing Notes; - External trigger, triggers the start of integration of the sensor Snapshot trigger If the External trigger enable, bit 6, of the Trigger mode register is set = 0 and the Sequence trigger bit 2 is set = 0, then the camera will remain in idle mode i.e. no images will be read from the sensor. Setting bit 0 will trigger an acquisition from the camera. Note that bit 0 is self clearing Trigger Abort For all modes of the camera the Trigger Abort (bit 3) will abort the current exposure when it is set = 1. Video data will still be sent from the camera. The image sent will be for the duration of the exposure up until the abort command was received. Note that bit 3 of the trigger mode register is self clearing.

16 Release OSPREY_IM_V1.0_ doc 27/07/12 16 of ROI A region of interest within the main active region of 2048*2048 may be defined. The ROI is setup using a bank of registers to control the X offset, the ROI width, the Y offset and the ROI height. These parameters are shown pictorially below. The user must ensure that X offset + ROI width is 2048 and similarly the Y offset + ROI height is Also ROI width and ROI height must be > pixels X W X = ROI X Offset Y Y = ROI Y Offset W = ROI width 2048 lines H ROI H = ROI height Figure 7: ROI size and offset It is possible to send a zero value to the ROI height, this will cause the camera to stop imaging even when a new value of greater than zero is issued. When/If this occurs the ROI height must be set to a value greater than zero and a Trigger Abort command will then need to be issued to reset the acquisition sequence. The camera will then trigger and readout as normal. It is recommended that when the ROI has been changed that the Host re-issues the command to set the appropriate trigger mode with the 'Trigger Abort' (bit 3) set in the trigger mode register. Further triggers/commands may be issued after this command. Note: The Image resolution and number of 12bit taps must be set correctly in the frame grabber format file to ensure correct display of the data.

17 Release OSPREY_IM_V1.0_ doc 27/07/12 17 of Binning In addition to standard 1*1 output, two levels of binning are implemented within the camera. The binning factors available within the camera are 1*1, 2*2, and 4*4. If a binning level of greater than 1*1 is used then the digital video on the camera link output switches to a single tap output. i.e. Binning 1* Tap output both at 80MHz pixel rate, 2048*2048 full frame Binning 2* Tap output at 80MHz, sequential pixel order, 1024*1024 full frame Binning 4* Tap output at 40Mhz, sequential pixel order, 512*512 full frame Note: The Image resolution and number of 12bit taps must be set correctly in the frame grabber format file to ensure correct display of the data. 3.9 Binning and ROI Binning and ROI may be active simultaneously. The ROI is determined on a single pixel basis after which Binning may be applied High Dynamic Range (HDR) Mode When enabled the amount of light required to saturate the ADC (i.e. reach 4095 counts) will be 16 times that of the standard mode of operation. HDR mode may be used for all trigger modes. Minimum exposure for this mode is 420msecs Unit Serial number The camera serial number may be read from the camera s EPROM when the Comms is enabled to the EPROM. Two bytes are used to hold the units serial number. Note that the serial number may also be read as part of the Manufacturers data.

18 Release OSPREY_IM_V1.0_ doc 27/07/12 18 of Manufacturers Data Manufacturers data may be read from the camera s EPROM when the Comms is enabled to the EPROM. 18 bytes are used to hold the manufacturers data that includes the serial number. Starting at address 0x bytes Serial number 3 bytes Build Date (DD/MM/YY) 5 bytes Build code (5 ASCII chars) 2 bytes ADC cal 0degC point 2 bytes ADC cal+4 0degC point 2 bytes DAC cal 0degC point 2 bytes DAC cal+4 0degC point ADC calibration data (Sensor temp) Two ADC values are held in the EPROM, each ADC value is held in 2bytes of the EPROM. The two ADC values represent the CMOS imaging sensor temperature at 0 degrees centigrade and +40 degrees centigrade. The ADC reading will vary linearly with temperature and the two calibration points may be used to define a straight line that can be used to convert the ADC reading to degrees centigrade DAC calibration data DAC calibration data is used as part of the factory setup to determine the set point of the temperature control loop. The camera will be setup at the factory to have a +5degrees centigrade set point for the CMOS imaging sensor.

19 Release OSPREY_IM_V1.0_ doc 27/07/12 19 of 31 4 SERIAL COMMUNICATION (CAMERALINK INTERFACE) 4.1 Overview For version 2.3 of the Micro firmware, the Power on default settings for camera serial port are; baud - 1 start bit - 8 data bits - 1 stop bit UART message format from Host to camera Command Data 1 Data 2... Data n ETX Chk_Sum The first Byte is the command to the Microcontroller in the camera, following bytes contain data required by the command, the ETX byte terminates the command. 0x50 is always used to terminate the command. An additional check sum byte may also be required to be sent by the host if check sum mode is enabled. UART message format from camera to Host Data 1 Data 2... Data n ETX Chk_Sum all or none of the above bytes may be sent in response to commands from the host depending on the commands sent by the host. An optional mode of operation is included in the firmware for command acknowledge. Once enabled the camera will respond to all commands send by the host. After the camera has received and processed the command from the host, a single command acknowledge byte will be sent at the end of transmission (ETX). i.e. should the host command require data to be sent from the camera then the ETX byte will be sent at the end of the requested data. Another optional mode of operation is included in the firmware is for check sum operation, this mode should only be used when the command acknowledge mode is enabled. Once the check sum mode is enabled the camera will only act upon commands that are received with the correct check sum byte sent at the end of the command packet. Note that if the check sum feature is not enabled check sum bytes may still be sent at the end of a command packet, the command will be processed and the check sum will be ignored. The check sum byte should be the result of the Exclusive OR of all bytes in the Host command packet including the ETX byte. When check sum mode is enabled data returned from the camera will include an echo of the checksum from the host command By default the camera will boot up with both command acknowledge and check sum operation disabled. It is intended that the camera be operated from a higher level perspective whereby complete UART messages or groups of UART messages are used to achieve required camera functionality.

20 Release OSPREY_IM_V1.0_ doc 27/07/12 20 of 31 Bits in registers that have not been identified in the documentation should be ignored. Once a command has been received by the camera all subsequent commands from the host will be ignored until the command has been processed. It is recommend that both command acknowledge and check sum operation be enabled at power up. 4.2 ETX/ERROR codes Error codes will be sent as ETX characters by the camera in response to commands that have failed. 0x50 ETX Command acknowledge, command processed successfully. 0x51 ETX_SER_TIMEOUT Partial command packet received, camera timed out waiting for end of packet. Command not processed 0x52 ETX_CK_SUM_ERR Check sum transmitted by host did not match that calculated for the packet. Command not processed 0x53 ETX_I2C_ERR An I2C command has been received from the Host but failed internally in the camera. 0x54 ETX_UNKNOWN_CMD Data was detected on serial line, command not recognized 0x55 ETX_DONE_LOW Host Command to access the camera EPROM successfully received by camera but not processed as EPROM is busy. i.e. FPGA trying to boot.

21 Release OSPREY_IM_V1.0_ doc 27/07/12 21 of Set Commands Set Command Serial Packet Comments Micro RESET 0x55 0x99 0x66 0x11 0x50 0xEB Will trap Micro causing watchdog and reset of firmware. The camera will give no response to this command Set system state 0x4F 0xYY 0x50 YY Bit 6 = 1 to enable check sum mode YY Bit 4 = 1 to enable command ack YY Bit 1 = 0 to Hold FPGA in RESET YY Bit 0 = 1 to enable comms to FPGA EPROM Set FPGA CTRL reg 0x53 0xE0 0x02 0x00 0xYY 0x50 YY Bit 0 = 1 to enable TEC (Default=1) Set Frame rate (Internal trigger, fixed rate only) Set Exposure Set Trig Mode Set Digital video gain Set Binning 0x53 0xE0 0x02 0xDD 0xY1 0x50 0x53 0xE0 0x02 0xDE 0xY2 0x50 0x53 0xE0 0x02 0xDF 0xY3 0x50 0x53 0xE0 0x02 0xE0 0xY4 0x50 0x53 0xE0 0x02 0xED 0xY1 0x50 0x53 0xE0 0x02 0xEE 0xY2 0x50 0x53 0xE0 0x02 0xEF 0xY3 0x50 0x53 0xE0 0x02 0xF0 0xY4 0x50 0x53 0xE0 0x02 0xF1 0xY5 0x50 0x53 0xE0 0x02 0xD4 0xYY 0x50 0x53 0xE0 0x02 0xD5 0xMM 0x50 0x53 0xE0 0x02 0xD6 0xLL 0x50 0x53 0xE0 0x02 0xDB 0xYY 0x50 32 bit value, 4 separate commands, 1 count = 1*80MHz period = 12.5nsecs Y1 = MSB of 4 byte word Y4 = LSB of 4 byte word; Frame rate updated on LSB write 40 bit value, 1count = 1*80MHz period Y1 = MSB of 4 byte word ::: Y5 = LSB of 4 byte word; Frame rate updated on LSB write YY Bit 7 = 1 to enable rising edge, = 0 falling edge Ext trigger (Default=1) YY Bit 6 = 1 to enable External trigger (Default=0) YY Bit 3 = 1 to Abort current exposure, self clearing bit (Default=0) YY Bit 2 = 1 to start continuous seq'., 0 to stop (Default=1) YY Bit 1 = 1 to enable Fixed frame rate, 0 for continuous ITR (Default=0) YY Bit 0 = 1 for snapshot, self clearing bit (Default=0) 16bit value = gain*512 MM bits 7..0 = gain bits LL bits 7..0 = level bits 7..0 Data updated on write to LSBs YY Default = 0x00 YY = 0x00, binning 1*1 YY = 0x11, binning 2*2 YY = 0x22, binning 4*4

22 Release OSPREY_IM_V1.0_ doc 27/07/12 22 of 31 Set ROI X Size Set ROI X offset Set ROI Y Size Set ROI Y offset Set Dynamic Range mode View NUC map 0x53 0xE0 0x02 0xD7 0xMM 0x50 0x53 0xE0 0x02 0xD8 0xLL 0x50 0x53 0xE0 0x02 0xD9 0xMM 0x50 0x53 0xE0 0x02 0xDA 0xLL 0x50 0x53 0xE0 0x02 0xF3 0x81 0x50 0x53 0xE0 0x02 0xF4 0xLL 0x50 0x53 0xE0 0x02 0xF3 0x82 0x50 0x53 0xE0 0x02 0xF4 0xMM 0x50 0x53 0xE0 0x02 0xF3 0x83 0x50 0x53 0xE0 0x02 0xF4 0xLL 0x50 0x53 0xE0 0x02 0xF3 0x84 0x50 0x53 0xE0 0x02 0xF4 0xMM 0x50 0x53 0xE0 0x02 0xF7 0xYY0x50 0x53 0xE0 0x02 0xF7 0xYY 0x50 12bit value MM bits 3..0 = size bits LL bits 7..0 = size bits 7..0 Data updated on write to LSBs 12bit value MM bits 7..0 = offset bits LL bits 7..0 = offset bits 7..0 Data updated on write to LSBs 12bit value MM bits 3..0 = size bits LL bits 7..0 = size bits 7..0 Data updated on write to MSBs or LSBs 12bit value MM bits 3..0 = size bits LL bits 7..0 = size bits 7..0 Data updated on write to MSBs or LSBs YY = 72 Enable High Dynamic Range capture/readout YY = 60 Enable Standard Dynamic Range capture/readout YY = 40 to view NUC offset map. YY = 60 to view live images.

23 Release OSPREY_IM_V1.0_ doc 27/07/12 23 of Query Commands Query Command Send Serial Packet Comments Get system status Get FPGA Status Get Frame rate (Internal trigger, fixed rate only) Get Exposure Get Digital video gain Get PCB temperature Get CMOS silicon temperature 0x49 0x50 0x53 0xE0 0x01 0x00 0x50 0x53 0xE0 0x01 0xDD 0x50 0x53 0xE0 0x01 0xDE 0x50 0x53 0xE0 0x01 0xDF 0x50 0x53 0xE0 0x01 0xE0 0x50 0x53 0xE0 0x01 0xED 0x50 0x53 0xE0 0x01 0xEE 0x50 0x53 0xE0 0x01 0xEF 0x50 0x53 0xE0 0x01 0xF0 0x50 0x53 0xE0 0x01 0xF1 0x50 0x53 0xE0 0x01 0xD5 0x50 0x53 0xE0 0x01 0xD6 0x50 0x53 0xE0 0x02 0x70 0x00 0x50 0x53 0xE0 0x02 0x71 0x00 0x50 0x53 0xE0 0x02 0x6E 0x00 0x50 0x53 0xE0 0x02 0x6F 0x00 0x50 1 byte returned from camera Bit 7 = Reserved Bit 6 = 1 check sum mode enabled Bit 5 = Reserved Bit 4 = 1 to enable command ACK Bit 3..2 = Reserved Bit 2 = 1 if FPGA booted ok Bit 1 = 0 to Hold FPGA in RESET Bit 0 = 1 to enable comms to FPGA EPROM 1 byte returned from camera Bit 0 = 1 if TEC is enabled 32 bit value, internal registers DD to E0 read, register E0 contains the LSBs 1 count = 1*80MHz period = 12.5nsecs 40 bit value, internal registers ED to F1 read, register F1 contains the LSBs 1 count = 1*80MHz period = 12.5nsecs 2 bytes returned from camera 16bit value = gain*512 1 st byte (from D5) => bits nd byte (from D6) => bits bytes returned for 12 bit signed value 1 st byte => bits 3..0 = MSBs nd byte => bits 7..1 = LSBs 7..0 Divide 12 bit value by 16 to get temp. 2 bytes returned, MSB followed by LSB, indicate sensor reading(therm). Conversion formula to deg C see section 3.12 Get Micro version 0x56 0x50 2 bytes returned. 1 st byte Major

24 Release OSPREY_IM_V1.0_ doc 27/07/12 24 of 31 Get FPGA version Get Trig Mode Get Binning Get ROI X Size Get ROI X offset Get ROI Y Size Get ROI Y offset 0x53 0xE0 0x01 0x7E 0x50 0x53 0xE0 0x01 0x7F 0x50 0x53 0xE0 0x01 0xD4 0x50 0x53 0xE0 0x01 0xDB 0x50 0x53 0xE0 0x01 0xD7 0x50 0x53 0xE0 0x01 0xD8 0x50 0x53 0xE0 0x01 0xD9 0x50 0x53 0xE0 0x01 0xDA 0x50 0x53 0xE0 0x02 0xF3 0x01 0x50 0x53 0xE0 0x02 0xF4 0x00 0x50 0x53 0xE0 0x01 0x73 0x50 0x53 0xE0 0x02 0xF3 0x02 0x50 0x53 0xE0 0x02 0xF4 0x00 0x50 0x53 0xE0 0x01 0x73 0x50 0x53 0xE0 0x02 0xF3 0x03 0x50 0x53 0xE0 0x02 0xF4 0x00 0x50 0x53 0xE0 0x01 0x73 0x50 0x53 0xE0 0x02 0xF3 0x04 0x50 0x53 0xE0 0x02 0xF4 0x00 0x50 0x53 0xE0 0x01 0x73 0x50 version 2 nd byte Minor version. Set address 7E (Major Version Byte) Read address 7E, 1 byte Set address 7F (Minor Version Byte) Read address 7F, 1 byte 1 byte returned; Bit 7 = 1 rising edge trig enabled Bit 6 = 1 External trigger enabled Bit 5,4 = reserved Bit 3 = Always read as '0' Bit 2 = 1 continuous seq'., enabled Bit 1 = 1 Fixed frame rate enabled, 0 for continuous ITR Bit 0 = Always read as '0' 1 byte returned; = 0x00, binning 1*1 = 0x11, binning 2*2 = 0x22, binning 4*4 X Size is a 12 bit value 1st BYTE returned (from D7) bits 3..0 = X size bits nd BYTE returned (from D8) bits 7..0 = X size bits 7..0 X Offset is a 12 bit value 1st BYTE returned (from D9) bits 3..0 = X Offset bits nd BYTE returned (from DA) bits 7..0 = X Offset bits 7..0 Y Size is a 12 bit value 1st BYTE returned after 1st 4 commands i.e. from 0x53 0xE0 0x02 0xF3 0x01 0x50 Bits 7..0 = Y size bits ND BYTE returned after 2nd 4 commands i.e. from 0x53 0xE0 0x02 0xF3 0x02 0x50 Bits 3..0 = Y size bits Y offset is a 12 bit value 1st BYTE returned after 1st 4 commands i.e. from 0x53 0xE0 0x02 0xF3 0x3 0x50 Bits 7..0 = Y offset bits ND BYTE returned after 2nd 4 commands i.e. from 0x53 0xE0 0x02 0xF3 0x04 0x50 Bits 3..0 = Y offset bits 11..8

25 Release OSPREY_IM_V1.0_ doc 27/07/12 25 of 31 Get Dynamic Range mode Get Unit Serial Number Get manufacturers Data 0x53 0xE0 0x01 0xF7 0x50 0x53 0xAE 0x05 0x01 0x00 0x00 0x02 0x00 0x50 0x53 0xAF 0x02 0x50 0x53 0xAE 0x05 0x01 0x00 0x00 0x02 0x00 0x50 0x53 0xAF 0x12 0x50 1 byte returned = 72 High Dynamic Range mode enabled = 60 Standard Dynamic Range enabled 2 bytes returned 1 st byte is the LSB 2 nd is the MSB Get 18 bytes from cameras EPROM. For 2 byte values 1st byte returned is the LSB. Starting at address 0x bytes Serial number 3 bytes Build Date (DD/MM/YY) 5 bytes Build code (5 ASCII chars) 2 bytes ADC cal 0degC point 2 bytes ADC cal+4 0degC point 2 bytes DAC cal 0degC point 2 bytes DAC cal+4 0degC point

26 Release OSPREY_IM_V1.0_ doc 27/07/12 26 of Serial Command Examples NOTE: Assume that Command Ack and Check sum mode are enabled unless otherwise stated Set System status(enable Command Ack and Check sum mode) From power up Command TX bytes (to camera) RX d bytes (From camera) Set System status (=0x56) 0x4F 0x56 0x50 0x49 0x50 0x49 (ack + chk_sum) YY Bit 7= 0 - reserved YY Bit 6= 1 to enable check sum mode YY Bit 5= 0 to enable external comms YY Bit 4 = 1 to enable command ack YY Bit 3 = 0 - reserved YY Bit 2 = 1 - reserved YY Bit 1 = 1 FPGA NOT in RESET YY Bit 0 = 0 to disable comms to FPGA EPROM Get System Status Command TX bytes (to camera) RX d bytes (From camera) Get system status 0x49 0x50 0x19 0x56 0x50 0x19 (status = 0x56) Get Micro version Command TX bytes (to camera) RX d bytes (From camera) Get Micro version 0x56 0x50 0x06 0x02 0x03 0x50 0x06 (V2.3) Get FPGA version Command TX bytes (to camera) RX d bytes (From camera) 0x53 0xE0 0x01 0x7E 0x50 0x9C 0x50 0x9C 0xE3 0x01 0x50 0xE3 Get FPGA version 0x53 0xE0 0x01 0x7F 0x50 0x50 0x9C 0x9D 0xE3 0x0B 0x50 0xE3 (v1.11) Reset camera Command TX bytes (to camera) RX d bytes (From camera) Micro Reset 0x55 0x99 0x66 0x11 0x50 0xEB None Set system State to Hold FPGA in RST -- Poll camera with this command every 500msecs until Rx bytes received 0x4F 0x51 0x50 0x4E Set system State to boot the 0x4F 0x52 0x50 0x4D 0x50 0x4D (0x50 0x4E) received when Micro has re-booted successfully

27 Release OSPREY_IM_V1.0_ doc 27/07/12 27 of 31 FPGA Get system status -- Poll the camera with this command every 500ms until bit 2 of the received status indicates that the FPGA has booted ok. 0x49 0x50 0x19 (0x52 0x50 0x19) -- FPGA not booted (0x56 0x50 0x19) -- FPGA booted ok Read Sensor PCB temperature Command TX bytes (to camera) RX d bytes (From camera) 0x53 0xE0 0x02 0x70 0x00 0x50 0x91 0x50 0x91 0xE3 0x01 0x50 0xE3 Get PCB temperature 0x53 0xE0 0x02 0x71 0x00 0x50 0x90 0x50 0x90 0xE3 0x93 0x50 0xE3 (25.18degC) 4.6 Serial Command Error Examples NOTE: Assume that Command Ack and Check sum mode are enabled unless otherwise stated Missing or wrong checksum Command TX bytes (to camera) RX d bytes (From camera) Get system status 0x49 0x50 0x52 0x19 Camera has received a partial command but not received the correct check sum and therefore responds with an error code of 0x52 + sends the check sum byte that it had been expecting. The command is ignored Partial host command with missing data/etx/checksum Command TX bytes (to camera) RX d bytes (From camera) Get system status 0x49 0x51 0x19 Camera has received a partial command but not received expected data or the ETX character. Camera responds with error code 0x51 + sends the check sum byte that it had been expecting. The command is ignored Corrupt/Unknown host command Command TX bytes (to camera) RX d bytes (From camera) Get system status 0x48 0x50 0x19 0x54 0x48 1st byte is corrupt and the camera has received an unknown command. Camera responds with error code 0x54 + sends the check sum byte that it had been expecting. The command is ignored.

28 Release OSPREY_IM_V1.0_ doc 27/07/12 28 of 31 APPENDIX A - FPGA FIRMWARE UPLOAD

29 Release OSPREY_IM_V1.0_ doc 27/07/12 29 of 31 CAMERA EPROM The cameraeprom is divided into15 sectors with address spaces as outlined below. Note that each address points to a 16bit word. /* Sector Structure... Sector Kwords words start end start end FFF FFF FFF FFF FFF FFF FFF FFF FFFF FFF FFFF FFF FFFF FFF FFFF SECTOR 1 - is used for Manufacture specific data i.e. serial number etc. SECTORS 2-15 are used to hold the FPGA configuration information. To program a new FPGA configuration 1. Sectors 2-15 must be erased 2. a new bit file must be uploaded to Sectors 2-15 Note that SECTOR 1 must not be ERASED as this contains detailed data about the camera. SECTOR ERASE The following command is used to erase a sector. SECTOR xx ERASE - 0x53 0xAE 0x05 0x04 0xAA 0xBB 0xCC 0x00 0x50 Where the Hex Number AABBCC represents an address in the sector to be erased. After the SECTOR erase command has been issued a small delay is required for the ERASE to take place. Successful erase can be determined by polling the sector with the following command. 0x53 0xAF 0x01 0x50 If a value of 0xFF is returned the sector erase is complete. Example Sector ERASEs

30 Release OSPREY_IM_V1.0_ doc 27/07/12 30 of 31 SECTOR 2 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x10 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 3 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x20 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 4 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x30 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 5 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x40 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 6 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x50 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 7 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x60 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 8 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x70 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 9 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x80 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 10 ERASE - 0x53 0xAE 0x05 0x04 0x01 0x00 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 11 ERASE - 0x53 0xAE 0x05 0x04 0x01 0x80 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 12 ERASE - 0x53 0xAE 0x05 0x04 0x02 0x00 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 13 ERASE - 0x53 0xAE 0x05 0x04 0x02 0x80 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 14 ERASE - 0x53 0xAE 0x05 0x04 0x03 0x00 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 15 ERASE - 0x53 0xAE 0x05 0x04 0x03 0x80 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR PROGRAMMING Bursts of 32 DATA bytes (sixteen 16bit words) should be sent to the EPROM using a single command, the EPROM will auto increment the addresses. Burst write command 0x53 0xAE 0x25 0x02 0xAA 0xBB 0xCC 0xN1 0xN2 0xN3...0xN32 0x00 0x50 The address of the burst write is given by AABBCC, 32 DATA bytes as read from bit file are sent N1-N32 Address AABBCC should start at the base address of sector 2 i.e. 0x and increment by 16 for every burst command until the end of file. At the end of file the last burst may not require 32bytes due to the file size, if this is the case the last 32 should be padded out to 32. Data in padding ignored.

31 Release OSPREY_IM_V1.0_ doc 27/07/12 31 of 31 Notes : - It is recommended to operate the camera with Command Ack. Waiting for a command Ack will ensure burst writes have taken place before moving to the next burst write. - The bit stream contains a check sum that is used by the FPGA during power up. If data is corrupted during upload the FPGA will not boot. - Verification that FPGA has successfully booted can be done by reading the FPGA version number. Example command list Command Enable FPGA programming Erase EEPROM sector 2 Confirm Sector 2 erase (by reading LSByte) Erase EEPROM sectors 3-15 and confirm erase after each sector. Burst write 32 bytes of bit file Multiple burst writes of 32 bytes of bit file Enable External Comms Get FPGA version Disable External Comms TX bytes (to camera) 0x4F 0x53 0x50 0x53 0xAE 0x05 0x04 0x00 0x10 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 As above with relevant sector address 0x53 0xAE 0x25 0x02 0x00 0x10 0x00 0xN1 0xN2 0xN3...0xN32 0x00 0x50 0x53 0xAE 0x25 0x02 0xAA 0xBB 0xCC 0xN1 0xN2 0xN3...0xN32 0x00 0x50 0x4f 0x02 0x50 0x53 0xE0 0x01 0x7E 0x50 0x53 0xE0 0x01 0x7F 0x50 RX d bytes (from camera) 0x50 0x50 0xFF 0x50 As above 0x50 0x50 0x50 0x50 0x01 0x50 0x50 0x0D 0x50 Comments Enable cmd ack, Enable chk sum, Hold FPGA in reset, enable EPROM comms Poll until 0xFF is returned Poll after each sector is erased until 0xFF is returned 1st burst starting at Sector 2 address. Address 0xAABBCC starts at sector 2 base address and needs to be incremented by 16 for each successive burst until end of file. FPGA will now boot with new firmware, need to delay approx. 500msec Version x4F 0x52 0x50 0x50 Disable External Comms