MDT90P General Description. 3. Applications. 2. Features. 4. Pin Assignment

Transcription

1 . General Description Sleep Mode for power saving This EPROM-Based 4-bit micro-controller uses a fully static CMOS technology process to achieve higher speed and smaller size with the low power consumption and high noise immunity. On chip memory includes.5k words of ROM, and 3 nibbles of static RAM. 2. Features The followings are some of the features on the hardware and software : oscillator start-up time : 2ms 8 bit real time clock/counter(rtcc) with 8-bit programmable prescaler On-chip RC oscillator based Watchdog Timer(WDT) Wake-up from sleep on pin change 3. Applications The application areas of this MDT9P range from appliance motor control and high speed automotive to low power remote Fully CMOS static design 4-bit data bus On chip EPROM size :.5 K words Internal RAM size : 3 nibbles (24 general purpose registers, 6 special registers) 24 single word instructions -bit instructions 2-level stacks Operating voltage : 2.5 V ~ 5.5 V Internal RC oscillator : 4MHz / 8MHz Power-on Reset transmitters/receivers, small instruments, chargers, toy, automobile and PC peripheral etc. 4. Pin Assignment MDT9PST26 / MDT9PST262 PB 6 PB3 VSS 2 5 VDD PB 3 4 PB2/RTCC (SOT-26) P. 29/6 Ver..

2 5. Order Information Device MARK ROM (Words) RAM (Nibbles) I/O Timer (8 Bit) Package MDT9PST SOT-26 MDT9PST SOT-26 Remark PB2 Output is open drain type PB2 Output is CMOS type 6. Block Diagram Stack Two Levels ROM 52 RAM 24 x 4 9 bits 9 bits bits Program Counters Instruction Register Special Register Port B Port PB~PB3 4 bits Oscillator Circuit (INTRC 4M / 8Mhz) Instruction Decoder Control Circuit D~D3 Power on Reset Power Down Reset Working Register ALU Data 4-bit Status Register 8-bit Timer/Counter Prescale WDT/OST Timer PB2(RTCC) P. 2 29/6 Ver..

3 7. Pin Function Description Pin Name I/O Function Description PB I/O Port B, TTL input level.can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change PB I/O Port B, TTL input level. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change PB2/RTCC I/O Real Time Clock/Counter, Schmitt Trigger input levels(clock input to RTCC). TTL input level(data input) MDT9PST26(Output is open drain type). MDT9PST262(Output is CMOS type). PB3 I/O Port B, TTL input level. Output is open drain type.can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change V dd V ss Power supply Ground 8. Memory Map (A) Register Map Address Description BANK RTCCL 2 PCL 3 STATUSL 4 STATUSH 5 IODS 6 PORTB 7 RTCCH 8~F General purpose registers () RTCCL (Real Time Counter/Counter Register) : R RTCCH (Real Time Counter/Counter Register) : R7 P. 3 29/6 Ver..

4 (2) PC (Program Counter) : R2 Write PC --- unchanged JUMP(CALL) --- from instruction word RTWI --- from STACK A8~A4 A3~A Write PC --- from ALU JUMP( CALL) --- from instruction word RTWI --- from STACK (3) STATUSL (Status register) : R3 Bit Symbol Function 2 3 TF C Z PF WDT Timer overflow Flag bit Carry bit Zero bit Power loss Flag bit STATUSH(Status register) : R4 Bit Symbol Function 2 3 SCALL PCWUF Unimplemented Unimplemented : JUMP (initial) : CALL (Change JUMP instruction to CALL instruction. This bit will be clear to zero automatically after CALL was executed) Pin change wake up from sleep P. 4 29/6 Ver..

5 SET CLR MDT9P (4) IODS(I/O data select) : R5 Bit Symbol Function IODS : Output the PORTB register data to PB(initial) Output the PORTB register data to PB(initial) : Output the input clock of RTCC register to PB Output the inverted input clock of RTCC register to PB IODS : Output the PORTB3 register data to PB3(initial) Output the PORTB2 register data to PB2(initial) : Output the input clock of RTCC register to PB3 Output the inverted input clock of RTCC register to PB2 2 RCOS : RTCC PIN can also be the clock input (initial) : RTCC PIN can also be the RC oscillater input 3 UNOV Output non-overlap Set (when IODS or IODS set) PB2 is the invert output of PB3 and PB is the invert output of PB. : Low Action, But they are non-overlap( Will not be low at the same time) output signals. : High Action, But they are non-overlap( Will not be high at the same time) output signals. *nonoverlap time delay(td), See TMRH(TCS) (p7) Fosc/4 TCE prescaler Sync with internal clocks RTCC reg PSC TCS Non-overlap CPIO/3 ENB PB/3 D D q RTCC PIN D Q Q e PORTB/3 data IODS RCOS TTL CPIO/2 ENB PB/2 D D q e PORTB/2 data IODS TTL P. 5 29/6 Ver..

6 (5) PORT B : R6 PB3~PB, I/O Register (6) TMRL (Time Mode Register Low Nibble) (only write) Bit Symbol Function 2 PS2 3 PSC Prescaler Value RTCC rate WDT rate Prescaler assignment bit : RTCC Watchdog Timer : 2 : 4 : 8 : 6 : 32 : 64 : 28 : 256 : : 2 : 4 : 8 : 6 : 32 : 64 : 28 TMRH (Time Mode Register High Nibble) (only write) Bit Symbol Function TCE TCS 2 PBPHB 3 PBWUB RTCC signal Edge : Increment on low-to-high transition on RTCC pin Increment on high-to-low transition on RTCC pin RTCC signal set : Internal instruction cycle clock TD = / Fosc (RTCC rate :, :2, :4) TD = 4 / Fosc (other RTCC rate) Transition on RTCC pin TD =~ us, VDD=5v PortB pull-high : Enable Disable PortB wake-up : Enable Disable (7) CPIO B (Control Port I/O Mode Register) The CPIO register is write-only =, I/O pin in output mode; =, I/O pin in input mode. (8) Configurable options for EPROM (Set by writer) : Oscillator Type INTRC 4Mhz INTRC 8Mhz P. 6 29/6 Ver..

7 Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time Power Edge Detect PED Disable PED Enable Security state Security Disable Security Enable The default security state of EPROM is weak disable. Once the IC was set to enable or disable, it s forbidden to change. (B) Program Memory Address Description -FF Program memory The starting address of power on, pin change or WDT time-out reset. 9. Reset Condition for all Registers Register Address Power-On Reset WDT Reset CPIOB - - TMRH - - TMRL - - RTCCL h xxxx uuuu PC 2h STATUSL 3h xx #uu# STATUSH 4h IODS 5h PORT B 6h xxxx uuuu RTCCH 7h xxxx uuuu Note : u=unchanged, x=unknown, - =unimplemented, read as #=value depends on the condition of the following table P. 7 29/6 Ver..

8 Condition STATUSH: bit 3 STATUSL: bit 3 STATUSL: bit WDT reset (not during SLEEP) WDT reset during SLEEP Wake-up from SLEEP on pin change. Instruction Set : Instruction Code Mnemonic Operands Function Operating Status NOP No operation None CLRWT Clear Watchdog timer WT TF, PF SLEEP Sleep mode WT, stop OSC TF, PF TMODEL Load W to TMRL register W TMRL None TMODEH Load W to TMRH register W TMRH None iiii RTWI Return,place immediate to W Stack PC, I W None rrr CPIO R Control I/O port register W CPIO r None r rrrr STWR R Store W to register W R None t r rrrr LDR R, t Load register R t Z iiii LDWI I Load immediate to W I W None t r rrrr ADDWR R, t Add W and register W + R t C, Z t r rrrr DECRSZ R, t Decrement register, skip if zero R - t None t r rrrr ANDWR R, t AND W and register R W t Z iiii ANDWI i AND W and immediate i W W Z t r rrrr IORWR R, t Inclu. OR W and register R W t Z iiii IORWI i Inclu. OR W and immediate i W W Z t r rrrr XORWR R, t Exclu. OR W and register R W t Z iiii XORWI i Exclu. OR W and immediate i W W Z t r rrrr RRR R, t Rotate right register R(n) R(n-), None R(3), R() x bbr rrrr BCR R, b Bit clear R(b) None bbr rrrr BSR R, b Bit set R(b) None bb rrrr BTSC R, b Bit Test, skip if clear Skip if R(b)= None bbr rrrr BTSS R, b Bit Test, skip if set Skip if R(b)= None n nnnn nnnn JUMP n JUMP(CALL) to address n PC None P. 8 29/6 Ver..

9 Note : W : Working register b : Bit position WT : Watchdog timer t : Target TMRL : Time mode register low nibble : Working register TMRH : TIme mode register high nibble : General register CPIO : Control I/O port register TF : Timer overflow flag R : General register address PF : Power loss flag C : Carry flag PC : Program Counter OSC : Oscillator Z : Zero flag Inclu. : Inclusive Exclu. : Exclusive x : Don t care AND : Logic AND i : Immediate data ( 4 bits ) n : Immediate address. Oscillator start up timer condition : Oscillator Type Porwer-on reset Subsequest resets INTRC 2ms 2ms 2. Electrical Characteristics (A) Operating Voltage & Frequency V dd : 2.5V ~ 5.5 V Frequency : 4 MHz & 8 MHz (B) Input V dd =5. V, Temperature=25 Port Type Min. Max. PB TTL V ss.v PB TTL V ss.v Vil PB2 TTL V ss.v ST V ss.v PB3 TTL V ss.v P. 9 29/6 Ver..

10 Port Type Min. Max. PB TTL 2.V V dd PB TTL 2.V V dd Vih PB2 TTL 2.V V dd ST 3.6V V dd PB3 TTL 2.V V dd *Threshold Voltage : PB~PB3 V th =.2~.7V (TTL trigger) PB2 V il =.4 V, V ih =3.4 V (Schmitt Trigger) (C) Output Voltage V dd =5. V, Temperature=25, the typical value as followings : PB Port I oh =-2. ma I ol =2. ma I oh =-5. ma I ol =5. ma V oh =3.5 V V ol =.7V V oh =4.4 V V ol =.5 V *PB2(MDT9PST26) & PB3 : (D) Leakage V dd =5. V, Temperature=25, the typical value as followings : I il I ih -.μa (Max.) +.μa (Max.) (E) Sleep Temperature=25, the typical value as followings : V dd =2.5 V V dd =3. V V dd =4. V V dd =5. V V dd =5.5V I dd <. μa I dd <. μa I dd <. μa I dd <. μa I dd <. μa P. 29/6 Ver..

11 @WDT-Enable, Temperature=25, the typical value as followings : V dd =2.5 V V dd =3. V V dd =4. V V dd =5. V V dd =5.5 V I dd =. μa I dd =2.5 μa I dd =3.5 μa I dd =6.5 μa I dd =. μa (F) Operating Current Temperature=25, the typical value as followings : (i) WDT-Enable & PED -Enable Voltage/Frequency 4 M 8 M Sleep 2.5 V 235uA 36uA <.ua 3. V 32uA 45uA 2.5uA 4. V 445uA 63uA 3.5uA 5. V 585uA 8uA 6.5uA 5.5 V 675uA 92uA.uA (G) The basic WDT time-out cycle Vdd=5.v,Temperature=25, the typical value as followings : Voltage (V) Basic WDT time-out cycle time (ms) P. 29/6 Ver..