Overview of Today s Lecture: Cost & Price, Performance { 1+ Administrative Matters Finish Lecture1 Cost and Price Add/Drop - See me after class

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1 Overview of Today s Lecture: Cost & Price, Performance EE176-SJSU Computer Architecture and Organization Lecture 2 Administrative Matters Finish Lecture1 Cost and Price Add/Drop - See me after class EE176 Lec2.$&Performance.1 EE176 Lec2.$&Performance.2 Integrated Circuit Costs Administrative Die cost = Wafer cost Dies per Wafer * Die yield Dies per wafer = š * ( Wafer_diam / 2) 2 š * Wafer_diam Test dies - Wafer Area Die Area 2 * Die Area Die Area Homework #1: available on Class Home Page, due 9/7 Be prepared for quiz on: Quiz will contribute to the homework % C language Finite State Machine Die Yield = Wafer yield Defects_per_unit_area * Die_Area α { 1+ } α Die Cost is goes roughly with the cube of the area. EE176 Lec2.$&Performance.3 EE176 Lec2.$&Performance.4

2 Die Yield Real World Examples Raw Dices Per Wafer wafer diameter die area (mm 2 ) /15cm /20cm /25cm die yield 23% 19% 16% 12% 11% 10% typical CMOS process: α =2, wafer yield=90%, defect density=2/cm2, 4 test sites/wafer Chip Metal Line Wafer Defect Area Dies/ Yield Die Cost layers width cost /cm 2 mm 2 wafer 386DX $ % $4 486DX $ % $12 PowerPC $ % $53 HP PA $ % $73 DEC Alpha $ % $149 SuperSPARC $ % $272 Pentium $ % $417 From "Estimating IC Manufacturing Costs, by Linley Gwennap, Microprocessor Report, August 2, 1993, p. 15 Good Dices Per Wafer (Before Testing!) 6 /15cm /20cm /25cm typical cost of an 8, 4 metal layers, 0.5um CMOS wafer: ~$2000 EE176 Lec2.$&Performance.5 EE176 Lec2.$&Performance.6 Other Costs System Cost: Workstation IC cost = Die cost + Testing cost + Packaging cost Final test yield Packaging Cost: depends on pins, heat dissipation Chip Die Package Test & Total cost pins type cost Assembly 386DX $4 132 QFP $1 $4 $9 486DX2 $ PGA $11 $12 $35 PowerPC 601 $ QFP $3 $21 $77 HP PA 7100 $ PGA $35 $16 $124 DEC Alpha $ PGA $30 $23 $202 SuperSPARC $ PGA $20 $34 $326 Pentium $ PGA $19 $37 $473 System Subsystem % of total cost Cabinet Sheet metal, plastic 1% Power supply, fans 2% Cables, nuts, bolts 1% (Subtotal) (4%) Motherboard Processor 6% DRAM (64MB) 36% Video system 14% I/O system 3% Printed Circuit board 1% (Subtotal) (60%) I/O Devices Keyboard, mouse 1% Monitor 22% Hard disk (1 GB) 7% Tape drive (DAT) 6% (Subtotal) (36%) EE176 Lec2.$&Performance.7 EE176 Lec2.$&Performance.8

3 COST v. PRICE Cost Summary list price Q: What % of company income on Research and Development (R&D)? % Average Discount (WS PC) (33 45%) Integrated circuits driving computer industry Die costs goes up with the cube of die area Economics ($$$) is the ultimate driver for performance! avg. selling price % Gross Margin gross margin (33 14%) +33% Direct Costs direct costs direct costs (8 10%) Component Cost component cost component cost component cost (25 31%) Input: chips, displays,... Making it: labor, scrap, returns,... Overhead: R&D, rent, marketing, profits,... Commision: channel profit, volume discounts, EE176 Lec2.$&Performance.9 EE176 Lec2.$&Performance.10 EE176 Lec2.$&Performance.11 Performance Purchasing perspective given a collection of machines, which has the - best performance? - least cost? - best performance / cost? Design perspective faced with design options, which has the - best performance improvement? - least cost? - best performance / cost? Both require basis for comparison metric for evaluation Our goal is to understand cost & performance implications of architectural choices Two notions of performance Plane Boeing 747 BAD/Sud Concodre DC to Paris 6.5 hours 3 hours Time to do the task (Execution Time) execution time, response time, latency Tasks per day, hour, week, sec, ns... (Performance) throughput, bandwidth Response time and throughput often are in opposition EE176 Lec2.$&Performance.12 Speed 610 mph 1350 mph Passengers Which has higher performance? Throughput (pmph) 286, ,200

4 Definitions Example Performance is in units of things-per-second bigger is better If we are primarily concerned with response time performance(x) = 1 execution_time(x) " X is n times faster than Y" means Performance(X) n = Performance(Y) Time of Concorde vs. Boeing 747? Concord is 1350 mph / 610 mph = 2.2 times faster = 6.5 hours / 3 hours Throughput of Concorde vs. Boeing 747? Concord is 178,200 pmph / 286,700 pmph = 0.62 times faster Boeing is 286,700 pmph / 178,200 pmph = 1.6 times faster Boeing is 1.6 times ( 60% )faster in terms of throughput Concord is 2.2 times ( 120% ) faster in terms of flying time We will focus primarily on execution time for a single job EE176 Lec2.$&Performance.13 EE176 Lec2.$&Performance.14 Basis of Evaluation SPEC95 Pros representative portable widely used improvements useful in reality Actual Target Workload Full Application Benchmarks Cons very specific non-portable difficult to run, or measure hard to identify cause less representative Eighteen application benchmarks (with inputs) reflecting a technical computing workload Eight integer go, m88ksim, gcc, compress, li, ijpeg, perl, vortex Ten floating-point intensive tomcatv, swim, su2cor, hydro2d, mgrid, applu, turb3d, apsi, fppp, wave5 Must run with standard compiler flags easy to run, early in design cycle Small Kernel Benchmarks easy to fool eliminate special undocumented incantations that may not even generate working code for real programs identify peak capability and potential bottlenecks Microbenchmarks peak may be a long way from application performance EE176 Lec2.$&Performance.15 EE176 Lec2.$&Performance.16

5 Metrics of performance Aspects of CPU Performance Application Programming Language Answers per month Useful Operations per second CPU CPU time time = Seconds = Instructions x Cycles Cycles x Seconds Program Program Instruction Cycle Cycle Compiler ISA (millions) of Instructions per second MIPS (millions) of (F.P.) operations per second MFLOP/s Program instr. count CPI clock rate Datapath Control Function Units Transistors Wires Pins Megabytes per second Cycles per second (clock rate) Compiler Instr. Set Arch. Organization Each metric has a place and a purpose, and each can be misused Technology EE176 Lec2.$&Performance.17 EE176 Lec2.$&Performance.18 Aspects of CPU Performance CPI CPU CPU time time = Seconds = Instructions x Cycles Cycles x Seconds Program Program Instruction Cycle Cycle instr count CPI clock rate Program X CPI = (CPU Time * Clock Rate) / Instruction Count = Clock Cycles / Instruction Count CPU time = ClockCycleTime * CPI * I i i i = 1 n Average cycles per instruction Compiler X X Instr. Set X X Organization X X Technology X EE176 Lec2.$&Performance.19 n CPI = CPI i * F where F = I i i i i = 1 Instruction Count "instruction frequency" Invest Resources where time is Spent! EE176 Lec2.$&Performance.20

6 Example (RISC processor) Amdahl's Law Base Machine (Reg / Reg) Op Freq Cycles CPI(i) % Time ALU 50% % Load 20% % Store 10% % Branch 20% % 2.2 Typical Mix How much faster would the machine be is a better data cache reduced the average load time to 2 cycles? How does this compare with using branch prediction to shave a cycle off the branch time? What if two ALU instructions could be executed at once? Speedup due to enhancement E: ExTime w/o E Performance w/ E Speedup(E) = = ExTime w/ E Performance w/o E Suppose that enhancement E accelerates a fraction F of the task by a factor S and the remainder of the task is unaffected then, ExTime(with E) Š ((1-F) + F/S) X ExTime(without E) Speedup(with E) Š 1 (1-F) + F/S EE176 Lec2.$&Performance.21 EE176 Lec2.$&Performance.22