128 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

Transcription

1 128 Megabit Serial Flash Memory with 4Kbyte Uniform Sector FEATURES EN25Q128 Single power supply operation - Full voltage range: volt Serial Interface Architecture - SPI Compatible: Mode 0 and Mode M-bit Serial Flash M-bit/16,384 K-byte/65,536 pages bytes per programmable page Standard, Dual or Quad SPI - Standard SPI: CLK, CS#, DI, DO, WP# - Dual SPI: CLK, CS#, DQ 0, DQ 1, WP# - Quad SPI: CLK, CS#, DQ 0, DQ 1, DQ 2, DQ 3 High performance - 104MHz clock rate for Standard SPI - 80MHz clock rate for two data bits - 80MHz clock rate for four data bits Low power consumption - 12 ma typical active current - 1 μa typical power down current Uniform Sector Architecture: sectors of 4-Kbyte blocks of 64-Kbyte - Any sector or block can be erased individually Software and Hardware Write Protection: - Write Protect all or portion of memory via software - Enable/Disable protection with WP# pin High performance program/erase speed - Page program time: 0.8ms typical - Sector erase time: 50ms typical - Block erase time 200ms typical - Chip erase time: 45 seconds typical Lockable 512 byte OTP security sector Minimum 100K endurance cycle Package Options - 8 contact VDFN (5x6mm) - 8 contact VDFN (6x8mm) - 16 pins SOP 300mil body width - 24 balls BGA (6x8mm) - All Pb-free packages are RoHS compliant Industrial temperature Range GENERAL DESCRIPTION The EN25Q128 is a 128 Megabit (16,384K-byte) Serial Flash memory, with advanced write protection mechanisms. The EN25Q128 supports the standard Serial Peripheral Interface (SPI), and a high performance Dual output as well as Dual/Quad I/O using SPI pins: Serial Clock, Chip Select, Serial DQ 0 (DI), DQ 1 (DO), DQ 2 (WP#) and DQ 3 (NC). SPI clock frequencies of up to 80MHz are supported allowing equivalent clock rates of 160MHz (80MHz x 2) for Dual Output and 320MHz (80MHz x 4) for Quad Output when using the Dual/Quad I/O Fast Read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The EN25Q128 is designed to allow either single Sector/Block at a time or full chip erase operation. The EN25Q128 can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector or block. This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

2 Figure.1 CONNECTION DIAGRAMS CS# 1 8 VCC DO (DQ 1 ) 2 7 NC (DQ 3 ) WP# (DQ 2 ) 3 6 CLK VSS 4 5 DI (DQ 0 ) 8 - LEAD VDFN 16 - LEAD SOP This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

3 24 - Ball BGA This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

4 Figure 2. BLOCK DIAGRAM Note: 1. DQ 0 and DQ 1 are used for Dual and Quad instructions. 2. DQ 0 ~ DQ 3 are used for Quad instructions. This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

5 Table 1. Pin Names Symbol Pin Name CLK Serial Clock Input DI (DQ 0 ) Serial Data Input (Data Input Output 0) *1 DO (DQ 1 ) Serial Data Output (Data Input Output 1) *1 CS# Chip Enable WP# (DQ 2 ) Write Protect (Data Input Output 2) *2 NC(DQ 3 ) Not Connect (Data Input Output 3) *2 Vcc Supply Voltage ( V) Vss Ground NC No Connect Note: 1. DQ 0 and DQ 1 are used for Dual and Quad instructions. 2. DQ 0 ~ DQ 3 are used for Quad instructions. SIGNAL DESCRIPTION Serial Data Input, Output and IOs (DI, DO and DQ 0, DQ 1, DQ 2, DQ 3 ) The EN25Q128 support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge CLK. Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Mode") Chip Select (CS#) The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is deselected and the Serial Data Output (DO, or DQ 0, DQ 1, DQ 2 and DQ 3 ) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When CS# is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new instruction will be accepted. Write Protect (WP#) The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register s Block Protect (BP0, BP1, BP2 and BP3) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial Data IO (DQ 2 ) for Quad I/O operation. This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

6 MEMORY ORGANIZATION The memory is organized as: 16,777,216 bytes Uniform Sector Architecture 256 blocks of 64-Kbyte 4,096 sectors of 4-Kbyte 65,536 pages (256 bytes each) EN25Q128 Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector, Block or Chip Erasable but not Page Erasable. This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

7 Table 2. Uniform Block Sector Architecture ( 1/4 ) Block Sector Address range Block Sector Address range 4095 FFF000h FFFFFFh 3839 EFF000h EFFFFFh FF0000h FF0FFFh 3824 EF0000h EF0FFFh 4079 FEF000h FEFFFFh 3823 EEF000h EEFFFFh FE0000h FE0FFFh 3808 EE0000h EE0FFFh 4063 FDF000h FDFFFFh 3807 EDF000h EDFFFFh FD0000h FD0FFFh 3792 ED0000h ED0FFFh F2F000h F2FFFFh 3631 E2F000h E2FFFFh F20000h F20FFFh 3616 E20000h E20FFFh 3871 F1F000h F1FFFFh 3615 E1F000h E1FFFFh F10000h F10FFFh 3600 E10000h E10FFFh 3855 F0F000h F0FFFFh 3599 E0F000h E0FFFFh F00000h F00FFFh 3584 E00000h E00FFFh Block Sector Address range Block Sector Address range 3583 DFF000h DFFFFFh 3327 CFF000h CFFFFFh DF0000h DF0FFFh 3312 CF0000h CF0FFFh 3567 DEF000h DEFFFFh 3311 CEF000h CEFFFFh DE0000h DE0FFFh 3296 CE0000h CE0FFFh 3551 DDF000h DDFFFFh 3295 CDF000h CDFFFFh DD0000h DD0FFFh 3280 CD0000h CD0FFFh D2F000h D2FFFFh 3119 C2F000h C2FFFFh D20000h D20FFFh 3014 C20000h C20FFFh 3359 D1F000h D1FFFFh 3103 C1F000h C1FFFFh D10000h D10FFFh 3088 C10000h C10FFFh 3343 D0F000h D0FFFFh 3087 C0F000h C0FFFFh D00000h D00FFFh 3072 C00000h C00FFFh This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

8 Table 2. Uniform Block Sector Architecture ( 2/4 ) Block Sector Address range Block Sector Address range 3071 BFF000h BFFFFFh 2815 AFF000h AFFFFFh BF0000h BF0FFFh 2800 AF0000h AF0FFFh 3055 BEF000h BEFFFFh 2799 AEF000h AEFFFFh BE0000h BE0FFFh 2784 AE0000h AE0FFFh 3039 BDF000h BDFFFFh 2783 ADF000h ADFFFFh BD0000h BD0FFFh 2768 AD0000h AD0FFFh B2F000h B2FFFFh 2607 A2F000h A2FFFFh B20000h B20FFFh 2592 A20000h A20FFFh 2847 B1F000h B1FFFFh 2591 A1F000h A1FFFFh B10000h B10FFFh 2576 A10000h A10FFFh 2831 B0F000h B0FFFFh 2575 A0F000h A0FFFFh B00000h B00FFFh 2560 A00000h A00FFFh Block Sector Address range Block Sector Address range FF000h 9FFFFFh FF000h 8FFFFFh F0000h 9F0FFFh F0000h 8F0FFFh EF000h 9EFFFFh EF000h 8EFFFFh E0000h 9E0FFFh E0000h 8E0FFFh DF000h 9DFFFFh DF000h 8DFFFFh D0000h 9D0FFFh D0000h 8D0FFFh F000h 92FFFFh F000h 82FFFFh h 920FFFh h 820FFFh F000h 91FFFFh F000h 81FFFFh h 910FFFh h 810FFFh F000h 90FFFFh F000h 80FFFFh h 900FFFh h 800FFFh This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

9 Table 2. Uniform Block Sector Architecture ( 3/4 ) Block Sector Address range Block Sector Address range FF000h 7FFFFFh FF000h 6FFFFFh F0000h 7F0FFFh F0000h 6F0FFFh EF000h 7EFFFFh EF000h 6EFFFFh E0000h 7E0FFFh E0000h 6E0FFFh DF000h 7DFFFFh DF000h 6DFFFFh D0000h 7D0FFFh D0000h 6D0FFFh F000h 72FFFFh F000h 62FFFFh h 720FFFh h 620FFFh F000h 71FFFFh F000h 61FFFFh h 710FFFh h 610FFFh F000h 70FFFFh F000h 60FFFFh h 700FFFh h 600FFFh Block Sector Address range Block Sector Address range FF000h 5FFFFFh FF000h 4FFFFFh F0000h 5F0FFFh F0000h 4F0FFFh EF000h 5EFFFFh EF000h 4EFFFFh E0000h 5E0FFFh E0000h 4E0FFFh DF000h 5DFFFFh DF000h 4DFFFFh D0000h 5D0FFFh D0000h 4D0FFFh F000h 52FFFFh F000h 42FFFFh h 520FFFh h 420FFFh F000h 51FFFFh F000h 41FFFFh h 510FFFh h 410FFFh F000h 50FFFFh F000h 40FFFFh h 500FFFh h 400FFFh This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

10 Table 2. Uniform Block Sector Architecture ( 4/4 ) Block Sector Address range Block Sector Address range FF000h 3FFFFFh 767 2FF000h 2FFFFFh F0000h 3F0FFFh 752 2F0000h 2F0FFFh EF000h 3EFFFFh 751 2EF000h 2EFFFFh E0000h 3E0FFFh 736 2E0000h 2E0FFFh 991 3DF000h 3DFFFFh 735 2DF000h 2DFFFFh D0000h 3D0FFFh 720 2D0000h 2D0FFFh F000h 32FFFFh F000h 22FFFFh h 320FFFh h 220FFFh F000h 31FFFFh F000h 21FFFFh h 310FFFh h 210FFFh F000h 30FFFFh F000h 20FFFFh h 300FFFh h 200FFFh Block Sector Address range Block Sector Address range 511 1FF000h 1FFFFFh 255 0FF000h 0FFFFFh F0000h 1F0FFFh 240 0F0000h 0F0FFFh 495 1EF000h 1EFFFFh 239 0EF000h 0EFFFFh E0000h 1E0FFFh 224 0E0000h 0E0FFFh 479 1DF000h 1DFFFFh 223 0DF000h 0DFFFFh D0000h 1D0FFFh 208 0D0000h 0D0FFFh F000h 12FFFFh 47 02F000h 02FFFFh h 120FFFh h 020FFFh F000h 11FFFFh 31 01F000h 01FFFFh h 110FFFh h 010FFFh F000h 10FFFFh 15 00F000h 00FFFFh h 100FFFh h 004FFFh h 003FFFh h 002FFFh h 001FFFh h 000FFFh This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

11 OPERATING FEATURES Standard SPI Modes The EN25Q128 is accessed through a SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the CLK signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the CLK. Data output on the DO pin is clocked out on the falling edge of CLK. Figure 3. SPI Modes Dual SPI Instruction The EN25Q128 supports Dual SPI operation when using the Dual Output Fast Read and Dual I/O Fast Read (3Bh and BBh) instructions. These instructions allow data to be transferred to or from the Serial Flash memory at two to three times the rate possible with the standard SPI. The Dual Read instructions are ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing) or for application that cache code-segments to RAM for execution. The Dual output feature simply allows the SPI input pin to also serve as an output during this instruction. When using Dual SPI instructions the DI and DO pins become bidirectional I/O pins; DQ 0 and DQ 1. All other operations use the standard SPI interface with single output signal. Quad SPI Instruction The EN25Q128 supports Quad output operation when using the Quad I/O Fast Read (EBh).This instruction allows data to be transferred to or from the Serial Flash memory at four to six times the rate possible with the standard SPI. The Quad Read instruction offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or for application that cache code-segments to RAM for execution. The EN25Q128 also supports full Quad Mode function while using the Enable Quad I/O (EQIO) (38h). When using Quad SPI instruction the DI and DO pins become bidirectional I/O pins; DQ 0 and DQ 1, and the WP# and NC pins become DQ 2 and DQ 3 respectively. This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

12 Figure 4. Quad SPI Modes Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration t PP ). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0) provided that they lie in consecutive addresses on the same page of memory. Sector Erase, Block Erase and Chip Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved a sector at a time, using the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle (of duration t SE t BE or t CE ). The Erase instruction must be preceded by a Write Enable (WREN) instruction. Polling During a Write, Program or Erase Cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE or CE) can be achieved by not waiting for the worst case delay (t W, t PP, t SE, t BE or t CE ). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. Active Power, Stand-by Power and Deep Power-Down Modes When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, and Write Status Register). The device then goes into the Stand-by Power mode. The device consumption drops to I CC1. The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to I CC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down Mode and Read Device ID (RDI) instruction) is executed. All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

13 Status Register The Status Register contain a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. WPDIS bit. The Write Protect disable (WPDIS) bit, non-volatile bit, when it is reset to 0 (factory default) to enable WP# function or is set to 1 to disable WP# function (can be floating during SPI mode.) SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRP, BP3, BP2, BP1, BP0) become read-only bits. In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only be programmed once. Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1, user must clear the protect bits before entering OTP mode and program the OTP code, then execute WRSR command to lock the OTP sector before leaving OTP mode. Write Protection Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern the EN25Q128 provides the following data protection mechanisms: Power-On Reset and an internal timer (t PUW ) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: Power-up Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction completion The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as readonly. This is the Software Protected Mode (SPM). The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction). This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

14 Table 3. Protected Area Sizes Sector Organization Status Register Content Memory Content BP3 BP2 BP1 BP0 Bit Bit Bit Bit Protect Areas Addresses Density(KB) Portion None None None None Block 0 to h-FEFFFFh 16320KB Lower 255/ Block 0 to h-FDFFFFh 16256KB Lower 254/ Block 0 to h-FBFFFFh 16128KB Lower 252/ Block 0 to h-F7FFFFh 15872KB Lower 248/ Block 0 to h-EFFFFFh 15360KB Lower 240/ Block 0 to h-DFFFFFh 14336KB Lower 224/ All h-FFFFFFh 16384KB All None None None None Block 255 to 1 FFFFFFh h 16320KB Upper 255/ Block 255 to 2 FFFFFFh h 16256KB Upper 254/ Block 255 to 4 FFFFFFh h 16128KB Upper 252/ Block 255 to 8 FFFFFFh h 15872KB Upper 248/ Block 255 to 16 FFFFFFh h 15360KB Upper 240/ Block 255 to 32 FFFFFFh h 14336KB Upper 224/ All FFFFFFh h 16384KB All INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output FAST_READ (EBh), Read Status Register (RDSR) or Release from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down (RES ) minimum number of bytes specified has to be given, without which, the command will be ignored. In the case of Page Program, if the number of byte after the command is less than 4 (at least 1 data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any less or more will cause the command to be ignored. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

15 Table 4A. Instruction Set Instruction Name Byte 1 Code Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-bytes EQIO RSTQIO (2) RSTEN RST (1) Write Enable Write Disable / Exit OTP mode Read Status Register Write Status Register 38h FFh 66h 99h 06h 04h 05h (S7-S0) (3) continuous (4) 01h S7-S0 Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 Next byte continuous Sector Erase / OTP erase 20h A23-A16 A15-A8 A7-A0 Block Erase D8h A23-A16 A15-A8 A7-A0 Chip Erase Deep Power-down C7h/ 60h B9h Release from Deep Power-down, and dummy dummy dummy (ID7-ID0) read Device ID ABh Release from Deep Power-down Manufacturer/ 00h (M7-M0) (ID7-ID0) 90h dummy dummy Device ID 01h (ID7-ID0) (M7-M0) Read Identification 9Fh (M7-M0) (ID15-ID8) (ID7-ID0) (7) Enter OTP mode 3Ah Notes: 1. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset. 2. Device accepts eight-clocks command in Standard SPI mode, or two-clocks command in Quad SPI mode 3. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis ( ) indicate data being read from the device on the DO pin 4. The Status Register contents will repeat continuously until CS# terminate the instruction 5. The Device ID will repeat continuously until CS# terminates the instruction 6. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminates the instruction. 00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID 7. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity (5) (6) This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

16 Table 4B. Instruction Set (Read Instruction) Instruction Name Byte 1 Code Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-bytes Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) continuous Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0) Dual Output Fast Read Dual I/O Fast Read BBh A23-A8 (2) Quad I/O Fast Read 3Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, ) (1) EBh Notes: 1. Dual Output data DQ 0 = (D6, D4, D2, D0) DQ 1 = (D7, D5, D3, D1) A23-A0, dummy (4) A7-A0, dummy (2) (dummy, D7-D0 ) (5) (D7-D0, ) (1) (D7-D0, ) (3) (Next Byte) continuous (one byte per 4 clocks, continuous) (one byte per 4 clocks, continuous) (one byte per 2 clocks, continuous) 2. Dual Input Address DQ 0 = A22, A20, A18, A16, A14, A12, A10, A8 ; A6, A4, A2, A0, dummy 6, dummy 4, dummy 2, dummy 0 DQ 1 = A23, A21, A19, A17, A15, A13, A11, A9 ; A7, A5, A3, A1, dummy 7, dummy 5, dummy 3, dummy 1 3. Quad Data DQ 0 = (D4, D0, ) DQ 1 = (D5, D1, ) DQ 2 = (D6, D2,.. ) DQ 3 = (D7, D3,.. ) 4. Quad Input Address DQ 0 = A20, A16, A12, A8, A4, A0, dummy 4, dummy 0 DQ 1 = A21, A17, A13, A9, A5, A1, dummy 5, dummy 1 DQ 2 = A22, A18, A14, A10, A6, A2, dummy 6, dummy 2 DQ 3 = A23, A19, A15, A11, A7, A3, dummy 7, dummy 3 5. Quad I/O Fast Read Data DQ 0 = ( dummy 12, dummy 8, dummy 4, dummy 0, D4, D0 ) DQ 1 = ( dummy 13, dummy 9, dummy 5, dummy 1, D5, D1 ) DQ 2 = ( dummy 14, dummy 10, dummy 6, dummy 2, D6, D2 ) DQ 3 = ( dummy 15, dummy 11, dummy 7, dummy 3, D7, D3 ) This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

17 Table 5. Manufacturer and Device Identification OP Code (M7-M0) (ID15-ID0) (ID7-ID0) ABh 17h 90h 1Ch 17h 9Fh 1Ch 3018h Enable Quad I/O (EQIO) (38h) The Enable Quad I/O (EQIO) instruction will enable the flash device for Quad SPI bus operation. Upon completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a power cycle or Reset Quad I/O instruction instruction, as shown in Figure 5. The device did not support the Read Data Bytes (READ) (03h), Dual Output Fast Read (3Bh) and Dual Input/Output FAST_READ (BBh) modes while the Enable Quad I/O (EQIO) (38h) turns on. Figure 5. Enable Quad I/O Sequence Diagram Reset Quad I/O (RSTQIO) (FFh) The Reset Quad I/O instruction resets the device to 1-bit Standard SPI operation. To execute a Reset Quad I/O operation, the host drives CS# low, sends the Reset Quad I/O command cycle (FFh) then, drives CS# high. This command can t be used in Standard SPI mode. This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

18 Reset-Enable (RSTEN) (66h) and Reset (RST) (99h) The Reset operation is used as a system (software) reset that puts the device in normal operating Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). To reset the EN25Q128 the host drives CS# low, sends the Reset-Enable command (66h), and drives CS# high. Next, the host drives CS# low again, sends the Reset command (99h), and drives CS# high. The Reset operation requires the Reset-Enable command followed by the Reset command. Any command other than the Reset command after the Reset-Enable command will disable the Reset- Enable. A successful command execution will reset the Status register to data = 00h, see Figure 6 for SPI Mode and Figure 6.1 for EQIO Mode. A device reset during an active Program or Erase operation aborts the operation, which can cause the data of the targeted address range to be corrupted or lost. Depending on the prior operation, the reset timing may vary. Recovery from a Write operation requires more software latency time (t SR ) than recovery from other operations. Figure 6. Reset-Enable and Reset Sequence Diagram Figure 6.1 Reset-Enable and Reset Sequence Diagram under EQIO Mode This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

19 Software Reset Flow Initial Command = 66h? No Yes Reset enable Command = 99h? No Yes Reset start WIP = 0? No Embedded Reset Cycle Yes Reset done Note: 1. Reset-Enable (RSTEN) (66h) and Reset (RST) (99h) commands need to match initial SPI or EQIO (Quad) mode. 2. Continue (Enhance) EB mode need to use quad Reset-Enable (RSTEN) (66h) and quad Reset (RST) (99h) commands. 3. If user is not sure it is in SPI or Quad mode, we suggest to execute sequence as follows: Quad Reset-Enable (RSTEN) (66h) -> Quad Reset (RST) (99h) -> SPI Reset-Enable (RSTEN) (66h) -> SPI Reset (RST) (99h) to reset. 4. The reset command could be executed during embedded program and erase process, EQIO mode and Continue EB mode to back to SPI mode. 5. The Status Register Bit will reset to default value after reset done. 6. If user reset device during erase, the embedded reset cycle software reset latency will take about 28us in worst case. This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

20 Write Enable (WREN) (06h) The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction code, and then driving Chip Select (CS#) High. The instruction sequence is shown in Figure 8.1 while using the Enable Quad I/O (EQIO) (38h) command. Figure 7. Write Enable Instruction Sequence Diagram Write Disable (WRDI) (04h) The Write Disable instruction (Figure 8) resets the Write Enable Latch (WEL) bit in the Status Register to a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by driving Chip Select (CS#) low, shifting the instruction code 04h into the DI pin and then driving Chip Select (CS#) high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase (BE) and Chip Erase instructions. The instruction sequence is shown in Figure 8.1 while using the Enable Quad I/O (EQIO) (38h) command. Figure 8. Write Disable Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

21 Figure 8.1 Write Enable/Disable Instruction Sequence under EQIO Mode Read Status Register (RDSR) (05h) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 9. The instruction sequence is shown in Figure 9.1 while using the Enable Quad I/O (EQIO) (38h) command. Figure 9. Read Status Register Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

22 Figure 9.1 Read Status Register Instruction Sequence under EQIO Mode Table 6. Status Register Bit Locations S7 S6 S5 S4 S3 S2 S1 S0 SRP Status Register Protect OTP_LOCK bit (note 1) WPDIS (WP# disable) BP3 (Block Protected bits) BP2 (Block Protected bits) BP1 (Block Protected bits) BP0 (Block Protected bits) WEL (Write Enable Latch) WIP (Write In Progress bit) (Note 3) 1 = status register write disable 1 = OTP sector is protected 1 = WP# disable 0 = WP# enable (note 2) (note 2) (note 2) (note 2) 1 = write enable 0 = not write enable 1 = write operation 0 = not in write operation Non-volatile bit Non-volatile bit Non-volatile bit. Non-volatile bit Non-volatile bit Non-volatile bit volatile bit volatile bit Note 1. In OTP mode, SRP bit is served as OTP_LOCK bit. 2. See the table Protected Area Sizes Sector Organization. The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP3, BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page Program (PP) Sector Erase (SE) and, Block Erase (BE), instructions. The Block Protect This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

23 (BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) instruction is executed if, and only if, all Block Protect (BP3, BP2, BP1, BP0) bits are 0. WPDIS bit. The Write Protect disable (WPDIS) bit, non-volatile bit, when it is reset to 0 (factory default) to enable WP# function or is set to 1 to disable WP# function (can be floating during SPI mode.) SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP, BP3, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only be programmed once. Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1, user must clear the protect bits before enter OTP mode and program the OTP code, then execute WRSR command to lock the OTP sector before leaving OTP mode. Write Status Register (WRSR) (01h) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code and the data byte on Serial Data Input (DI). The instruction sequence is shown in Figure 10. The Write Status Register (WRSR) instruction has no effect on S1 and S0 of the Status Register. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose duration is t W ) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. The instruction sequence is shown in Figure 10.1 while using the Enable Quad I/O (EQIO) (38h) command. NOTE : In the OTP mode, WRSR command will ignore input data and program OTP_LOCK bit to 1. This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

24 Figure 10. Write Status Register Instruction Sequence Diagram Figure 10.1 Write Status Register Instruction Sequence under EQIO Mode Read Data Bytes (READ) (03h) The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a maximum frequency f R, during the falling edge of Serial Clock (CLK). The instruction sequence is shown in Figure 11. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

25 while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 11. Read Data Instruction Sequence Diagram Read Data Bytes at Higher Speed (FAST_READ) (0Bh) The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a maximum frequency F R, during the falling edge of Serial Clock (CLK). The instruction sequence is shown in Figure 12. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. The instruction sequence is shown in Figure 12.1 while using the Enable Quad I/O (EQIO) (38h) command. This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

26 Figure 12. Fast Read Instruction Sequence Diagram Figure 12.1 Fast Read Instruction Sequence under EQIO Mode This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

27 Dual Output Fast Read (3Bh) The Dual Output Fast Read (3Bh) is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins, DQ 0 and DQ 1, instead of just DQ 0. This allows data to be transferred from the EN25Q128 at twice the rate of standard SPI devices. The Dual Output Fast Read instruction is ideal for quickly downloading code from to RAM upon power-up or for applications that cache codesegments to RAM for execution. Similar to the Fast Read instruction, the Dual Output Fast Read instruction can operation at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight dummy clocks after the 24-bit address as shown in Figure 13. The dummy clocks allow the device s internal circuits additional time for setting up the initial address. The input data during the dummy clock is don t care. However, the DI pin should be high-impedance prior to the falling edge of the first data out clock. Figure 13. Dual Output Fast Read Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

28 Dual Input / Output FAST_READ (BBh) The Dual I/O Fast Read (BBh) instruction allows for improved random access while maintaining two IO pins, DQ 0 and DQ 1. It is similar to the Dual Output Fast Read (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. The Dual I/O Fast Read instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of CLK, and data of every two bits (interleave 2 I/O pins) shift out on the falling edge of CLK at a maximum frequency. The first address can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single Dual I/O Fast Read instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing Dual I/O Fast Read instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit, as shown in Figure 14. Figure 14. Dual Input / Output Fast Read Instruction Sequence Diagram Quad Input / Output FAST_READ (EBh) The Quad Input/Output FAST_READ (EBh) instruction is similar to the Dual I/O Fast Read (BBh) instruction except that address and data bits are input and output through four pins. DQ 0, DQ 1, DQ 2 and DQ 3 and four Dummy clocks are required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Input/Output FAST_READ (EBh) instruction enable quad throughput of Serial Flash in read mode. The address is latching on rising edge of CLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of CLK at a maximum frequency F R. The first address can be any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single Quad Input/Output FAST_READ This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

29 instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing Quad Input/Output FAST_READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing Quad Input/Output FAST_READ (EBh) instruction is: CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24-bit address interleave on DQ 3, DQ 2, DQ 1 and DQ 0 -> 6 dummy clocks -> data out interleave on DQ 3, DQ 2, DQ 1 and DQ 0 -> to end Quad Input/Output FAST_READ (EBh) operation can use CS# to high at any time during data out, as shown in Figure 15. The instruction sequence is shown in Figure 15.1 while using the Enable Quad I/O (EQIO) (38h) command. Figure 15. Quad Input / Output Fast Read Instruction Sequence Diagram Figure Quad Input / Output Fast Read Instruction Sequence under EQIO Mode This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

30 Another sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24- bit address interleave on DQ 3, DQ 2, DQ 1 and DQ 0 -> performance enhance toggling bit P[7:0] -> 4 dummy clocks -> data out interleave on DQ 3, DQ 2, DQ 1 and DQ 0 till CS# goes high -> CS# goes low (reduce Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit random access address, as shown in Figure 16. In the performance enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah, F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh) instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. And afterwards CS# is raised, the system then will escape from performance enhance mode and return to normal operation. While Program/ Erase/ Write Status Register is in progress, Quad Input/Output FAST_READ (EBh) instruction is rejected without impact on the Program/ Erase/ Write Status Register current cycle. The instruction sequence is shown in Figure 16.1 while using the Enable Quad I/O (EQIO) (38h) command. This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

31 Figure 16. Quad Input/Output Fast Read Enhance Performance Mode Sequence Diagram This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

32 Figure 16.1 Quad Input/Output Fast Read Enhance Performance Mode Sequence under EQIO Mode This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

33 Page Program (PP) (02h) The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (DI). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is t PP ) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP3, BP2, BP1, BP0) bits (see Table 3) is not executed. The instruction sequence is shown in Figure 17.1 while using the Enable Quad I/O (EQIO) (38h) command. Figure 17. Page Program Instruction Sequence Diagram This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,

34 Figure 17.1 Program Instruction Sequence under EQIO Mode Sector Erase (SE) (20h) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Sector (see Table 2) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 18. Chip Select (CS#) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose duration is t SE ) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a sector which is protected by the Block Protect (BP3, BP2, BP1, BP0) bits (see Table 3) is not executed. The instruction sequence is shown in Figure 19.1 while using the Enable Quad I/O (EQIO) (38h) command. This Data Sheet may be revised by subsequent versions Eon Silicon Solution, Inc.,