The Design Complexity of Program Undo Support in a General Purpose Processor. Radu Teodorescu and Josep Torrellas

Transcription

1 The Design Complexity of Program Undo Support in a General Purpose Processor Radu Teodorescu and Josep Torrellas University of Illinois at Urbana-Champaign

2 Processor with program undo support Safe Speculative Safe Code Speculative execution over large code sections Begin Spec Rollback/re-play of program execution Speculative code Some Code Very low overhead End Spec Speculation exposed to the software 2 Safe Code

3 Applications of program undo Safety net for speculating over: correctness of aggressive optimizations: thread level speculation, value prediction, speculative synchronization system reliability: software - primitive for software debugging 3

4 How complex is program undo support? Determined the hardware needed Implemented it in a simple processor Prototyped it using FPGA technology Estimated complexity using three metrics: Hardware overhead, development time, VHDL code size 4

5 Implementation of program undo support Save/restore processor state, buffer speculative data, control transitions: RF Safe Speculative CKPT CPU 1. Register checkpointing and restoration 2. Data cache that buffers speculative data Data Cache 3. Instructions enable/disable speculation on-the-fly Memory 5

6 Register checkpointing Beginning of the speculative section RF saved into a Shadow RF PC, state registers are saved End of speculative section Commit: discard checkpoint IDLE CHECKPOINT ROLLBACK RESTORE Rollback: restore RF & PC 6

7 Data cache extensions Holds both speculative and nonspeculative data Safe Speculative Speculative lines will not be evicted to memory Data Cache Cache walk state machine: Memory Commit: merge lines IDLE Rollback: invalidate speculative lines 7 WALK RESTORE

8 Software control Give the compiler control over speculative execution Added control instructions: Begin speculation End speculation (commit or rollback) We use SPARC s special access load LDA [r0] code, r1 8

9 Hardware prototype LEON2 - SPARC V8 compliant processor In-order, single issue, 5-stage pipeline Windowed register file L1 instruction and data caches Synthesizable, open source VHDL code Fully functional, runs Linux embedded 9

10 System deployment Processor Image J T A G C O M PCI I/O Terminal Binaries 10 Control App.

11 Evaluating design complexity Hardware overhead, development time, VHDL code size Major components: register checkpointing speculative cache software control Comparison: write-back cache controller 11

12 Hardware overhead Avg. 4.5% overhead 7000 software control speculative cache register checkpointing write back extensions baseline processor CLBs KB 8KB 16KB 32KB 64KB Data cache size 12

13 Development time Time (man-hours) Testing Implementation 300 Design WB Cache Controller Speculative Cache Register Checkpointing 13 Software Control

14 Lines of code % Lines of VHDL code Software control Speculative cache Register checkpointing Write back extensions Baseline unit % Data Cache Controller Pipeline 14

15 Conclusions Program undo support is reasonably easy to implement Complexity similar to adding write-back support to a write-through cache controller Qualifying factor: Relatively simple processor 15

16 Thank you! Short demo and questions... 16