Scenarios for a ROB system built with SHARC processors. Jos Vermeulen, 7 September 1999 Paper model results updated on 7 October 1999

Transcription

1 Scenarios for a ROB system built with processors Jos Vermeulen, 7 September 1999 Paper model results updated on 7 October

2 Scenario I : 6 ROBIns on normal size VME card Configuration Mbyte/s LVL2 and EB links (Gigabit Ethernet) Interfacing to LVL2 interface via PMC connector of RIO-II board, LVL2 interface in other PMC slot of that board, 1 ROBin card per LVL2 interface Interfacing to EB interface with links via backplane connecting to on PMC on RIO-II board with EB interface in other PMC slot of that board, max. 8 ROBin cards connecting to 1 EB link 2

3 Paper model procedure for computing number of LVL2 and EB interfaces and number of crates 1. Compute minimum number of LVL2 and EB links 2. Group ROBIns and LVL2 and EB interfaces (1 LVL2 or 1 EB interface per group), taking into account specified maximum number of ROBIns per LVL2 and EB interface 3. Fit these groups into crates such that at max. 18 slots are occupied 3

4 Low Luminosity Bandwidth per link (MByte/s) LVL2 --> 80 EB --> 80 # of ROBIns per card 6 Max # of cards per link LVL2 --> 1 EB --> 8 Detector mu-mdt muon-trig e.m. cal hadron cal TRT SCT Pixels Total Number of ROBIns Number of cards with ROBins Minimum number of LVL2 links required Number of LVL2 links after grouping Minimum number of EB links required Number of EB links after grouping # of crates (max. 18 slots used) High Luminosity Bandwidth per link (MByte/s) LVL2 --> 80 EB --> 80 # of ROBIns per card 6 Max # of cards per link LVL2 --> 1 EB --> 8 Detector mu-mdt muon-trig e.m. cal hadron cal TRT SCT Pixels Total Number of ROBIns Number of cards with ROBins Minimum number of LVL2 links required Number of LVL2 links after grouping Minimum number of EB links required Number of EB links after grouping # of crates (max. 18 slots used)

5 Configuration Mbyte/s LVL2 and EB links (Gigabit Ethernet) Interfacing to LVL2 interface with links via backplane connecting to on PMC on RIO-II board with LVL2 interface in other PMC slot of that board, max. 8 ROBin cards connecting to 1 LVL2 link Interfacing to EB interface via PMC connector of RIO-II board, connecting to on PMC on RIO-II board, EB interface in other PMC slot of that board, max. 8 interconnected ROBin cards per EB interface 5

6 4 ROBIns per card for TRT Low Luminosity Bandwidth per link (MByte/s) LVL2 --> 80 EB --> 80 # of ROBIns per card 6 Max # of cards per link LVL2 --> 8 EB --> 8 Detector mu-mdt muon-trig e.m. cal hadron cal TRT SCT Pixels Total Number of ROBIns Number of cards with ROBins Minimum number of LVL2 links required Number of LVL2 links after grouping Minimum number of EB links required Number of EB links after grouping # of crates (max. 18 slots used) High Luminosity Bandwidth per link (MByte/s) LVL2 --> 80 EB --> 80 # of ROBIns per card 6 Max # of cards per link LVL2 --> 8 EB --> 8 Detector mu-mdt muon-trig e.m. cal hadron cal TRT SCT Pixels Total Number of ROBIns Number of cards with ROBins Minimum number of LVL2 links required Number of LVL2 links after grouping Minimum number of EB links required Number of EB links after grouping # of crates (max. 18 slots used)

7 Configuration 3. 4 ROBIns per VME card 15 Mbyte/s LVL2 and EB links (ATM) Interfacing to LVL2 interface via PMC connector of RIO-II board, LVL2 interface in other PMC slot of that board, 1 ROBin card per LVL2 interface Interfacing to EB interface with PVIC bus via backplane connecting to PMC on RIO-II board with EB interface in other PMC slot of that board, max. 8 ROBin cards connecting to 1 EB link 7

8 1 ROBIn per card for TRT Low Luminosity Bandwidth per link (MByte/s) LVL2 --> 15 EB --> 15 # of ROBIns per card 4 Max # of cards per link LVL2 --> 1 EB --> 8 Detector mu-mdt muon-trig e.m. cal hadron cal TRT SCT Pixels Total Number of ROBIns Number of cards with ROBins Minimum number of LVL2 links required Number of LVL2 links after grouping Minimum number of EB links required Number of EB links after grouping # of crates (max. 18 slots used) High Luminosity Bandwidth per link (MByte/s) LVL2 --> 15 EB --> 15 # of ROBIns per card 4 Max # of cards per link LVL2 --> 1 EB --> 8 Detector mu-mdt muon-trig e.m. cal hadron cal TRT SCT Pixels Total Number of ROBIns Number of cards with ROBins Minimum number of LVL2 links required Number of LVL2 links after grouping Minimum number of EB links required Number of EB links after grouping # of crates (max. 18 slots used)

9 Scenario II : S-links for output of event data EB fragment data Farm processors Read-Out Links 128 irobs / crate (8 per 9U VME card, 2 S-links / daughter board) 12 crates Partial fragment building in crate irob Crate (9U VME ROD crate) LVL2 fragment data S-link LDAQ/TRG requests, decisions Most of RoI data passes though farm processor Supervisor S W I T C H (S-link could be used for requests, decisions) 9

10 Input board with 8 ROBIns and 4 output links connecting to backplane 8 ROBIns Backplane Control bus Total output bandwidth : 160 Mbyte/s 10

11 Control S-link output board connecting to Backplane with 16 input links bus Note : this is the slide shown, it contains an error : s have only 6 links, while in the drawing some s have 8 links : the vertical arrows linking s receiving data from the backplane have to be removed. With the structure shown a crate can then support 2 in stead of 4 output boards. See the scenarios document for an alternative structure allowing to have 4 output boards per crate Backplane with links 8 S-links Total throughput : 640 Mbyte/s Control bus links 11

12 irob-crate organisation with S-link outputs Max. 128 input S-links 9 U VME crate with backplane with 64 links for data transfer + additional links for control Structure of backplane with links Max. 16 input boards Max. 4 output boards Backplane bandwidth 2.56 Gbyte/s 1 general purpose CPU card with Linux / LynxOS Max. 32 output S-links Network, used for RoI requests, LVL2 accepts/rejects, control 12

13 S-links for output of event data, LVL2 fragment building in additional modified irob crates (same hardware, probably other FPGA programs) Farm processors irob Crate Modified irob Crate Event data out S-link Fraction of RoI data passes though farm processor S W I T C H LDAQ/TRG Throughput per crate = 2.56 Gbyte/s => 2 crates needed Supervisor requests, decisions 13

14 Paper model results Low Luminosity mu-mdt muon-trig e.m. cal hadron cal TRT SCT Pixels Total RoI fragm. data vol. (MByte/s) EB fragm. data vol. (MByte/s) # of 80 Mbyte/s LVL2-links # of 80 Mbyte/s EB-links High Luminosity mu-mdt muon-trig e.m. cal hadron cal TRT SCT Pixels Total RoI fragm. data vol. (MByte/s) EB fragm. data vol. (MByte/s) # of 80 Mbyte/s LVL2-links # of 80 Mbyte/s EB-links Using maximum bandwidth requirements : mu-mdt muon-trig e.m. cal hadron cal TRT SCT Pixels Total # of ROBins Total number of ROBIn cards Total number of crates Total # of LVL2-links out per crate Total # of EB-links out per crate modified irob crates enough for all LVL2 fragment and for total event building 14