ISSCC 2003 / SESSION 8 / COMMUNICATIONS SIGNAL PROCESSING / PAPER 8.7

Transcription

1 ISSCC 2003 / SESSION 8 / COMMUNICATIONS SIGNAL PROCESSING / PAPER A Programmable Turbo Decoder for Multiple 3G Wireless Standards Myoung-Cheol Shin, In-Cheol Park KAIST, Daejeon, Republic of Korea As turbo codes [1] have extremely impressive performance, the 3G mobile radio systems such as W-CDMA and cdma2000 adopted them for channel coding. Although the previous turbo decoders are developed for a single standard or a fixed data rate, flexible and programmable decoders are required for 3G communications because: 1) global roaming is recommended between different 3G standards, and 2) the frame size may change on a frame basis. Figure shows how the two standards are different. As the recursive systematic convolutional (RSC) code of W-CDMA is actually a subset of cdma2000, a soft-input-soft-output (SISO) RSC decoder compatible with both standards can be implemented without much difficulty. However, the interleavers make the implementation of a multi-standard turbo decoder difficult, as the operations and parameters of their generation rules are distinct and complex. Fortunately, the standards share the general concept of block interleavers that write data in a two-dimensional matrix row by row, permutes them, and read them out column by column. A multi-standard turbo decoder implemented with a configurable hardware SISO decoder and a single-instruction multiple-data (SIMD) processor performing flexible tasks such as interleaving is proposed. An incremental interleaving algorithm and specialized instructions suitable for 3G communications are developed to provide interleaved data at the speed of the hardware SISO and change the interleaver structure in a very short time. The proposed turbo decoder is shown in Fig , which has the simplest time-multiplex architecture containing only one SISO, one interleaver, and one extrinsic log-likelihood ratio (LLR) Λ e memory. All the components are shared for both the first and the second SISO decoding of an iteration. Data are read and written in a sequential order for the first decoding, and in an interleaved order for the second decoding. The buffer memory block in Fig stores the received systematic sequence y s and the parity sequence y p s multiplied by the channel reliability L c = 2 /σ 2, and provides them to the SISO. The SIMD processor plays the role of the interleaver. When it calculates interleaved read addresses, the address queue whose length is the SISO latency saves them to use again as the write addresses. In addition to the interleaving, the processor controls the hardware blocks, interfaces with an external host, processes the trellis termination and a stopping criterion during the SISO decoding that does not need an interleaver. The processor controls the configurable hardware blocks by setting their control registers or by loading micro-programs in their hardware controllers. The architecture of the proposed SISO decoder is similar to the memory architecture presented in [2] with a sliding window size of 32. The SISO produces one decoded data every two cycles, and consists of four groups of add-compare-select-add (ACSA) units and four separated memories shown in Fig Input data are read into one of the Γ memories and used three times for calculating forward metrics, backward metrics, and extrinsic LLR s. To support multiple standards, it employs configurable ACSA units. Figure shows an example of the ACSA units calculating a forward metric Α k (s). The input multiplexers change the coding rate and the transfer function, while the second multiplexer selects the decoding algorithm: Log-MAP or Max-Log-MAP [3]. To keep pace with the hardware SISO, parallel processing is indispensable for interleaved address generation. A SIMD architecture depicted in Fig is suitable for the simple and repetitive address generation and has simpler control and lower power consumption than VLIW or superscalar architectures. The SIMD processor has four pipeline stages, and the bit widths of instructions and data are all 16. It has five processing elements (PEs) since the number of rows of W-CDMA block interleaver is a multiple of five. The first PE, PE 0, plays the role of controlling the other PEs and processing scalar operations. It fetches, decodes, and executes instructions including control and multi-cycle scalar instructions, while the other PEs only execute SIMD instructions. The common register files of five PEs form a five-element vector register file to store the data for parallel operations. PE 0 has an additional scalar register file to store scalar and control data. Note that a SIMD instruction is not executed in all PEs simultaneously, but executed serially so that a data memory port and an I/O port can be shared in a time-multiplexed fashion saving memory access power and providing a simple I/O interface. Three specialized SIMD processor instructions, named store to output port if less than (STOLT), subtract if greater or equal (SUBGE), and LOOP, are introduced to replace common instruction sequences appearing in interleaver programs. Each of them takes only one clock cycle to execute and is equivalent to a sequence of three typical RISC instructions. 3G wireless systems support a variable bit rate which may result in full reconstruction of the interleaver at every 10ms or 20ms frame. Generating the whole interleaved address pattern at once consumes once is time-consuming and requires a large-sized RAM to store the pattern. As a solution the interleaver generation into is split into two parts: preprocessing for interleaving and incremental on-the-fly address generation. When the bit rate changes, only the preprocessing is performed to prepare a relatively small number of seed variables. Whenever the interleaved address sequence is required, the SIMD processor generates it column by column using the seed variables. The splitting method reduces the timing overhead of frame size changes. It also requires only a small memory to save the seed data. Using these instructions reduces the basic block lengths of the onthe-fly generation of W-CDMA, cdma2000, and CCSDS to six, five, and four instructions, respectively. The five PEs can then provide one address per cycle for cdma2000 turbo decoding. A multi-standard interleaver is realized by switching several interleaver programs. Implementation of an entire turbo decoder system supports both W-CDMA and cdma2000 1x RTT turbo codes in a 0.25µm CMOS technology. The characteristics of the chip are summarized in Fig and the micrograph is shown in Fig The maximum data rate is 5.48Mb/s, indicating that the decoder is sufficient for the 2Mb/s 3G standards. Compared to an ideal turbo decoder, the BER performance of the proposed decoder shown in Fig is degraded by less than 0.05dB, mainly due to fixedpoint arithmetic. Simulations for high bit rate interleavers showed that the on-the-fly generation is almost as fast as one address per cycle. In addition, the preprocessing time is shorter than the SISO decoding, which can completely hide the overhead as the preprocessing completes during the first SISO decoding. Acknowledgments This work was supported in part by KOSEF through the MICROS center, MOST and MOCIE through System IC 2010, and MIC through the CHiPS ITRC. The authors thank IDEC for fabrication support. References [1] C. Berrou, A. Glavieux, and P. Thitimajshima, Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes, Proc. ICC 93, pp , [2] G. Masera, G. Piccinini, M.R. Roch, and M Zamboni, VLSI Architectures for Turbo Codes, IEEE Trans. VLSI Systems, vol. 7, pp , Sep [3] P. Robertson, E. Villebrun, and P. Hoeher, A Comparison of Optimal and Sub-Optimal MAP Decoding Algorithms Operating in the Log Domain, Proc. ICC 95, pp , June 1995.

2 ISSCC 2003 / February 11, 2003 / Salon 7 / 11:45 AM D+ D + D D + D Λ Γ Γ Γ Α 8 Figure 8.7.1: Differences between the cdma2000 and W-CDMA turbo codes. Figure 8.7.2: Block diagram of the proposed decoder. Λ Γ Α Α Γ Α Λ Figure 8.7.3: ACSA unit for a forward metric A k (s). Figure 8.7.4: Architecture of the SIMD processor. Figure 8.7.5: Summary of the chip implementation. Figure 8.7.6: Chip micrograph.

3 Figure 8.7.7: BER performances in an AWGN channel. 8

4 D+ D + D D + D Figure 8.7.1: Differences between the cdma2000 and W-CDMA turbo codes.

5 Λ Γ Γ Γ Α Figure 8.7.2: Block diagram of the proposed decoder.

6 Λ Γ Α Α Α Γ Λ Figure 8.7.3: ACSA unit for a forward metric A k (s).

7 Figure 8.7.4: Architecture of the SIMD processor.

8 Figure 8.7.5: Summary of the chip implementation.

9 Figure 8.7.6: Chip micrograph.

10 Figure 8.7.7: BER performances in an AWGN channel.