March Quarterly Reliability Report. Document Number DOC-60021, Revision 1

Transcription

1 March 2014 Quarterly Reliability Report Document Number DOC-60021, Revision 1

2 Table of Contents Peregrine Semiconductor Reliability System 3 Failure Rate Calculation Acceleration Factor 4 Failure in Time Calculation 5 Reliability Results (FITs) 6 Process Technology Classification ULTRACMOS 2 Process (U500E) 7 ULTRACMOS 3.5 Process (U350E) 8 ULTRACMOS 5 Process (U350B) 9 ULTRACMOS 6 Process (U250E) 10 ULTRACMOS 6.5 Process (U250E) 11 ULTRACMOS 8 Process (U250B) 12 Product Family Classification Antenna Switches (ASW) 13 High Performance Switches (HPSW) 14 Digitally Tunable Capacitors (DTC) 15 Digital Step Attenuators (DSA) 16 DC-DC Buck Regulators/Converters (DCDC) 17 Mixers (MXR) 18 Phase Locked-Loop Synthesizers (PLL) 19 Prescalers (PSR) 20 Power Limiters (LMTR) 21 Reliability Data (Periodic Testing - 8 QTRs) 22 High Temperature Operating Life (HTOL) 23 Temperature Cycle (TC) 24 Highly Accelerated Stress Test (HAST) 25 High Temperature Storage (HTS) 26 Document No. DOC Page 2 of 25

3 Peregrine Semiconductor Reliability System The Quarterly Reliability Report is a compilation of reliability stress test results that crosses the entire product & technology family of Peregrine Semiconductor Corporation products. Data is collected on a regular basis through the efforts of product and process qualifications, standard product monitoring and lot acceptance testing. To date, a total of 32,793 devices have been tested in HTOL with a total of 3 billion equivalent device hours. The overall failure rate for the PSC family of products is 0.31 FIT at 55 C and 60% UCL. Peregrine Semiconductor reliability testing standards conform to industry standard qualification procedures as detailed in the JEDEC and/or Military Standard guidelines. In addition, where clear guidelines have not been established yet, Peregrine Semiconductor has developed stringent reliability requirements to ensure consistent high reliability performance. Peregrine Semiconductor makes use of accelerated life testing results, along with thermal acceleration factors in the prediction of failure rates. High Temperature Operating Life (HTOL) stress testing is performed at accelerated voltage and temperature conditions which are based on MIL-STD-883 M and Jedec JESD22 A108 standards. Resulting data collected from HTOL tests is de-rated (accelerated) to a typical operating temperature of 55 C. Failure Rate (ELFR) is derived after 48-hr performance. Peregrine Semiconductor conducts an ongoing product reliability monitoring program to evaluate sample products from high volume, major product families on a quarterly basis. The reliability monitoring process is a continuously improving system within Peregrine Semiconductor as we strive for superior product knowledge and performance. Peregrine Semiconductor performs the majority of reliability testing using an ISO17025 certified test laboratory located in San Jose, California. Regular auditing of the laboratory is performed to ensure compliance to ISO standards. Document No. DOC Page 3 of 25

4 Failure Rate Calculation Acceleration Factor An acceleration factor is a constant, which expresses the enhanced effect of temperature on a device s failure rate used in reliability prediction formulas. The typical purpose is to show the acceleration effect between the failure rates at two different temperatures. The semiconductor industry uses the thermal acceleration factor formula based on Arrhenius equation noted below natural logarithm E a = Activation energy k = Boltzmann s constant T 1 = test temperature in Kelvin T 2 = use temperature in Kelvin where e = base of the Sample Calculation T 1 = 55 o C = o K T 2(125) = 125 o C = o K A F(125) = exp [(0.7 / (8.617 x 10 5 )) x ((1/ /398.15))] = C T 2(150) = 150 o C = o K A F(150) = exp [(0.7 / (8.617 x 10 5 )) x ((1/ /423.15))] = C Document No. DOC Page 4 of 25

5 Failure Rate Calculation (continued) Failure in Time Calculation Mean time to failure (M.T.T.F.) is defined as the average time it takes for a failure to occur. Failure in Time (F.I.T.) is the number of units predicted to fail in a billion (1e 9 ) device hours at a specified temperature. After the life test is completed and accelerated device hour data is calculated, the failure rate is estimated using the Chi-Square approximation (χ 2 ) as follows where χ 2 = chi square function r = number of failures EDH = equivalent device hours (units tested x test hours x AF) Sample Calculation Given Units Tested (Sample Size) = 231 devices Test temperature = 150 C Test duration = 500 hours Failures = 0 EDH = (231 x 500 x 259.2) = 2.99E+7 equivalent device hours χ 60% confidence level and 0 failures = 1.83 FIT (60% confidence level) = [1.83 / (2 x 2.99E+7)] x 1.0E+9 = 30.6 FIT Document No. DOC Page 5 of 25

6 Reliability Results (FITs)

7 ULTRACMOS 2 Process Technology Generation Units Tested 19,122 Product Family 500 nm CMOS Silicon Epi Process (U500E) ASW, HPSW, DSA, DC-DC, MXR, PLL, PSR, Standard Failure Rate Calculations at 55 C and 1.38E E E E+09 Document No. DOC Page 7 of 25

8 ULTRACMOS 3.5 Process Technology Generation Units Tested 6,973 Product Family 350 nm CMOS Silicon Epi Process (U350E) ASW, HPSW, DTC, DSA, PSR Standard Failure Rate Calculations at 55 C and 8.59E E E E Document No. DOC Page 8 of 25

9 ULTRACMOS 5 Process Technology Generation Units Tested 4,385 Product Family 350 nm CMOS Bonded Silicon Process (U350B) ASW, HPSW, DTC, PLL, LMTR Standard Failure Rate Calculations at 55 C and 5.43E E E E Document No. DOC Page 9 of 25

10 ULTRACMOS 6 Process Technology Generation Units Tested 1,032 Product Family 250 nm CMOS Silicon Epi Process (U250E) ASW Standard Failure Rate Calculations at 55 C and 8.35E E E E Document No. DOC Page 10 of 25

11 ULTRACMOS 6.5 Process Technology Generation Units Tested 305 Product Family 250 nm CMOS Silicon Epi Process (U250E) ASW Standard Failure Rate Calculations at 55 C and 3.79E E E E Document No. DOC Page 11 of 25

12 ULTRACMOS 8 Process Technology Generation Units Tested 886 Product Family 250 nm CMOS Bonded Silicon Process (U250B) ASW, LMTR Standard Failure Rate Calculations at 55 C and 1.10E E E E Document No. DOC Page 12 of 25

13 ANTENNA SWITCHES (ASW) Description Products in Family Multi-pole & multi-throw high power handling antenna switch products for Mobile Wireless RF and Test Equipment /ATE applications. PE4211x, PE421230, PE421240, PE4255x, PE426x, PE4261x, PE42614x, PE42615x, PE42616x, PE42617x, PE4263x, PE42641, PE4266x, PE4267x, PE4268x, PE42682x, PE42684x, PE42685x, PE4269x, PE42695x, PE42688x, PE421510, PE421550, PE42162x, PE42128x, PE42129x, PE42159x, PE636030, PE Process Technology UltraCMOS 2, UltraCMOS 3.5, UltraCMOS 5, UltraCMOS 6, UltraCMOS 6.5, UltraCMOS 8 Units Tested 6,918 Standard Failure Rate Calculations at 55 C and 8.26E E E E+08 Document No. DOC Page 13 of 25

14 HIGH PERFORMANCE SWITCHES (HPSW) Description Products in Family High performance switch products for wireless RF, broadband and high reliability space switch applications. PE33241, PE4210, PE4220, PE423x, PE424x, PE4242x, PE425x, PE42520, PE4254x, PE427x, PE42721, PE42742, PE42750, PE428x, PE42820, PE84140, PE84244, PE94257, PE9354, PE9542x, PE42359, PE42850, PE Process Technology UltraCMOS 2, UltraCMOS 3.5, UltraCMOS 5 Units Tested 12,414 Standard Failure Rate Calculations at 55 C and 1.34E E E E+09 Document No. DOC Page 14 of 25

15 DIGITALLY TUNABLE CAPACITORS (DTC) Description Products in Family Supports a wide range of tuning applications, from tuning the center frequency of mobile-tv and antennas, to tunable impedance matching and filters. PE6230x, PE621010, PE621020, PE623060, PE623090, PE6490x, PE6410x, PE Process Technology UltraCMOS 3.5, UltraCMOS 5 Units Tested 1,691 Standard Failure Rate Calculations at 55 C and 2.10E E E E Document No. DOC Page 15 of 25

16 DIGITAL STEP ATTENUATORS (DSA) Description 50Ω and 75Ω Digital Step Attenuators for wireless infrastructure, microwave, test equipment and high Products in Family PE430x, PE4320x, PE43404, PE4350x, PE4360x, PE4370x, PE94302, PE4312 Process Technology UltraCMOS 2, UltraCMOS 3.5, UltraCMOS 5 Units Tested 2,014 Standard Failure Rate Calculations at 55 C and 1.68E E E E Document No. DOC Page 16 of 25

17 DC-DC BUCK REGULATORS/CONVERTERS (DCDC) Description These devices are radiation-hardened point-of-load (POL) buck regulators with integrated switches suited for DC-DC converter applications. This monolithic technology replaces multi-chip modules by offering superior performance, smaller size and reduced weight in sensitive Products in Family PE9915x Process Technology UltraCMOS 2 Units Tested 509 Standard Failure Rate Calculations at 55 C and 2.10E E E E Document No. DOC Page 17 of 25

18 MIXERS (MXR) Description Products in Family Process Technology UltraCMOS 2 Units Tested 783 UltraCMOS MOSFET quad array broadband and tuned mixers. PE412x, PE413x, PE414x, PE4150 Standard Failure Rate Calculations at 55 C and 4.92E E E E Document No. DOC Page 18 of 25

19 PHASE LOCKED-LOOP SYNTHESIZERS (PLL) Description Products in Family Integer-N, Fractional-N and Delta Sigma Modulated frequency synthesizers for base station, mobile wireless and high reliability space applications. PE323x, PE3240, PE329x, PE333x, PE334x, PE8334x, PE960x, PE970x, PE972x, PE97240, PE9763, PE33241 Process Technology UltraCMOS 2, UltraCMOS 5 Units Tested 5,629 Standard Failure Rate Calculations at 55 C and 2.77E E E E Document No. DOC Page 19 of 25

20 PRESCALERS (PSR) Description Products in Family UltraCMOS RF Prescalers. PE350x, PE351x, PE8350x, PE8351x, PE930x, PE931x Process Technology UltraCMOS 2, UltraCMOS 5 Units Tested 2,355 Standard Failure Rate Calculations at 55 C and 1.15E E E E Document No. DOC Page 20 of 25

21 POWER LIMITERS (LMTR) Description Products in Family UltraCMOS Power Limiters. PE45450, PE45140 Process Technology UltraCMOS 5, UltraCMOS 8 Units Tested 480 Standard Failure Rate Calculations at 55 C and 5.96E E E E Document No. DOC Page 21 of 25

22 Reliability Data (Periodic Testing for the last 8 Quarters)

23 HIGH TEMPERATURE OPERATING LIFE (HTOL) Reference Standards JESD22-A108, MIL-STD-883 M Test Conditions Test Duration (typical) T A = 125 C (A) or 150 C (B) V bias = max operating voltage 1,000 hrs. at (A) or 500 hrs. at (B) DC HTOL Process Technology Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 UltraCMOS 2 0/1076 0/504 0/1611 0/2755 0/66 0/107 0/352 0/135 UltraCMOS 3.5 0/509 0/240 0/609 0/346 0/283 0/581 0/170 0/2696 UltraCMOS 5 0/460 0/768 0/240 0/255 0/203 0/598-0/955 UltraCMOS 6 n/a n/a n/a 0/401 0/360 0/80 0/77 0/114 UltraCMOS 6.5 n/a n/a n/a n/a n/a n/a 0/107 0/243 UltraCMOS 8 n/a n/a n/a n/a n/a 0/646-0/240 UltraCMOS /90 - RF HTOL Process Technology Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 UltraCMOS UltraCMOS 3.5 0/32-0/ / UltraCMOS 5 0/46 0/61-0/16 0/16 0/48-0/61 UltraCMOS 6 n/a n/a n/a n/a /32 UltraCMOS 6.5 n/a n/a n/a n/a n/a n/a n/a 0/32 UltraCMOS 8 n/a n/a n/a n/a n/a n/a - - UltraCMOS /28 - DC HTOL Product Family Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 ASW 0/460 0/537 0/103 0/567-0/936 0/274 0/833 DCDC 0/188 0/22 0/111-0/22 0/ DSA - - 0/39-0/96 0/400 0/45 0/6 DTC 0/269-0/506 0/180-0/ HPSW 0/470 0/549 0/240 0/2994 0/728 0/181 0/192 0/3020 MXR PLL 0/614 0/404 0/776 0/16 0/66 0/234 0/45 0/44 PSR 0/44-0/ /240 - LMTR /480 RF HTOL Product Family Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 ASW 0/46 0/61 0/32 0/64-0/125 0/59 0/125 DSA / DTC 0/32-0/ HPSW /16-0/ Note n/a - Reliability data not available. Technology or product family not yet qualified at the specified period. dash (-) - Test not performed at the specified period. RF HTOL may not apply to some products. Document No. DOC Page 23 of 25

24 TEMPERATURE CYCLE (TC) Reference Standards Test Conditions Test Duration (typical) JESD22-A C to +125 C (B) -65 C to +150 C (C) 1,000 cyc. at (B) or 500 cyc. at (C) TC Package Family Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 8L 1.5x1.5 UDFN 0/ L 2x2 FCETSLP L 2x2 QFN n/a n/a 0/ L 2x2 QFN 0/299 0/ /300 12L 3x3 QFN - 0/ /360 16L 3x3 QFN n/a n/a n/a n/a 0/150 0/180 0/120 0/460 6L SC70 0/ /240-0/57-0/55 20L 4x4 QFN /135-0/180-0/179 24L 4x4 QFN /55 32L 5x5 QFN n/a n/a / L 4x4 QFN FCOLAM n/a - 0/ L 5x5 QFN FCOLAM n/a n/a n/a n/a n/a n/a - 0/301 8L TSSOP /283-32L 5x5 QFN n/a n/a n/a n/a - 0/ L CQFP / Note n/a - Reliability data not available. Package (family) not yet qualified at the specified period. dash (-) - Test not performed at the specified period. * Plastic encapsulated packages had undergone MSL Preconditioning prior to test. Document No. DOC Page 24 of 25

25 HIGHLY ACCELERATED STRESS TEST (HAST) Reference Standards Test Conditions Test Duration (typical) JESD22-A C, 85% RH, 2.27 atm. (A) 110 C, 85% RH, 1.20 atm. (B) 96 hrs. at (A) or 264 hrs. at (B) HAST Package Family Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 8L 1.5x1.5 UDFN 0/ L 2x2 FCETSLP L 2x2 QFN n/a n/a 0/ L 2x2 QFN 0/135 0/ /599 12L 3x3 QFN - 0/ /348 16L 3x3 QFN n/a n/a n/a n/a 0/180 0/150 0/110 0/645 6L SC70 0/ /238-0/58-0/55 20L 4x4 QFN - 0/ /178-0/179 24L 4x4 QFN /55 32L 5x5 QFN n/a n/a / L 4x4 QFN FCOLAM n/a n/a 0/ L 5x5 QFN FCOLAM n/a n/a n/a n/a n/a n/a - 0/180 8L TSSOP /285-32L 5x5 QFN n/a n/a n/a n/a n/a n/a n/a n/a 44L CQFP Note n/a - Reliability data not available. Package (family) not yet qualified at the specified period. dash (-) - Test not performed at the specified period. HAST may not apply to hermetic packages. * Plastic encapsulated packages had undergone MSL Preconditioning prior to test. Document No. DOC Page 25 of 25

26 HIGH TEMPERATURE STORAGE (HTS) Reference Standards JESD22-A103 Test Conditions Ta = 150 C Test Duration (typical) 1,000 hrs. HTS Package Family Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 8L 1.5x1.5 UDFN 0/ L 2x2 FCETSLP L 2x2 QFN n/a n/a 0/ L 2x2 QFN 0/300 0/ /298 12L 3x3 QFN - 0/ /269 16L 3x3 QFN n/a n/a n/a n/a - 0/300-0/555 6L SC70 0/ / L 4x4 QFN /77-0/299-0/300 20L 4x4 QFN /77-0/299-0/300 32L 5x5 QFN n/a n/a / L 4x4 QFN FCOLAM n/a - 0/ L 5x5 QFN FCOLAM n/a n/a n/a n/a n/a n/a - 0/297 8L TSSOP /298-32L 5x5 QFN n/a n/a n/a n/a - 0/ L CQFP / Note n/a - Reliability data not available. Package (family) not yet qualified at the specified period. dash (-) - Test not performed at the specified period. Document No. DOC Page 26 of 25