DDR SDRAM Controller. MegaCore Function User Guide. 101 Innovation Drive San Jose, CA (408)

Transcription

1 DDR SDRAM Controller MegaCore Function User Guide 101 Innovation Drive San Jose, CA (408) Core Version: Document Version: rev 1 Document Date: March 2003

2 DDR SDRAM Controller MegaCore Function User Guide Copyright 2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. All rights reserved. ii Altera Corporation UG-DDRSDRAM-1.3

3 About this User Guide This user guide provides comprehensive information about the Altera DDR SDRAM Controller MegaCore function. Table 1 shows the user guide revision history. f Go to the following sources for more information: See Features on page 10 for a complete list of the core features, including new features in this release Refer to the readme file for late-breaking information and known issues that are not available in this user guide Table 1. User Guide Revision History Date March 2003 February 2003 June 2002 March 2002 Description Column address strobe (CAS) latency information updated. Cyclone and Stratix GX device information added. Timing analysis information improved and moved to Appendix B. Updated PLL diagrams. Changes to getting started section. First full release. Includes Stratix device support information. Preliminary release. How to Find Information The Adobe Acrobat Find feature allows you to search the contents of a PDF file. Click on the binoculars icon in the top toolbar to open the Find dialog box Bookmarks serve as an additional table of contents Thumbnail icons, which provide miniature previews of each page, provide a link to the pages Numerous links, shown in green text, allow you to jump to related information Altera Corporation iii

4 About this User Guide How to Contact Altera DDR SDRAM Controller MegaCore Function User Guide For the most up-to-date information about Altera products, go to the Altera world-wide web site at For additional information about Altera products, consult the sources shown in Table 2. Table 2. How to Contact Altera Information Type Access USA & Canada All Other Locations Technical support Web site Altera Literature Services Non-technical customer service General product information FTP site ftp.altera.com ftp.altera.com Telephone hotline (800) 800-EPLD (6:00 a.m. to 6:00 p.m. Pacific Time) Note: (1) You can also contact your local Altera sales office or sales representative. (408) (1) (7:30 a.m. to 5:30 p.m. Pacific Time) Fax (408) (408) (1) Electronic mail (1) (1) Telephone hotline (800) SOS-EPLD (408) (7:30 a.m. to 5:30 p.m. Pacific Time) Fax (408) (408) Telephone (408) (408) (1) Web site iv Altera Corporation

5 DDR SDRAM Controller MegaCore Function User Guide About this User Guide Typographic Conventions The DDR SDRAM Controller MegaCore Function User Guide uses the typographic conventions shown in Table 3. Table 3. Conventions Visual Cue Bold Type with Initial Capital Letters bold type Italic Type with Initial Capital Letters Meaning Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: f MAX, \qdesigns directory, d: drive, chiptrip.gdf file. Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design. Italic type Internal timing parameters and variables are shown in italic type. Examples: t PIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file. Initial Capital Letters Subheading Title Courier type Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: Typographic Conventions. Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. 1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention. r The angled arrow indicates you should press the Enter key. f The feet direct you to more information on a particular topic. Altera Corporation v

6 Notes:

7 Contents About this User Guide... iii How to Find Information... iii How to Contact Altera... iv Typographic Conventions... v About this Core...9 Release Information...9 Device Family Support...9 Introduction...10 New in Version Features...10 General Description...10 Performance...12 Getting Started...13 Software Requirements...13 Design Flow...13 Download & Install the Function...15 Obtaining the DDR SDRAM Controller MegaCore Function...15 Installing the DDR SDRAM Controller Files...16 Directory Structure...17 Set Up Licensing...19 Append the License to Your license.dat File...19 Specify the Core s License File in the Quartus II Software...20 DDR SDRAM Controller Walkthrough...21 Create a New Quartus II Project...21 Launch the MegaWizard Plug-In Manager...22 Choose the Parameters...23 Complete the Custom Core...32 Using the Reference Design...34 Set Up the Reference Design...34 Compile the Reference Design...35 Post-route Simulation...36 Configure the PLL...36 Behavioral Simulation...37 Simulate with the ModelSim VHDL Model...37 Simulate with the Visual IP Model...39 Compile & Place-&-Route...40 Cyclone Devices...40 Altera Corporation vii

8 Contents Stratix & APEX II Devices...41 Timing Analysis...42 Perform Post-Route Simulation...42 License for Configuration...43 Specifications...45 Functional Description...45 Signals...45 Control Logic Module...49 Data Path Module...50 Controller Access Operation...54 Write Operation...54 Read Operation...56 Refresh Timing...58 Initialization Timing...59 Miscellaneous SDRAM Settings...60 PLL Configuration...61 APEX II Devices...61 Cyclone & Stratix Devices...62 Core Verification...64 Simulation Testing...65 Hardware Testing...65 Board Design Package...65 Appendix A The Quartus II Constraint Settings...67 APEX II Devices...67 Stratix Devices...70 Appendix B DDR SDRAM Timing Analysis...75 Introduction...75 FPGA-SDRAM Interface...75 Write Data Timing...75 Address & Command Timing...77 Read Data Capture using DQS...78 Resynchronization of Captured Read Data from the DQS to the System Clock Domain...78 Appendix C Board Design Guidelines...87 General Guidelines...87 Decoupling Capacitance...89 viii Altera Corporation

9 Release Information About this Core Table 4 provides information about this release of the DDR SDRAM Controller MegaCore function. 1 Specifications About DII Interface this Core Device Family Support Table 4. DDR SDRAM Controller Release Information Item Description Version Release Date March 2003 Ordering Code IP-SDRAM/DDR Product ID(s) 0055 Vendor ID(s) 6AF7 Every Altera MegaCore function offers a specific level of support to each of the Altera device families. The following list describes the three levels of support: Full The core meets all functional and timing requirements for the device family and may be used in production designs Preliminary The core meets all functional requirements, but may still be undergoing timing analysis for the device family; may be used in production designs. No support The core has no support for device family and cannot be compiled for the device family in the Quartus II software. Altera Corporation 9

10 About this Core DDR SDRAM Controller MegaCore Function User Guide Table 5 shows the level of support offered by the DDR SDRAM Controller MegaCore function to each of the Altera device families. Table 5. Device Family Support Device Family Stratix GX Cyclone Stratix APEX II Other device families Preliminary Preliminary Preliminary Full No support Support Introduction New in Version The Altera DDR SDRAM Controller MegaCore function provides a simplified interface to industry-standard DDR SDRAM memory. Support for column address strobe (CAS) latency of 3.0 clock cycles Features Burst lengths of 2, 4, or 8 data words CAS latency of 2.0, 2.5, or 3.0 clock cycles 16-bit programmable refresh counter for automatic refresh 1, 2, 4, or 8 chip-select signals Support for the NOP, READ, WRITE, AUTO_REFRESH, PRECHARGE, ACTIVATE, and BURST_TERMINATE SDRAM commands Data mask lines supported for partial write operations Bank management architecture, which minimizes latency Access cascading architecture, which maximizes throughput Memory data path widths of 8 to 80 bits Each dqs signal supports 8 dq bits and samples read data Multiple DIMM support OpenCore feature allows designers to instantiate and simulate designs in the Quartus II software prior to purchasing a license Hardware tested at 167 MHz with DDR333 (PC2700) memory devices in Stratix devices Hardware tested at 133 MHz with DDR266 (PC2100) memory devices in APEX II devices General Description The DDR SDRAM Controller handles the complex aspects of using DDR SDRAM initializing the memory devices, managing SDRAM banks, and keeping the devices refreshed at appropriate intervals. The DDR SDRAM Controller translates read and write requests from the local interface into all the necessary SDRAM command signals. 10 Altera Corporation

11 DDR SDRAM Controller MegaCore Function User Guide GettingAbout this Core The DDR SDRAM Controller is optimized for Altera Cyclone, Stratix, Stratix GX, and APEX II devices. The advanced features available in these devices allow you to interface directly to DDR SDRAM devices and to use the data strobe signal (dqs) in the read and write direction. Figure 1 shows a system-level diagram of the DDR SDRAM Controller (see Tables 13 and 14 on page 46 for signal descriptions). 1 About this Core Figure 1. DDR SDRAM Controller System-Level Diagram clk clk_shifted reset_n raddr b_size r_req w_req rw_ack d_req w_valid r_valid DDR SDRAM Controller MegaCore Function a ba cs_n cke ras_n cas_n we_n dm dq dqs DDR SDRAM datain dm_in dataout Altera Corporation 11

12 About this Core Performance DDR SDRAM Controller MegaCore Function User Guide Table 6 shows typical performance results for the DDR SDRAM Controller. Table 6. Typical Performance Device DDR SDRAM System f MAX (MHz) Cyclone (EP1C20F400C6) Pending Device Characteristics Stratix (EP1S25F780C6) Pending Device Characteristics APEX II (EP2A15F672C9) 133 Table 7 shows typical sizes for the DDR SDRAM Controller. Table 7. Typical Sizes Data Width (bits) LEs Cyclone Device Stratix Device APEX II Device , , , ,020 1, ,050 1, ,100 1, Altera Corporation

13 Getting Started Software Requirements Design Flow f This section requires the following software: Quartus II version 2.2 SP1 1 This section assumes you are using a PC with the Windows operating system. However, the core also works with UNIX platforms. If you are using UNIX, you must install the Java Runtime Environment version 1.3. Refer to the core s readme file for more information on UNIX support. The DDR SDRAM Controller has the following design flows: User top-level flow Create a custom variation and instantiate it into your existing functional top-level design. However, follow the guidelines on setting up the PLLs and system timing analysis. 1 If you do not have a functional top-level design, use the following method for evaluating the DDR SDRAM Controller. Do not use a DDR SDRAM Controller instance as a top-level design to compile in the Quartus II software. Dummy top-level flow Create a custom variation and use the wizardgenerated dummy top-level design to compile it in the Quartus II software. The dummy top-level design instantiates your custom variation, PLLs for the appropriate family, and dummy logic that connects the local-side interface signals to pins via registers. This flow allows you to perform area and timing analysis. You can use this flow for any custom variation, but you cannot simulate, because the dummy top-level is non-functional. To simulate your instance, Altera provides a separate example testbench and script. In addition, Altera provides a VHDL reference design for each of the supported families in the \reference_design directory. You can compile each reference design in the Quartus II software, perform post-route simulation, and run in real hardware. The reference designs use read and write command sequences to drive the controller. A script is provided, which allows you to change the exact sequence of these commands. For more information on the reference designs, see Using the Reference Design on page 34 and doc\readme_test_stim.txt. 2 Getting Started Altera Corporation 13

14 Getting Started DDR SDRAM Controller MegaCore Function User Guide Table 8 shows the steps for the three possible design flows of the DDR SDRAM Controller. Table 8. Design Flow Steps User Top-Level Dummy Top-Level Reference Design HDL. VHDL, Verilog, or AHDL. VHDL or Verilog. VHDL only. Quartus II project location. Any directory. Any directory. The reference_design directory structure must be maintained, but can be moved. Perform walkthrough. Yes. Yes. No. Choose parameters. Any combination. Any combination. Fixed. 32-bit memory for Stratix and APEX II devices; 16-bit for Cyclone devices. Configure PLL. Follow PLL configuration section in UG Fixed at 133 MHz (see Note (1)). Fixed at 133 MHz (see Note (1)). Behavioral simulation. Run constraints scripts. Yes, you can simulate using your user top-level in VHDL or Verilog. Altera also provides a VHDL testbench that you can use to simulate your core (see Simulate with the ModelSim VHDL Model on page 37). See Appendix A The Quartus II Constraint Settings on page 67. No; you cannot simulate the dummy logic. However, Altera provides a VHDL testbench that you can use to simulate your core (see Simulate with the ModelSim VHDL Model on page 37). Only supported for one configuration and device for each family. Quartus II compile Yes. Yes. Yes. and place and route. Area estimates. Yes. Yes, but you must subtract the Yes. dummy logic LEs. Timing analysis. See Appendix A The Quartus II Constraint Settings on page 67. Yes. No. Post place-and-route simulation with ModelSim script. No. No; you cannot simulate the dummy logic. Restrictions Ensure that the Quartus II toplevel design entity is the same name as your dummy toplevel. No. Yes. Yes (VHDL only). 14 Altera Corporation

15 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started Note to Table 8: (1) To edit this frequency, see Configure the PLL on page 36. This getting started covers the following topics: 1. Download and install the DDR SDRAM Controller MegaCore function. 2. Set up licensing. 3. DDR SDRAM Controller MegaCore function walkthrough. 4. Simulate your design to confirm the operation of your system. 5. Compile and place-and-route. 6. Timing analysis 7. Post-route simulation. 2 Getting Started 8. License the DDR SDRAM Controller MegaCore function and configure the devices. Download & Install the Function Before you can start using Altera MegaCore functions, you must obtain the MegaCore files and install them on your PC. The following instructions describe this process. Obtaining the DDR SDRAM Controller MegaCore Function If you have Internet access, you can download MegaCore functions from Altera s web site at Follow the instructions below to obtain the DDR SDRAM Controller via the Internet. If you do not have Internet access, you can obtain the DDR SDRAM Controller from your local Altera representative. 1. Point your web browser to 2. Type DDR SDRAM in the Keyword Search box. 3. Click Go. 4. Choose your MegaCore function. 5. Click the Free Evaluation link. 6. Follow the on-line instructions to download the function and save it to your hard disk. Altera Corporation 15

16 Getting Started DDR SDRAM Controller MegaCore Function User Guide Installing the DDR SDRAM Controller Files To install the DDR SDRAM Controller files, perform the following steps: 1. Choose Run (Start menu). 2. Type <path name>\<filename>, where <path name> is the location of the downloaded MegaCore function and <filename> is the file name of the core. Click OK. 3. Follow the on-line instructions to finish installation. 4. After you have finished installing the MegaCore files, you must specify the DDR SDRAM Controller s library directory (<path>\ddr_sdram-<version>\lib) as a user library in the Quartus II software. Search for User Libraries in Quartus II Help for instructions on how to add a library. f For additional installation instructions, refer to the readme file. 16 Altera Corporation

17 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started Directory Structure Figures 2 and 3 show the directory structure for the DDR SDRAM Controller. Figure 2. Directory Structure (Part 1 of 2) MegaCore ddr_sdram-<version> Contains the DDR SDRAM Controller MegaCore function files and documentation. ahdl_for_cyclone Contains modified Quartus II AHDL files for Cyclone devices. constraints Contains a Tcl script that generates an instance-specific Tcl script for each instance of the DDR-SDRAM Controller in a Cyclone device. Examples of how to run the script are included. dat Contains a data file for each Cyclone device combination that is used by the Tcl script to generate the instance-specific Tcl script. 2 Getting Started doc Contains the documentation for the core. lib Contains encrypted lower-level design files and some open-source example files that are used in the design flow. After installing the MegaCore function, you should set a user library in the Quartus II software that points to this directory. This library allows you to access all the necessary MegaCore files. sim_lib Contains the simulation models provided with the core. modelsim Contains the precompiled libraries for the ModelSim simulation tool. vhdl Contains the VHDL precompiled simulation libraries. visualip Contains the PC or UNIX precompiled models for the Visual IP software. Altera Corporation 17

18 Getting Started DDR SDRAM Controller MegaCore Function User Guide Figure 3. Directory Structure (Part 2 of 2) MegaCore ddr_sdram-<version> Contains the DDR SDRAM Controller MegaCore function files and documentation. reference_design Contains the reference design source files. apexii_example Contains an example Quartus II project for APEX II devices containing a 32-bit, 133-MHz DDR SDRAM Controller. cyclone_example Contains an example Quartus II project for Cyclone devices containing a 16-bit, 133-MHz DDR SDRAM Controller. stratix_example Contains an example Quartus II project for Stratix devices containing a 32-bit, 167-MHz DDR SDRAM Controller. test_stimulus Contains the clear text read and write command sequences and a Tcl script to convert the command sequences into ROM contents for the reference designs. user_simulation Contains example ModelSim simulation scripts. project_for_your-instance Contains a Quartus II project that you must run from the the MegaWizard Plug-In, before you run the user_simulation scripts. vhdl Contains the VHDL reference design source files. testbench Contains the testbench directories. vhdl Contains the sample VHDL testbench, which illustrates the functionality of the core. 18 Altera Corporation

19 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started Set Up Licensing You can use the Altera OpenCore feature to compile and simulate the DDR SDRAM Controller MegaCore function, allowing you to evaluate it before purchasing a license. However, you must purchase and install a license from Altera before you can generate programming files or EDIF, VHDL, or Verilog HDL gate-level netlist files for simulation in third-party EDA tools. You can request a license file for your purchased DDR SDRAM Controller from the Altera web site at and install it on your PC. When you request a license file, Altera s you a license.dat file. If you do not have Internet access, contact your local Altera representative. 2 To install your license, you can either append the license to your license.dat file or you can specify the core s license.dat file in the Quartus II software. 1 Before you set up licensing for the DDR SDRAM Controller, you must already have the Quartus II software installed on your PC with licensing set up. Getting Started Append the License to Your license.dat File To append the license, perform the following steps: 1. Close the following software if it is running on your PC: Quartus II MAX+PLUS II LeonardoSpectrum Synplify ModelSim 2. Open the DDR SDRAM Controller license file in a text editor. The file should contain one FEATURE line, spanning 2 lines. 3. Open your Quartus II license.dat file in a text editor. 4. Copy the FEATURE line from the DDR SDRAM Controller license file and paste it into the Quartus II license file. 1 Do not delete any FEATURE lines from the Quartus II license file. Altera Corporation 19

20 Getting Started DDR SDRAM Controller MegaCore Function User Guide 5. Save the Quartus II license file. 1 When using editors such as Microsoft Word or Notepad, ensure that the file does not have extra extensions appended to it after you save (e.g., license.dat.txt or license.dat.doc). Verify the filename in a DOS box or at a command prompt. Specify the Core s License File in the Quartus II Software To specify the core s license file, perform the following steps: 1. Create a text file with the FEATURE line and save it to your hard disk. 1 Altera recommends that you give the file a unique name, e.g., <core name>_license.dat. 2. Run the Quartus II software. 3. Choose License Setup (Tools menu). The Options dialog box opens to the License Setup page. 4. In the License file box, add a semicolon to the end of the existing license path and filename. 5. Type the path and filename of the core license file after the semicolon. 1 Do not include any spaces either around the semicolon or in the path/filename. 6. Click OK to save your changes. 20 Altera Corporation

21 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started DDR SDRAM Controller Walkthrough This walkthrough describes the design flow using the Altera DDR SDRAM Controller MegaCore function and the Quartus II development system. Altera provides a MegaWizard Plug-In with the DDR SDRAM Controller. The MegaWizard Plug-In Manager, which you can use within the Quartus II software, lets you create or modify design files to meet the needs of your application. This walkthrough consists of the following steps: Create a New Quartus II Project Launch the MegaWizard Plug-In Manager Choose the Parameters Complete the Custom Core Create a New Quartus II Project Before you create a core, you must create a new Quartus II project. With the New Project wizard, you specify the working directory for the project, assign the project name, and designate the name of the top-level design entity. You also specify the DDR SDRAM Controller user library. To create a new project, perform the following steps: 2 Getting Started 1. Choose Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software. 2. Choose New Project Wizard (File menu). 3. Click Next in the introduction (the introduction does not display if you turned it off previously). 4. Specify the working directory for your project. 5. Specify the name of the project. 1 For the dummy top-level flow only, enter <variation name>_dummy_top as the top-level design entity name, where <variation name> is the name that you will chose for your custom function. 6. Click Next. 7. Click User Library Pathnames. 8. Type <path>\ddr_sdram-<version>\lib\ into the Library name box, where <path> is the directory in which you installed the DDR SDRAM Controller. The default installation directory is c:\megacore. Altera Corporation 21

22 Getting Started DDR SDRAM Controller MegaCore Function User Guide 9. Click Add. 10. Click OK. 11. Click Next. 12. Click Next. 13. Choose the device family you wish to target from the Device dropdown box. Select Yes, you want to assign a specific device. 14. Choose an available device from the Device list. 1 The DDR SDRAM Controller wizard-generated constraint script is suitable only for the following devices: 15. Click Next. - Cyclone EP1C20F400C6 device - Stratix EP1S25F1020C6 device - APEX II EP2A15F672C7 device 16. Click Finish. Launch the MegaWizard Plug-In Manager The MegaWizard Plug-In Manager allows you to run a wizard that helps you easily specify options for the DDR SDRAM Controller. To launch the wizard, perform the following steps: 1. Start the MegaWizard Plug-In Manager by choosing the MegaWizard Plug-In Manager command (Tools menu). The MegaWizard Plug-In Manager dialog box is displayed. 1 Refer to the Quartus II Help for more information on how to use the MegaWizard Plug-In Manager. 2. Specify that you want to create a new custom megafunction and click Next. 3. Expand the Interfaces and Memory Controllers directories. Choose DDR SDRAM-<version> in the Memory Controllers directory. 4. Choose the output file type for your design; the wizard supports, VHDL, Verilog HDL, and AHDL (except for dummy top-level flow). 1 The MegaWizard Plug-In also generates symbol files (.bsf). 22 Altera Corporation

23 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started 5. Specify a directory, <directory name> and name for the output file, <variation name>. Figure 4 shows the wizard after you have made these settings. Figure 4. Selecting the Megafunction 2 Getting Started 6. Click Next. Choose the Parameters To specify your custom core parameters, perform the following steps: 1. Choose the size parameters (see Figure 5). 1 To use the wizard-generated constraint script choose data width bits = 32 bits for Stratix and APEX II devices; 16 bits for Cyclone devices. Altera Corporation 23

24 Getting Started DDR SDRAM Controller MegaCore Function User Guide Figure 5. Choose the Size Table 9 describes the available size parameters. Table 9. Size Parameters Parameter Range Description Data width bits 8, 16, 24, 32, 40, 48, 64, 72, or 80 The memory interface width. The local bus interface width is twice the memory interface width, because the DDR SDRAM interface is clocked on both edges of the clock. The maximum memory width possible with the DDR SDRAM Controller on a Cyclone device is 48 bits, and this is reduced even further if more than one IO bank is not set to 2.5V. Row address bits 11 to 14 The number of row address bits in the memory device. Column address bits 8 to 13 The number of column address bits in the memory device. Number of banks 2 or 4 The number of banks in the memory device. Number of chip selects 1, 2, 4, or 8 The number of chip-select signals. 24 Altera Corporation

25 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started Table 10 describes the options. Table 10. Options Parameter Description Dummy top-level design The dummy top-level design name, which is created with the custom variation. The dummy top-level design is a minimal design that allows you to compile the DDR SDRAM Controller into a device. It instantiates the DDR SDRAM Controller custom variation, some dummy logic (a set of registers) between the local-side interface and the FPGA pins, and the necessary PLLs. You can use the dummy top-level design to compile the DDR SDRAM Controller in the Quartus II software and perform a simple timing analysis. This dummy top-level design also illustrates how to create a working system with the DDR SDRAM Controller. You can edit this file, and replace the dummy-logic with a real local-side interface. The default name is <variation name>_dummy_top where <variation name> is the name you chose for your DDR SDRAM Controller. Overwrite Overwrite indicates whether or not the MegaWizard Plug-In overwrites the existing dummy top-level design. Choose not to overwrite if you have edited the dummy toplevel design file and added your own code. Target device family The DDR SDRAM Controller supports the Stratix, Stratix GX, APEX II, and Cyclone device families. The device family is the same as the family that you chose in the Quartus II software, unless you chose an unsupported device family, whereby it defaults to Stratix. Non 2.5 V on left-hand side For Cyclone devices only. To use DDR-SDRAM byte groups on the left-hand side (LHS) of the device, the left-hand power bank must be set to 2.5 V, where LHS refers to the die orientation. Checking this option prevents you from making byte group assignments on the LHS of the device. This option also limits the maximum possible memory interface width to 24-bits for the smaller devices. For more information, refer to the Cyclone data sheet. 2 Getting Started 2. Click Next. 3. Enter a value for the System Clock (see Figure 6). The System Clock text box accepts values from 77.0 to MHz. To set default timer settings for the chosen frequency, click Set Defaults. 1 For frequencies other than MHz, see Configure the PLL on page Enter the timer settings and choose the timing parameters (see Figure 6). Altera Corporation 25

26 Getting Started DDR SDRAM Controller MegaCore Function User Guide 1 The default initialization time is 50 cycles, which is appropriate for simulation. If you click Set Defaults, the initialization time sets the correct number of cycles to give a 200 µs delay. If you intend to simulate you should change the initialization time back to a small number (eg. 50 cycles) to avoid lengthy simulation times. Figure 6. Choose Timing Parameters & Timer Settings 26 Altera Corporation

27 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started Table 11 describes the available memory timing parameters. Table 11. Memory Timing Parameters (Part 1 of 2) Parameter Range Description Burst length 2, 4, or 8 The maximum number of data words in each DDR SDRAM data burst. The burst length on the local bus interface is half the burst length on the DDR SDRAM interface, because the DDR SDRAM interface is clocked on both edges of the clock. CAS latency (CL) 2.0, 2.5, or 3.0 After you assert cas_n, the memory presents the data CL clock cycles later. Generally the higher the clock speed, the higher the CAS latency. DDR SDRAM typically uses a setting of 2.0, 2.5, or 3.0 cycles. Consult your chosen DDR SDRAM memory device data sheet for appropriate settings. CL= 2.0 can typically be used for frequencies up to 133 MHz. CL= 2.5 can typically be used for frequencies up to 167 MHz. CL= 3.0 is typically required for frequencies of 200 MHz and above. The read resynchronization phase setting (see Resynchronization of Captured Read Data from the DQS to the System Clock Domain on page 78) may delay the read data a further clock cycle. Precharge command period (RP) 2, 3, or 4 The time that must elapse between a precharge command and banks becoming available for row access. RP is derived from t RP and the clock speed and is specified in clock cycles. 2 Getting Started RP = (t RP /clock period), rounded up to the next integer value, Active A to active B (RRD) where t RP is the value from the SDRAM data sheet, clock period is the clock period of the SDRAM clock. 2, 3, or 4 After an active command to one bank, there must be at least a minimum time interval before the DDR SDRAM Controller issues a subsequent active command to a different bank. RRD is derived from t RRD and the clock speed and is specified in clock cycles. RRD = (t RRD /clock period), rounded up to the next integer value, where t RRD is the value from the SDRAM data sheet, clock period is the clock period of the SDRAM clock. Altera Corporation 27

28 Getting Started DDR SDRAM Controller MegaCore Function User Guide Table 11. Memory Timing Parameters (Part 2 of 2) Parameter Range Description Active to read/write (RCD) 3, 4, or 5 The active command opens a row in a particular bank. After an active command, the DDR SDRAM controller does not issue a read or write command until the minimum time interval has expired. RCD is derived from t RCD and the clock speed and is specified in clock cycles. RCD = (t RCD /clock period), rounded up to the next integer value, Auto-refresh command period (RFC) where t RCD is the value from the SDRAM data sheet, clock period is the clock period of the SDRAM clock. 7 to 14 The auto-refresh command period is the amount of time that must pass between successive auto-refresh commands. RFC is derived from t RFC and the clock speed and is specified in clock cycles. RFC = (t RFC /clock period), rounded up to the next integer value, Write recovery time (WR) where t RFC is the value from the SDRAM data sheet clock period is the clock period of the SDRAM clock. 2 or 3 Set the write recovery time to 3 for operation at higher frequencies (consult memory device data sheet). 28 Altera Corporation

29 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started Table 12 describes the available timer settings. Table 12. Timer Settings Parameter Refresh command interval timer Initialization time Description The refresh command interval is the number of clock cycles that elapse between each refresh command and is given by: refresh period /clock period, rounded up to the next integer value. If an SDRAM device connected to the controller has a 64-ms, 4,096-cycle refresh requirement, the controller must issue a refresh command to the device at least every 64 ms/4,096 = µs. If the SDRAM and controller are clocked by a 100-MHz clock, the maximum value is µs/0.01µs = 1,562 clock cycles. The initialization time specifies the settling time after power up, and after the clocks have settled, that the SDRAM device requires before any command activity from the DDR-SDRAM Controller. This time is typically 200 µs and is given by: 2 Getting Started 200 µs/clock period, rounded up to the next integer value. For simulation a small value such as 50 cycles is sufficient. The DDR SDRAM Controller starts this initialization count when it is released from reset. If the reset is a known delay after power-on (and PLL settling), the initialization period can be reduced if advantageous. The mode registers are written after this delay. There is also a DLL lock timer delay built into the DDR SDRAM Controller. This is a fixed period of 200 cycles of clk (independent of frequency) during which the core waits while the DLLs within the memory device lock. This period starts after the mode registers have been written (thus enabling the memory devices DLLs) and when the delay is over, the core can accept user commands. 5. Click Next. Altera Corporation 29

30 Getting Started DDR SDRAM Controller MegaCore Function User Guide 6. Select positive or negative clock edge (see Figure 7). This option allows you to control which edge of the system clock (clk) to use for the SDRAM address and command outputs. Which edge you choose depends on how your hardware is setup and how you have setup the clocks. For this walkthrough the following recommendations apply: For Stratix and Cyclone devices, select the negative edge. For APEX II devices, you can also select the negative edge. Use the positive edge if you are using the slower sidebanks for the address and command outputs and the sidebanks are sufficiently slow to guarantee hold time at the SDRAM. Figure 7. Select Output Edge & Resynchronization Phase 7. Select the Resynchronization Phase. This option allows you to control the resynchronization of data from the dqs clock domain into the system clock domain. You should understand your hardware before you decide which phase to select. f For more information, see Resynchronization of Captured Read Data from the DQS to the System Clock Domain on page Altera Corporation

31 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started f 8. Click Next. 9. For Cyclone devices only, select the positions on the device for each of the DDR SDRAM byte groups (see Figure 8). This flow only allows you to implement a 16-bit interface on the LHS of an EP1C20F400 device. For more information on the floorplan, see the doc/readme.txt file. a. To place an un-placed byte group, select the unplaced byte group in the drop-down box at your chosen position. Placed byte-groups are no longer available in the drop-down boxes. b. To move a placed byte group, un-place the byte group from the current location (select -- in the drop-down box). The byte group now appears in all of the other empty byte group locations, so you can now place the byte group as described previously. The floorplan matches the orientation of the Quartus II floorplanner. The layout represents the die as viewed from above. A byte group consists of eight dq pins, a dm pin and a dqs pin. The larger Cyclone devices have eight possible regions where you can place a byte group two on each side of the device. The smaller devices only have a total of four groups one on each side of the device. On all devices, if the LHS power bank is configured for anything other than 2.5V (e.g., if you are using configuration devices), that side of the device is no longer available for use as DDR SDRAM pins. The EP1C3T100 cannot use the LHS or RHS of the device for 2.5V DDR, so is always limited to a maximum of three byte groups. The JTAG and configuration output pins are on the RHS and must be configured for 2.5 V operation, to use that side of the device for DDR. 1 The wizard does not make assignments for the address and control pins; you must make these pin assignments. 2 Getting Started Altera Corporation 31

32 Getting Started DDR SDRAM Controller MegaCore Function User Guide Figure 8. Select Byte Group Position Complete the Custom Core To complete your custom core, perform the following steps: 1. The final screen lists the design files that the wizard creates (see Figure 9). Click Finish. The wizard generates the following files: One of the following files (depending on your selection), which are used to used to instantiate an instance of the function in your design: - AHDL text design file (<variation name>.tdf) - VHDL design file (<variation name>.vhd) - Verilog HDL design file (<variation name>.v) A symbol file (<variation name>.bsf) used to instantiate the function into a schematic design An include file <variation name>.inc (Verilog HDL and AHDL only) An example of the instantiation of the core <variation name> _inst A blackbox Verilog HDL model, <variation name>_bb (Verilog HDL only) A component declaration file <variation name>.cmp (VHDL only) <variation name>_quartus_script.tcl, which can be used to apply the necessary constraints to your custom core (not applicable for Cyclone devices) 32 Altera Corporation

33 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started Figure 9. Design Files <dummy top-level wrapper>, which instantiates your synthesized instance of the DDR SDRAM Controller, some dummy logic, and the necessary PLLs A plain-text configuration file user_assignments.txt that is read in by the Cyclone constraint generation script. This file defines the byte group locations, which you chose using the floorplanner on page 4 of the wizard, with other assignments. Cyclone devices only. 1 <variation name> is the variation name that you chose in the MegaWizard Plug-In. 1 <dummy top-level wrapper> is the dummy top-level design name, which you chose on page 1 of the wizard. The default name is <variation name>_dummy_top. 2 Getting Started 2. Before performing any other actions, read and click OK on the message window (Figure 10). Altera Corporation 33

34 Getting Started DDR SDRAM Controller MegaCore Function User Guide Figure 10. Message When you have created your custom megafunction, you can integrate it into your system design and compile. Using the Reference Design The reference design is the same for all device families with different parameters: 32-bits for Stratix and APEX II devices; 16-bits for Cyclone devices. 1 Altera recommends that you copy the following directories to a new directory <working directory> before use: /reference_design /testbench /user_simulation f For more information on the reference design for Cyclone devices, read the doc/readme_test_stim.txt file. Set Up the Reference Design To set up the reference design, perform the following steps: 1. Choose Open Project (File menu). 2. Browse to the \<working directory>\reference_design\<family> directory. Click Open. Choose example_top.quartus and click Open. 34 Altera Corporation

35 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started 3. You must specify the DDR SDRAM Controller s library directory (<path>\ddr_sdram-<version>\lib) as a user library in the Quartus II software. Search for User Libraries in Quartus II Help for instructions on how to add a library. 4. Choose MegaWizard Plug-In Manager (Tools menu). 5. Select Edit an existing Custom Megafunction and click Next. 6. Choose mw_wrapper.vhd file and Click Next. 7. Click Finish. 1 Do not change any of the MegaWizard Plug-In settings. 8. Click OK on any warning messages. Compile the Reference Design 2 Getting Started For Cyclone devices, perform the following steps: 1. Open a Command Prompt. 2. Type the following command: cd <working directory>/reference_design/cyclone_example 3. Type the following command: generate_quartus_tcl_script_for_ref_design 1 Do not run the generate_quartus_tcl_script.bat file. 4. In the Quartus II Tcl console type the following command: source add_constraints.tcl 5. Choose Start Compilation (Processing menu). For Stratix and APEX II devices, perform the following steps: 1. In the Quartus II Tcl console type the following command: source mw_wrapper_quartus_script.tcl 2. Choose Start Compilation (Processing menu). Altera Corporation 35

36 Getting Started DDR SDRAM Controller MegaCore Function User Guide Post-route Simulation To simulate in the ModelSim simulator, perform the following steps: 1. Open the ModelSim simulator. Select Change Directory (File menu) and change to the \<working directory>\user_simulation directory. 2. Choose Execute Macro (Macro menu). 3. For ModelSim PE choose simulate_<family>_ref_design_gate.do; for ModelSim-Altera simulate_ae_<family>_ref_design_gate.do and click Open. f Configure the PLL For more information on the reference design test stimulus, see the /reference_design/test_stimulus/readme_test_stim.txt file If you have specified a frequency other than MHz, you must edit the following PLL instances: /lib directory for the dummy top-level flow /reference_design directory for the reference design To edit the PLL instances for the dummy top-level flow, perform the following steps: 1. Open the Quartus II software. 2. Choose Open Project (File menu). 3. Browse to your relevant project. Click Open. 4. Choose MegaWizard Plug-In Manager (Tools menu). 5. Select Edit an existing Custom Megafunction and click Next. 6. Choose the \ddr_sdram-v<version>\lib directory in the Look-In box. 7. Choose the appropriate example_<family>.vhd file and Click Next. 8. Edit the PLL instance and click Finish. To edit the PLL instances in the reference design, perform the following steps: 1. Open the Quartus II software. 36 Altera Corporation

37 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started Behavioral Simulation 2. Choose Open Project (File menu). 3. Browse to the \ddr_sdram-v<version>\reference_design\<family> directory. Click Open. Choose example_top.quartus and click Open. 4. Choose MegaWizard Plug-In Manager (Tools menu). 5. Select Edit an existing Custom Megafunction and click Next. 6. Choose example_pll_<family>.vhd file and Click Next. 7. Edit the PLL instance and click Finish. Altera provides a ModelSim VHDL model that you can use to simulate the DDR SDRAM Controller in your system. Altera also provides a Visual IP model in the sim_lib\visualip directory, which you can use with the Visual IP software and is supported by other Verilog HDL and VHDL simulators. The VHDL model is supplied as pre-compiled libraries for the ModelSim simulation tool and is installed in the sim_lib\modelsim\vhdl\ directory. You can use these models to simulate the core in your system, or you can use them with the testbench provided with the core. Simulate with the ModelSim VHDL Model Before you simulate the VHDL model of your instance using the testbench in the ModelSim software, perform the following steps: 1. Download the Micron MT46V16M8 128-MB memory model (or equivalent) to the \ddr_sdram-v<version>\testbench\vhdl directory from the Micron web site, DDR+SDRAM. 2. Open the Quartus II software. 3. Choose Open Project (File menu). 4. Browse to the \ddr_sdramv<version>\user_simulation\proj_for_your_instance directory. 5. Choose example.quartus and click Open. 6. Start the MegaWizard Plug-In Manager by choosing the MegaWizard Plug-In Manager command (Tools menu). The MegaWizard Plug-In Manager dialog box is displayed. 2 Getting Started Altera Corporation 37

38 Getting Started DDR SDRAM Controller MegaCore Function User Guide 7. Specify that you want to edit a custom megafunction and click Next. 8. Choose example.vhd (see Figure 11). Figure 11. Choose Example.vhd 9. Choose your parameters (see Choose the Parameters on page 23). 1 Set small value (e.g., 50) for memory initialization time, to keep the simulation time short. 10. Click Finish. 11. Click OK on the constraint script warning message. 1 You need not run the constraints scripts in this Quartus II project unless you want to compile this project. To simulate the VHDL model of your instance in the ModelSim simulation tool, perform the following steps: 38 Altera Corporation

39 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started 1. Open the ModelSim simulator. Select Change Directory (File menu) and change to the \ddr_sdram-v<version>\user_simulation directory. 2. Choose Execute Macro (Tools menu). 3. Choose simulate_your_instance_rtl.do (see Figure 12) and click Open. Figure 12. Select simulate_your_instance_rtl.do 2 Getting Started The simulate_your_instance_rtl.do script performs the following functions: Maps the provided library Refreshes the library Creates a working library work Compiles your instance and the provided testbench into work Executes vsim and opens a wave window with the testbench signals Passes in parameters Simulate with the Visual IP Model Follow the instructions below to obtain the Visual IP software via the Internet. If you do not have Internet access, you can obtain the Visual IP software from your local Altera representative. 1. Point your web browser at /eda_software/visualip/dnl-visualip.jsp. Altera Corporation 39

40 Getting Started DDR SDRAM Controller MegaCore Function User Guide 2. Follow the on-line instructions to download the Innoveda Visual IP software and save it to your hard disk. To use the Visual IP model, perform the following steps: 1. Set up your system to use the Visual IP software, as detailed in the Visual IP documentation (Simulating Visual IP Models with the ModelSim Simulator for PCs White Paper, Simulating the Visual IP Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX) Simulators White Paper). 2. Compile the wrapper for the core model. The Verilog HDL version of the wrapper is in the sim_lib\visualip\auk_ddr_sdram\interface\pli directory; the corresponding VHDL version is in the sim_lib\visualip\auk_ddr_sdram\interface\mti directory. 3. Compile the memory model that you want to use. 4. Compile the wizard-generated wrapper <variation name>.vhd, <variation name>.v. The Visual IP model is now ready for use in your simulator. Compile & Place-&-Route After you have verified that your design is functionally correct, you are ready to compile and place-and-route your design. The Quartus II software works seamlessly with tools from many EDA vendors, including Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, and Viewlogic. Cyclone Devices For Cyclone devices, before you compile and place-and-route your project, perform the following steps: 1. Open a Command Prompt. 2. Type the following command: cd <your project> 3. Type the following command: generate_quartus_tcl_script 40 Altera Corporation

41 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started 4. In the Quartus II Tcl console type the following command: source add_constraints.tcl 5. Choose Start Compilation (Processing menu). Stratix & APEX II Devices Before you compile and place-and-route your project, you should run the MegaWizard Plug-In generated Quartus II constraint script (<variation name> quartus_script.tcl), or follow the manual procedure in Appendix A The Quartus II Constraint Settings on page 67. If you selected an APEX II device in the MegaWizard Plug-In, the Quartus II constraint script performs the following actions on your Quartus II project: Selects an APEX II device (EP2A15C672) Applies the necessary Quartus II constraints for your chosen frequency Creates LogicLock regions that place the controller in the bottom right of the APEX II device Applies a sample pin configuration to match the controller 2 Getting Started If you selected a Stratix device in the MegaWizard Plug-In, the Quartus II constraint script performs the following actions on your Quartus II project: Copies the reference design files into your project directory Selects a Stratix device (EP1S25F1020) Applies the necessary Quartus II constraints for your chosen frequency Applies a sample pin configuration to match the controller f For more information on LogicLock incremental design capability, refer to AN 161: Using the LogicLock Methodology in the Quartus II Design Software. To apply the Quartus II constraint script, perform the following steps: 1. Choose Auxiliary Windows > Tcl Console (View menu). 2. In the Tcl console window type the following command: source <variation name>_quartus_script.tcl Altera Corporation 41

42 Getting Started DDR SDRAM Controller MegaCore Function User Guide You can now compile your design. The Quartus II Compiler synthesizes, performs place-and-route, and applies the necessary timings to your design. 1 Refer to the Quartus II Help for further instructions on performing compilation. Timing Analysis After you have compiled your design in Quartus II, to check that the timing requirements have been met, perform the following step: v Check the compiler messages in the Processing tab in the Messages window. If the timing requirements were met, the following message appears during compilation: All timing requirements were met. See Report window for more details. If timing requirements were not met, open the Timing Analysis folder in the Compilation Report window. Open the Clock Requirements section for each clock to check that all requirements were met. Paths that failed to meet timing requirements are marked in red. 1 You can use the MegaWizard-generated system to check timing in the Quartus II software. However, if you want to perform hardware testing or gate-level simulation, use the reference design. Perform Post- Route Simulation If you have licensed the core, you can generate EDIF, VHDL, Verilog HDL, and standard delay output files from the Quartus II software and use them with your existing EDA tools to perform functional modeling and post-routing simulation of your design. 1. Open your existing Quartus II project. 2. Depending on the type of output file you want, specify Verilog HDL output settings or VHDL output settings in the General Settings dialog box (Project menu). 3. Compile your design with the Quartus II software, see Compile & Place-&-Route on page 40. The Quartus II software generates output and programing files. 4. You can now import your Quartus II software-generated output files (.edo,.vho,.vo, or.sdo) into your third-party EDA tool for postroute, device-level, and system-level simulation. 42 Altera Corporation

43 DDR SDRAM Controller MegaCore Function User Guide GettingGetting Started 1 Alternatively, you can use the reference design for post-route simulation, see Post-route Simulation on page 36. License for Configuration After you have compiled and analyzed your design, you are ready to configure your targeted Altera FPGA. If you are evaluating the DDR SDRAM Controller with the OpenCore feature, you must license the function before you can generate programming files. To obtain licenses contact your local Altera sales representative. 2 Getting Started Altera Corporation 43

44 Notes:

45 Specifications 1 Functional Description Figure 13. DDR SDRAM Controller Block Diagram Local Bus Interface raddr r_req w_req b_size rw_ack r_valid d_req w_valid clk The DDR SDRAM Controller instantiates a control logic module and one or more data path modules. Figure 13 shows a block diagram of the DDR SDRAM Controller. Control Logic a ba cs_n ras_n cas_n we_n cke SDRAM Interface Specifications DII Interface Specifications 3 clk_shifted dq datain dataout dm_in Data Path Modules dqs dm Signals Table 13 shows the DDR SDRAM Controller local interface signals; Table 14 shows the DDR SDRAM Controller SDRAM interface signals. The local interface signals operate on the positive edge of clk with the following exception: dataout[] is generated on either the positive or negative edge of clk depending on the read resynchronization phase setting (see Altera Corporation 45