1. Specifications Applicable Conditions Operational Overview of Functions Used Principles of Operation...

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1 APPLICATION NOTE SH7080 Group Introduction This application note provides information that may be useful in designing software. The note describes how to erase and program the flash memory when the flash reprogram command is received via a UART (Universal Asynchronous Receiver/Transmitter) during execution of a user application in the user program mode. In the user program mode, which is one of the three on-board programming modes along with the boot mode and the user boot mode, flash memory can be erased or programmed using any interface. Target Device SH7086 Contents 1. Specifications Applicable Conditions Operational Overview of Functions Used Principles of Operation Description of Software Flowcharts REJ06B /Rev.1.00 September 2006 Page 1 of 28

2 1. Specifications SH7080 Group In this sample task, the flash reprogram command is received via a UART while the user application is being executed in the user program mode, and flash memory is erased and programmed. Figure 1 shows the operations of this sample task. SH7080 Group MCU Flash memory Host (PC) Flash erasing/ programming tool and program data RXD1 TXD1 Internal SCI_1 Internal RAM Flash erasing/ programming/ reading program Figure 1 Erasing and Programming Flash Memory in User Boot Mode 2. Applicable Conditions Microcomputer: SH7086 (R5F7086) Operating frequency: Internal clock 80 MHz : Bus clock 40 MHz : Peripheral clock 40 MHz : MTU2 clock 40 MHz : MTU2S clock 80 MHz C Compiler: Renesas Technology V REJ06B /Rev.1.00 September 2006 Page 2 of 28

3 3. Operational Overview of Functions Used 3.1 Flash Memory A block diagram of flash memory is shown in figure 2. Block diagram of flash memory Internal address bus Internal data bus (32 bits) FCCS FPCS FECS Module bus FKEY FMATS Control section Memory MAT section FTDAR RAMER User MAT: 512 KB or 256 KB User boot MAT: 12 KB FWE pin Mode pin Operating mode [Legend] FCCS: Flash code control and status register FPCS: Flash program code select register FECS: Flash erasing code select register FKEY: Flash key code register FMATS: Flash MAT select register FTDAR: Flash transfer destination address register RAMER: RAM emulation register Figure 2 Block Diagram of Flash Memory REJ06B /Rev.1.00 September 2006 Page 3 of 28

4 The Flash Code Control and Status (FCCS) register consists of the bits for monitoring the FWE pin state, for indicating the error occurrence during execution of flash memory programming or erasing, and the bit for requesting downloading of the internal program. The Flash Program Code Select (FPCS) register is used to select downloading of an internal program related to programming. The Flash Erase Code Select (FECS) register is used to select downloading of an internal program related to erasing. The Flash Key Code (FKEY) register is a software protection register that enables downloading of internal programs, and programming and erasing of flash memory. For these operations, separate key codes are required: one must be written before 1 is written to the SCO bit that enables downloading of an internal program and one must be written before a downloaded programming/erasing program can be executed. The Flash MAT Select (FMATS) register is used to select user MAT or user boot MAT. The Flash Transfer Destination Address Register (FTDAR) is used to specify the address in the internal RAM to which the internal program is to be downloaded. Specify this register before writing 1 to the SCO bit in the FCCS register. The initial register value is H'00, which indicates address H'FFFF9000 in the internal RAM. te: Please see Flash Memory in Section 23 of the SH7080 Group Hardware Manual for details regarding operational specification of each register. REJ06B /Rev.1.00 September 2006 Page 4 of 28

5 3.2 Programming/Erasing Interface Parameters SH7080 Group The programming/erasing interface parameters specify the operating frequencies for a downloaded internal program, the user branch destination address, the location for storing program data, the programming destination address, the blocks to be erased, as well as exchanging processing results. The programming/erasing interface parameters are used for the following functions: 1. Download control 2. Initialization before programming or erasing 3. Programming 4. Erasing Table 1 Parameters and Applicable Mode Parameter Name Abbreviation Downloading Initialization Programming Erasing Allocation Download pass/fail result DPFR Ο Internal RAM Flash pass/fail result FPFR* Ο Ο Ο R0 register of the CPU Flash programming/erasing frequency control FPEFEQ Ο R4 register of the CPU Flash user branch address set parameter FUBRA Ο R5 register of the CPU Flash multipurpose address area FMPAR Ο R5 register of the CPU Flash multipurpose data destination area FMPDR Ο R4 register of the CPU Flash erase block select parameter FEBS Ο R4 register of the CPU te: Please see Section 23 Flash Memory of the SH7080 Group Hardware Manual for details regarding operational specification of each register. * For the FPFR parameter, although a processing results of initialization, programming, and erasing operations are returned, the meaning of the bits vary depending on the nature of the processing. Each parameter is readable and writable, and respective initial values are undefined. REJ06B /Rev.1.00 September 2006 Page 5 of 28

6 3.3 Specifications of Flash Erasing/Programming SH7080 Group The flash erasing/programming specifications are shown in figure 3. The memory map of the user MAT and internal RAM for this sample task is shown in figure 4. [Internal RAM] [Erasing] User area Address RAMTOP Address FTDAR specification DPFR (Return value: 1 byte) 4 KB x 8 32 KB EB0 to EB7 Download area (size: 3 KB) Erasing program download area Programming program download area System area (15 bytes) FTDAR specification Programming/erasing entry + 16 FTDAR specification Initialization processing entry + 32 Initialization + programming program or initialization + erasing program 64 KB 64 KB 64 KB 64 KB 64 KB EB8 EB9 EB10 EB11 EB12 FTDAR specification KB EB13 User area 64 KB EB14 RAM emulation area 64 KB EB15 User area RAMEND Erase blocks EB1 to EB15 are to be erased. EB0 will not be erased because it contains the communication program. [Programming] Flash memory H' H' H' bytes 128 bytes 128 bytes Data reception (128 bytes) Procedure program Programming control program H'0007FE bytes H'0007FF bytes Data is received from address H' on. Data from address H' on. H'0007FF bytes Figure 3 Flash Erasing/Programming Specifications REJ06B /Rev.1.00 September 2006 Page 6 of 28

7 User MAT H' to DF H' to FF H' to FF H' to 0000 FFFF H' to 0007 FFFF H'FFFF 4000 to FFFF 47FF H'FFFF 4800 to FFFF 8FFF H'FFFF 9000 to FFFF 9FFF H'FFFF A000 to FFFF AFFF Vector table User application SCI1 communication program Procedure program storage area Reprogram target area Internal RAM Data area Procedure program execution area Erasing program download area 0000 DPFR (Return value: 1 byte) 0001 to 000F System area (15 bytes) 0010 to 001F Erasing processing entry 0020 to 002F Erasing initialization entry 0030 to 0FFF Erasing initialization + erasing program Programming program download area 0000 DPFR (Return value: 1 byte) 0001 to 000F System area (15 bytes) 0010 to 001F Programming processing entry 0020 to 002F Programming initialization entry 0030 to 0FFF Programming initialization + programming program Figure 4 Memory Map of the User MAT and Internal RAM REJ06B /Rev.1.00 September 2006 Page 7 of 28

8 4. Principles of Operation Table 2 Command Specifications Command Command Value Description CMD_GO H 55 Flash erasing/programming request command CMD_READ H AA Flash read request command CMD_ERASE H 77 Flash erasing request command CMD_WRITE H 88 Flash programming request command CMD_WEND H 99 Flash programming end command CMD_OK H 00 OK (normal end response) command CMD_NG H 01 NG (abnormal end response) command CMD_REQUEST H 11 Transmit request command REJ06B /Rev.1.00 September 2006 Page 8 of 28

9 The command control sequence in this sample task is shown in figure 5. SH7080 Group Flash erasing/programming tool (UART tool) SH7080 Group MCU Transmit the read data (in 1-byte units) Flash read request command (CMD_READ) Read the flash memory Transmit data equivalent to the specified read request size. Flash erasing/programming request command (CMD_GO) Copy the procedure program to the RAM Execute the procedure program in the RAM Download the erasing program Perform initial setting for erasing Download the programming program CMD_OK Perform initial setting for programming Flash erasing request command (CMD_ERASE) Flash programming request command (CMD_WRITE) Erase the flash memory Receive the programming address and programming size Repeated until there is no more data to be programmed. Transmit request command (CMD_REQUEST) Receive the program data (in 128-byte units) Program the flash memory CMD_OK Confirm the flash programming end command (CMD_WEND) CMD_OK END END Figure 5 Command Control Sequence REJ06B /Rev.1.00 September 2006 Page 9 of 28

10 5. Description of Software 5.1 Description of Modules The modules of this sample task are described in table 3. Table 3 Modules Module Name Label Name File Name Description Main routine main() main.c Initial setting of SCI channel 1 Executes the user application program. Performs flash erasing/programming processing when there is a flash erasing/programming request. SCI channel 1 initial setting routine com_init () sci.c Handles SCIF transmit-fifo-data-empty interrupts. SCI_1 receive data CheckRcv() Checks whether receive data is stored in SCRDR. presence check routine SCI_1 n-byte rcvnbyte() Receives data for the number of bytes specified. reception routine SCI_1 1-byte trs1byte() Writes 1 byte to be output serially. transmission routine Erasing program download and SetupFlashErase() flash.c Downloads the erasing program into the RAM and performs initialization. initialization routine Flash erasing routine FlashErase() Erase the specified erase blocks sequentially starting with the EB0 block. Programming program download and initialization routine Flash programming routine Flash programming main routine Flash reading routine SetupFlashWrite() FlashWrite() FlashMain() FlashRead() Downloads the programming program into the RAM and performs initialization. Writes data to the specified address Checks commands and performs erasing/programming. Reads flash memory starting from the specified address for the specified size. REJ06B /Rev.1.00 September 2006 Page 10 of 28

11 5.2 Variables Used The variables used in this sample task are described in table 4. Table 4 Variables Used Variable, Label Name Description Used in unsigned char WriteBuff[128] Program data area FlashMain () unsigned char Erasing program download area SetupFlashErase() flash_erase[2048] unsigned char flash_write[2048] Programming program download area SetupFlashWrite() 5.3 Setting the Registers This section describes the setting of registers used in this sample task. te that the settings shown below are used in the sample task and are not initial values Register for Setting the Clock Pulse Generator (CPG) Frequency Control Register (FRQCR) The Frequency Control Register specifies the division ratio of the operating frequency. Setting value: H'0241 Bit Bit Name Setting Value Function 15 0 Reserved 14 to 12 IFC[2:0] 000 Division ratio of the internal clock (Iφ) frequency 000: x 1, 80 MHz when the input clock is 10 MHz 11 to 9 BFC[2:0] 001 Division ratio of the bus clock (Bφ) frequency 001: x 1/2, 40 MHz when the input clock is 10 MHz 8 to 6 PFC[2:0] 001 Division ratio of the peripheral clock (Pφ) frequency 001: x 1/2, 40 MHz when the input clock is 10 MHz 5 to 3 MIFC[2:0] 000 Division ratio of the MTU2S clock (MIφ) frequency 000: x 1, 80 MHz when the input clock is 10 MHz 2 to 0 MPFC[2:0] 001 Division ratio of the MTU2 clock (MPφ) frequency 001: x 1/2, 40 MHz when the input clock is 10 MHz REJ06B /Rev.1.00 September 2006 Page 11 of 28

12 5.3.2 Setting the Power-Down Mode Standby Control Register 3 (STBCR3) This register controls the operation of each module in the power-down mode. Setting value: H'EF Bit Bit Name Setting Value Function 7 MSTP15 1 1: Stops clock supply to I 2 C2 module. 6 MSTP14 1 1: Stops clock supply to the SCIF module. 5 MSTP13 1 1: Stops clock supply to SCI_2 module. 4 MSTP12 0 0: SCI_1 module in operation. 3 MSTP11 1 1: Stops clock supply to SCI_0 module. 2 MSTP10 1 1: Stops clock supply to the SSU module. 1 to 0 11 Reserved SH7080 Group Registers for Setting the Serial Communication Interface-1 (SCI_1) Serial Control Register (SCSCR) This register enables or disables transmit and receive operations and interrupt requests, and selects the clock source for transmit and receive operations. Setting value: H'30 Bit Bit Name Setting Value Function 7 TIE 1 0: Disables transmit-fifo-data-empty interrupt (TXIF) requests. 1: Enables transmit-fifo-data-empty interrupt (TXIF) requests. 6 RIE 0 0: Disables receive-data-full interrupt (RXIF) requests, reception error interrupt (ERIF) requests and break interrupt (BRIF) requests. 5 TE 1 0: Disables transmit operations. 1: Enables transmit operations. 4 RE 0 0: Disables receive operations. 3 REIE 0 0: Disables receive error interrupt (ERIF) requests and break interrupt (BRIF) requests. 2 0 Reserved 1 to 0 CKE[1:0] 00 00: The internal clock/sck pin functions as an input pin (the input signal is ignored). REJ06B /Rev.1.00 September 2006 Page 12 of 28

13 Serial Mode Register (SCSMR) This register sets the communication format and selects the clock source of the baud rate generator. Setting value: H'00 Setting Bit Bit Name Value Function 7 C/A 0 0: Asynchronous mode 6 CHR 0 0: 8-bit data 5 PE 0 0: Disables parity bit addition and checking. 4 O/E 0 0: The O/E bit is invalid because PE = 0. 3 STOP 0 0: 1 stop bit 2 0 Reserved 1 to 0 CKS[1:0] 00 00: Pφ clock Bit Rate Register (SCBRR) This register specifies the bit rate for serial transmission and reception. Setting value: 129 Bit Bit Name Setting Value 7 to Function Bit rate for serial transmission/reception Registers for Setting the Pin Function Controller (PFC) Port A I/O register L (PAIORL) This register selects the input directions of the pins in port A. Setting value: H'0010 Bit Bit Name Setting Value Function 15 PA15IOR 0 0: PA15 input 14 PA14IOR 0 0: PA14 input 13 PA13IOR 0 0: PA13 input 12 PA12IOR 0 0: PA12 input 11 PA11IOR 0 0: PA11 input 10 PA10IOR 0 0: PA10 input 9 PA9IOR 0 0: PA9 input 8 PA8IOR 0 0: PA8 input 7 PA7IOR 0 0: PA7 input 6 PA6IOR 0 0: PA6 input 5 PA5IOR 0 0: PA5 input 4 PA4IOR 1 0: PA4 output. TXD1 output pin 3 PA3IOR 0 0: PA3 input. RXD1 input pin 2 PA2IOR 0 0: PA2 input 1 PA1IOR 0 0: PA1 input 0 PA0IOR 0 0: PA0 input REJ06B /Rev.1.00 September 2006 Page 13 of 28

14 Port A Control Register L2 (PACRL2) This register selects the functions of multiplexed pins in port A. Setting value: H'0001 Bit Bit Name Setting Value Function 15 0 Reserved 14 to 12 PA7MD[2:0] : PA7 input/output (port) 11 0 Reserved 10 to 8 PA6MD[2:0] : PA6 input/output (port) 7 0 Reserved 6 to 4 PA5MD[2:0] : PA6 input/output (port) 3 0 Reserved 2 to 0 PA4MD[2:0] : TXD1 output (SCI) SH7080 Group Port A Control Register L1 (PACRL1) This register selects the functions of multiplexed pins in port A. Setting value: H'1000 Bit Bit Name Setting Value Function 15 0 Reserved 14 to 12 PA3MD[2:0] : RXD1 input (SCI) 11 0 Reserved 10 to 8 PA2MD[2:0] : PA2 input/output (port) 7 0 Reserved 6 to 4 PA1MD[2-0] : PA1 input/output (port) 3 0 Reserved 2 to 0 PA0MD[2:0] : PA0 input/output (port) REJ06B /Rev.1.00 September 2006 Page 14 of 28

15 6. Flowcharts 6.1 Main Routine main( ) Set the Frequency Control Register (FRQCR) Initialize the UART Set the operating frequencies. When the external input clock frequency is 10 MHz: Internal (Iφ) = 80 MHz, bus (Bφ) = 40 MHz, peripheral (Pφ) = 40 MHz, MTU2S (MIφ) = 80 MHz, MTU2 (MPφ) = 40 MHz Initialize SCI channel 1. User application program processing There is no processing in this sample program. Receive data presence check processing Check whether the receive data is stored in SCRDR. Receive data exist? Receive data reading processing Store the receive data in a variable. Command received? Flash erasing/programming request command (Command name: CMD_GO) Flash read request command (Command name: CMD_READ) Flash reading processing Flash erasing/ programming processing After copying the procedure program into the RAM, execute the procedure program in the RAM. REJ06B /Rev.1.00 September 2006 Page 15 of 28

16 6.2 SCI Channel 1 Initialization Routine com_init( ) Set the Standby Control Register 3 (STBCR3) Cancel the standby state of SCI_1. Set the Serial Control Register (SCSCR) Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits in SCSCR to 0. Set the Internal clock/sck pin as an input pin. Set the Serial Mode Register (SCSMR) 8-bit data, no parity, and 1 stop bit. Set the Bit Rate Register (SCBRR) Bit rate = 9600 bps at 40 MHz (Pφ) Has a 1-bit period elapsed? Wait for at least a 1-bit period (104 µs). Set Port A I/O Register L (PAIOR) PA4 (TXD1) output pin Set Port A Control Register L2 (PACRL2) TXD1 output Set Port A Control Register L1 (PACRL1) RXD1 input Set the Serial Control Register (SCSCR) Enable receive operation. Enable transmit operation. END REJ06B /Rev.1.00 September 2006 Page 16 of 28

17 6.3 SCI_1 Receive Data Presence Check Routine SH7080 Group CheckRcv( ) Read the Serial Status Register (SCSSR) Set the contents of SCSSR in a variable. Reception error? Set the Serial Status Register (SCSSR) Parity error (PER) Framing error (FER) Overrun error (ORER) Clear the ORER, PER and FER flags of SCSSR to 0. Receive data present? If the RDRF flag of SCSSR is 1, received data has been stored in the Receive Data Register (SCRDR). Return the RDRF flag value to the return value. END REJ06B /Rev.1.00 September 2006 Page 17 of 28

18 6.4 SCI_1 n-byte Reception Routine rcvnbyte( ) Reading of the number of requested bytes completed? END Read the Serial Status Register (SCSSR) Set the contents of SCSSR in a variable. Reception error? Receive data present? Set the Serial Status Register (SCSSR) Parity error (PER) Framing error(fer) Overrun error(orer) Clear the ORER, PER and FER flags of SCSSR to 0. If RDRF of SCSSR is 1, the received data is stored in the Receive Data Register (SCRDR). Set the receive data in a variable Set the Serial Status Register (SCSSR) Clear the RDRF flag of SCSSR to 0. Decrement the number of requested bytes REJ06B /Rev.1.00 September 2006 Page 18 of 28

19 6.5 SCI_1 1-Byte Transmission Routine trs1byte( ) Data programming enabled? Determined by the TDRE flag of SCSSR. Write the transmit data Write 1 byte to SCTDR. Read the Serial Status Register (SCSSR) Clear the TDRE flag of SCSSR to 0. Transmission completed? Determined by the TEND flag of SCSSR. END REJ06B /Rev.1.00 September 2006 Page 19 of 28

20 6.6 Flash Programming Main Routine FlashMain( ) Flash write enabled? Error processing (NG command transmission) The FWE signal is not at a high level and the user MAT is not selected. Downloading of erasing program and execution of erasing initialization program Error? Error processing (NG command transmission) Downloading of the erasing program and initialization failed. Preparation for programming/ erasing Downloading of programming program and execution of programming initialization program. Error? Error processing (NG command transmission) Downloading of the programming program and initialization failed. OK command processing Erase command receive processing Receive command is? Command other than the erase command Erase command Error processing (NG command transmission) Erase block receive processing Absence of erase block? Error processing (NG command transmission) Erasing Erasing processing Erasing error? Error processing (NG command transmission) OK command processing 1 REJ06B /Rev.1.00 September 2006 Page 20 of 28

21 1 1-byte reception processing Write end command Command is? Command other than the write command Write command Error processing (NG command transmission) Programming start address receive processing Programming size receive processing Programming address or programming size error? Transmit request command transmit processing Error processing (NG command transmission) Determine the receive size Program data receive processing Programming Pad H'FF if less than 128 bytes Flash programming processing Programming error? Error processing (NG command transmission) Update the programming address and programming size Programming of specified size completed? OK command processing OK command processing Wait for a reset. REJ06B /Rev.1.00 September 2006 Page 21 of 28

22 6.7 Flash Reading Routine FlashRead( ) Read start address receive processing Read size receive processing Obtain the start address for reading using the rcvnbyte function (SCI_1 n-byte reception). Obtain the size for reading using the rcvnbyte function (SCI_1 n-byte reception). 1-byte transmission of data in flash memory Serial data transmission by the trs1byte function (SCI_1 1-byte transmission), 1 byte at a time from the read start address up to the read size Completed transmission of data in flash memory? END REJ06B /Rev.1.00 September 2006 Page 22 of 28

23 6.8 Erasing Program Downloading and initialization Routine SH7080 Group SetupFlashErase( ) Set the Flash Erase Code Select Register (FECS) Select the internal erasing program Set the Flash Transfer Destination Address Register (FTDAR) Download start address: H'FFFF9000 Clear the DPFR parameter value. Set the Flash Key Code Register (FKEY) Enable writing to the SCO bit. Set the Flash Code Control and Status Register (FCCS) After clearing the VBR register, set SCO to 1 and execute downloading. NOP x 4 Set the Flash Key Code Register (FKEY) Clear the FKEY register. Download successful? Set the operating frequency Erasing initialization processing Set the operating frequency to the FPEFEQ parameter value. 80 MHz (80*100) Set the error state (download error) END REJ06B /Rev.1.00 September 2006 Page 23 of 28

24 6.9 Flash Erasing Routine FlashErase( ) Set the Flash Key Code Register (FKEY) Enable programming/erasing. Erase block present? Erase block? Erasing processing Erasing error? Increment the erase block number Set the Flash Key Code Register (FKEY) Clear the FKEY register. END REJ06B /Rev.1.00 September 2006 Page 24 of 28

25 6.10 Programming Program Download and Initialization Routine SetupFlashWrite() Set the Flash Erase Code Select Register (FECS) Select the internal programming program Set the Flash Transfer Destination Address Register (FTDAR) Download start address: H'FFFFA000 Clear the DPFR parameter value. Set the Flash Key Code Register (FKEY) Enable writing to the SCO bit. Set the Flash Code Control and Status Register (FCCS) After clearing the VBR register, set SCO to 1 and execute downloading. NOP x 4 Set the Flash Key Code Register (FKEY) Clear the FKEY register. Download successful? Set the operating frequency Set the operating frequency to the FPEFEQ parameter value. 80 MHz (80*100) Programming initialization processing Set the error state (download error) END REJ06B /Rev.1.00 September 2006 Page 25 of 28

26 6.11 Flash Programming Routine FlashWrite( ) Set the Flash Key Code Register (FKEY) Enabling programming/erasing. Set FMPAR (flash multipurpose address area parameter) Set the start address of the programming destination in the user mat. Set FMPDR (flash multipurpose data destination area parameter) Set the start address of the area that stores the program data. Programming processing Set the Flash Key Code Register (FKEY) Clear the FKEY register. END REJ06B /Rev.1.00 September 2006 Page 26 of 28

27 Website and Support Renesas Technology Website Inquiries Revision Record Description Rev. Date Page Summary 1.00 Sep First edition issued REJ06B /Rev.1.00 September 2006 Page 27 of 28

28 Keep safety first in your circuit designs! SH7080 Group 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. tes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page ( 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein Renesas Technology Corp., All rights reserved. REJ06B /Rev.1.00 September 2006 Page 28 of 28