MMC power. NAND Flash power

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1 Features e MMC Memory MTFC4GGQDM, MTFC4GGQDI, MTFC8GKQDI, MTFC16GKQDI, MTFC32GKQDH Features MultiMediaCard (MMC) controller and NAND Flash 153-ball FBGA or 169-ball FBGA (6/6 RoHS-compliant) V CC : V V CCQ (dual voltage): V, V Storage temperature range: 40 C to +85 C Typical current consumption Standby current: 70µA (4GB, 8GB); 90µA (16GB); 130µA (32GB) Active current (RMS): 70mA (4GB, 8GB); 90mA (16GB, 32GB) MMC-Specific Features JEDEC/MMC standard version 4.41-compliant (JEDEC Standard No. 84-A441) SPI mode, highpriority interrupt (HPI), background operation, enhanced reliable WRITE, and double data rate (DDR) function not supported Advanced 11-signal interface x1, x4, and x8 I/Os, selectable by host MMC mode operation Command classes: class 0 (basic); class 2 (block read); class 4 (block write); class 5 (erase); class 6 (write protection); class 7 (lock card) MMCplus and MMCmobile protocols Temporary write protection 52 MHz clock speed (MAX) Boot operation (high-speed boot) Sleep mode Reliable WRITE Replay-protected memory block (RPMB) Secure erase and trim Hardware reset signal Multiple partitions with enhanced attribute Permanent and power-on write protection Backward-compatible with previous MMC modes ECC and block management implemented Deviations from the JEDEC specification are described in the last section of this data sheet. Figure 1: Micron e MMC Device MMC power NAND Flash power MMC controller NAND Flash MMC interface Options Density: 4GB, 8GB, 16GB, 32GB Temperature range Industrial temperature: 40 C to +85 C IT emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 1 Products and specifications discussed herein are subject to change by Micron without notice.

2 Features Part Numbering Information Micron e MMC memory devices are available in different configurations and densities. Figure 2: e MMC Part Numbering MT FC xx x x xx - xx Micron Technology Product Family FC = NAND Flash + controller NAND Flash Density NAND Flash Component Production Status Operating Temperature Range Package Codes Reserved Blank Controller Revision Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, Product Mark/ Label, at Valid Part Number Combinations Verify valid part numbers by using Micron s part catalog search at To compare features and specifications by device type, visit Contact the factory for devices not found. emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 2

3 Contents General Description Signal Descriptions Ball Signal Assignments Ball Signal Assignments Ball DM Package Dimensions Ball DH Package Dimensions Ball DI Package Dimensions Architecture MMC Protocol Independent of NAND Flash Technology Defect and Error Management MMC Controller Registers OC Register CID Register CID Register Fields MID Field (bits[127:120]) CBX Field (bits[113:112]) OID Field (bits[111:104]) PNM Field (bits[103:56]) PRV Field (bits[55:48]) PSN Field (bits[47:16]) MDT Field (bits[15:8]) CRC Field (bits[7:1]) CSD Register (MLC e MMC) CSD Register Fields CSD_STRUCTURE Field (bits[127:126]) SPEC_VERS Field (bits[125:122]) TAAC Field (bits[119:112]) NSAC Field (bits[111:104]) TRAN_SPEED Field (bits[103:96]) CCC Field (bits[95:84]) READ_BL_LEN Field (bits[83:80]) READ_BL_PARTIAL Field (bit 79) WRITE_BLK_MISALIGN Field (bit 78) READ_BLK_MISALIGN Field (bit 77) DSR_IMP Field (bit 76) C_SIZE Field (bits[73:62]) VDD_R_CURR_MIN Field (bits[61:59]), VDD_W_CURR_MIN Field (bits[55:53]) VDD_R_CURR_MAX Field (bits[58:56]), VDD_W_CURR_MAX Field (bits[52:50]) C_SIZE_MULT Field (bits[49:47]) ERASE_GRP_SIZE Field (bits[46:42]) ERASE_GRP_MULT Field (bits[41:37]) WP_GRP_SIZE Field (bits[36:32]) WP_GRP_ENABLE Field (bit 31) DEFAULT_ECC Field (bits[30:29]) R2W_FACTOR Field (bits[28:26]) WRITE_BL_LEN Field (bits[25:22]) WRITE_BL_PARTIAL Field (bit 21) CONTENT_PROT_APP Field (bit 16) FILE_FORMAT_GRP Field (bit 15) COPY Field (bit 14) emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 3

4 PERM_WRITE_PROTECT Field (bit 13) TMP_WRITE_PROTECT Field (bit 12) FILE_FORMAT Field (bits[11:10]) ECC Field (bits[9:8]) CRC Field (bits[7:1]) ECSD Register (MLC e MMC) ECSD Register Fields Properties Segment S_CMD_SET Field (byte 504) HPI_FEATURES Field (byte 503) BKOPS_SUPPORT Field (byte 502) BKOPS_STATUS Field (byte 246) CORRECTLY_PRG_SECTORS_NUM Field ([245:242]) INI_TIMEOUT_PA Field (byte 241) TRIM_MULT Field (byte 232) SEC_FEATURE_SUPPORT Field (byte 231) SEC_ERASE_MULT Field (byte 230) SEC_TRIM_MULT Field (byte 229) BOOT_INFO Field (byte 228) BOOT_SIZE_MULT Field (byte 226) ACC_SIZE Field (byte 225) HC_ERASE_GRP_SIZE Field (byte 224) ERASE_TIMEOUT_MULT Field (byte 223) REL_WR_SEC_C Field (byte 222) HC_WP_GRP_SIZE Field (byte 221) S_C_VCC Field (byte 220), S_C_VCCQ Field (byte 219) S_A_TIMEOUT Field (byte 217) SEC_COUNT Field ([215:212]) MIN_PERF_DDR_R/W_b_ff Fields ([235:234]), MIN_PERF_R/W_b_ff Fields ([210:205]) Device Performance Measurement PWR_CL_DDR_ff_vvv Fields ([239:238]), PWR_CL_ff_vvv Fields ([203:200]) PARTITION_SWITCH_TIME Field (byte 199) OUT_OF_INTERRUPT_TIME Field (byte 198) CARD_TYPE Field (byte 196) CSD_STRUCTURE Field (byte 194) EXT_CSD_REV Field (byte 192) ECSD Register Fields Modes Segment CMD_SET Field (byte 191) CMD_SET_REV Field (byte 189) POWER_CLASS Field (byte 187) HS_TIMING Field (byte 185) BUS_WIDTH Field (byte 183) ERASED_MEM_CONT Field (byte 181) PARTITION_CONFIG Field (byte 179) BOOT_CONFIG_PROT Field (byte 178) BOOT_BUS_WIDTH Field (byte 177) ERASE_GROUP_DEF Field (byte 175) BOOT_WP Field (byte 173) USER_WP Field (byte 171) FW_CONFIG Field (byte 169) RPMB_SIZE_MULT Field (byte 168) WR_REL_SET Field (byte 167) WR_REL_PARAM Field (byte 166) emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 4

5 BKOPS_START Field (byte 164) BKOPS_EN Field (byte 163) RST_n_FUTION Field (byte 162) HPI_MGMT Field (byte 161) PARTITIONING_SUPPORT Field (byte 160) MAX_ENH_SIZE_MULT Field ([159:157]) PARTITIONS_ATTRIBUTE Field (byte 156) PARTITION_SETTING_COMPLETED Field (byte 155) GP_SIZE_MULT Field ([154:143]) ENH_SIZE_MULT Field ([142:140]) ENH_START_ADDR Field ([139:136]) SEC_BAD_BLK_MGMNT Field (byte 134) RCA Register DS Register Bus Protocol Message Types Bus Protocol Command Token Command Types Command Classes Command Descriptions Bus Protocol Response Token R1 Response Token R1b Response Token R2 Response Token R3 Response Token Bus Protocol Data Packet Bus Protocol CRC CRC CRC Bus Protocol CRC Status Token CRC Status Token Bus Protocol Clock Control Host Restrictions Bus Transactions Bus Protocol Bus Error Conditions COM_CRC_ERROR Bit ILLEGAL_COMMAND Error Bit ADDRESS_OUT_OF_RANGE Error MMC Mode Bus Operations NO RESPONSE Operation NO DATA Operation Without a Busy Indicator NO DATA Operation With a Busy Indicator DATA TRANSFER Operation Partition Management Memory Partition Organization Partition Command Restrictions Configuring Partitions Accessing Partitions Operating Modes Boot Mode Device Reset to Pre-Idle State Boot Partitions Boot Mode Operation emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 5

6 Alternative Boot Mode Operation Accessing Boot Partitions Boot Bus Width and Access Configuration Boot Partition Write Protection Card Identification Mode Device Reset Idle State to Ready State Ready State to Identification State Identification State to Standby State Data Transfer Mode Overview Data Transfer Mode Command Sets and Extended Settings High-Speed Mode Selection Power Class Selection Bus Width Selection Bus Testing Procedure Data Transfer Mode Data READ Operation Block Read Data Transfer Mode Data WRITE Operation Block Write Data Transfer Mode ERASE Operation Data Transfer Mode SECURE ERASE Operation Data Transfer Mode TRIM Operation Data Transfer Mode SECURE TRIM Operation Data Transfer Mode Write-Protect Management Data Transfer Mode LOCK/UNLOCK Operations LOCK/UNLOCK Command Sequences Data Transfer Mode SLEEP/AWAKE Operations Data Transfer Mode RPMB RPMB Access Data Frame RPMB Memory Map MAC Calculation for RPMB Accesses to the RPMB Data Transfer Mode Background Operation Data Transfer Mode High-Priority Interrupt Data Transfer Mode R/W Blocks, Erase Groups, and WPGs Inactive Mode DC Electrical Specifications Bus (MLC e MMC) Bus Topology Bus Operating Conditions Bus Signal Line Load Bus Signal Levels DC Electrical Specifications Device Power (MLC e MMC) DC Electrical Specifications Power-On Sequence DC Electrical Specifications RST_n Signal During Power-On Period DC Electrical Specifications Power Cycling AC Electrical Specifications Timeout Conditions Bus and Device Interface Timing Command Timing Symbols and Definitions BOOT Operation Timing Command/Response Timing SEND_OP_COND (CMD1) and ALL_SEND_CID (CMD2) Timing emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 6

7 SET_RCA (CMD3) Timing Data Transfer Mode Timing R1b Response Timing Last Device Response to Next Host Command Timing Last Host Command to Next Host Command Timing Data Read Timing READ_SINGLE_BLOCK (CMD17) Timing READ_MULTIPLE_BLOCK (CMD18) Timing Data Write Timing WRITE_BLOCK (CMD24) Timing WRITE_MULTIPLE_BLOCK (CMD25) Timing STOP_TRANSMISSION (CMD12) Timing ERASE (CMD38), SET_WRITE_PROT (CMD28), CLR_WRITE_PROT (CMD29) Timing Reselecting a Busy Device BUSTEST_W (CMD19) and BUSTEST_R (CMD14) Timing Hardware Reset Timing Hardware Reset Waveform Hardware Reset Noise Filtering Timing Optional Features Not Supported by the Device Device Deviations From JEDEC v4.41 Specification (Errata) Bus Test (CMD14/CMD19) at Low Frequency (<400 khz) Power Cycle Required for RST_n Signal Enabled Cell Type of ERASE_GROUP_DEF No Erase Commands Supported in Boot Partitions Limit to the Number of Step 1s in a SECURE TRIM Command Sequence (511 Max) RST_n Signal ECSD Values for Bytes[159:157] in ECSD Register (MLC e MMC) Boot Acknowledge Time (for MTFC8GKQxx and MTFC4GGQxx) CMD Line Kept LOW for BOOT Operation After Hardware Reset (RST_n) Asserted BUS_WIDTH and HS_TIMING Bits Not Reset by CMD CMD24 Interrupted by CMD Issuing ERASE Command to RPMB Partition Prohibited SEC_BAD_BLK_MGMT (ECSD[134]) Not Supported Revision History Rev. C, Production 7/ Rev. B, Production 6/ Rev. A, Production 4/ emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 7

8 List of Tables Table 1: Signal Descriptions Table 2: OC Register Settings Table 3: CID Register Field Parameters Table 4: CBX Field Device Types Table 5: CSD Register Field Parameters (MLC e MMC) Table 6: CSD_STRUCTURE Field Values Table 7: SPEC_VERS Field Values Table 8: TAAC Field Bit Position Codes Table 9: TRAN_SPEED Field Bit Position Codes Table 10: CCC Field Bit Codes Table 11: READ_BL_LEN Field Block Length Codes Table 12: DSR_IMP Field Codes Table 13: VDD_R_CURR_MIN, VDD_W_CURR_MIN Field Values Table 14: VDD_R_CURR_MAX, VDD_W_CURR_MAX Field Values Table 15: C_SIZE_MULT Field Values Table 16: R2W_FACTOR Field Values Table 17: FILE_FORMAT Field Definitions Table 18: ECC Field Formats Table 19: ECSD Register Field Parameters (MLC e MMC) Table 20: S_CMD_SET Field Values Table 21: HPI_FEATURES Field Byte Format Table 22: HPI_FEATURES Field Bit Descriptions Table 23: BKOPS_SUPPORT Field Byte Format Table 24: BKOPS_SUPPORT Field Bit Descriptions Table 25: BKOPS_STATUS Field Byte Format Table 26: BKOPS_STATUS Field Bit Descriptions Table 27: Number of Sectors Correctly Programmed Table 28: INI_TIMEOUT_PA Field Initialization Maximum Timeout Values Table 29: TRIM_MULT Field TRIM Timeout Values Table 30: SEC_FEATURE_SUPPORT Field Byte Format Table 31: SEC_FEATURE_SUPPORT Field Bit Descriptions Table 32: SEC_ERASE_MULT Field SECURE ERASE Timeout Values Table 33: SEC_TRIM_MULT Field SECURE TRIM Timeout Values Table 34: BOOT_INFO Field Byte Format Table 35: BOOT_INFO Field Bit Descriptions Table 36: BOOT_SIZE_MULT Field Boot Partition Size Values Table 37: ACC_SIZE Field Byte Format Table 38: ACC_SIZE Field SUPER_PAGE_SIZE Values Table 39: HC_ERASE_GRP_SIZE Field Erase Unit Size Values Table 40: ERASE_TIMEOUT_MULT Field Erase Timeout Values Table 41: HC_WP_GRP_SIZE Field Write Protect Group Size Table 42: S_C_VCC and S_C_VCCQ Field Values Table 43: S_A_TIMEOUT Field Values Table 44: Read/Write (R/W) Access Performance Values Table 45: Supported Power Classes Table 46: PARTITION_SWITCH Timeout Values Table 47: OUT_OF_INTERRUPT_TIME Timeout Values Table 48: CARD_TYPE Field Definitions Table 49: CSD_STRUCTURE Field Descriptions Table 50: EXT_CSD_REV Field Descriptions emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 8

9 Table 51: CMD_SET_REV Field Values Table 52: POWER_CLASS Field Descriptions Table 53: BUS_WIDTH Field Values Table 54: ERASED_MEM_CONT Field Values Table 55: PARTITION_CONFIG Field Byte Format Table 56: PARTITION_CONFIG Field Bit Descriptions Table 57: BOOT_CONFIG_PROT Field Byte Format Table 58: BOOT_CONFIG_PROT Field Bit Descriptions Table 59: BOOT_BUS_WIDTH Field Byte Format Table 60: BOOT_BUS_WIDTH Field Bit Descriptions Table 61: ERASE_GROUP_DEF Field Byte Format Table 62: ERASE_GROUP_DEF Field Bit Descriptions Table 63: BOOT_WP Field Byte Format Table 64: BOOT_WP Field Bit Descriptions Table 65: USER_WP Field Byte Format Table 66: USER_WP Field Bit Descriptions Table 67: FW_CONFIG Field Byte Format Table 68: FW_CONFIG Field Bit Descriptions Table 69: RPMB_SIZE_MULT Field Values and Descriptions Table 70: WR_REL_SET Field Bit Types Table 71: WR_REL_SET Field Bit Descriptions Table 72: WR_REL_PARAM Field Bit Types Table 73: WR_REL_PARAM Field Bit Descriptions Table 74: BKOPS_EN Field Byte Format Table 75: BKOPS_EN Field Bit Descriptions Table 76: RST_n_FUTION Field Byte Format Table 77: RST_n_FUTION Field Bit Descriptions Table 78: HPI_MGMT Field Byte Format Table 79: HPI_MGMT Field Bit Descriptions Table 80: PARTITIONING_SUPPORT Field Byte Format Table 81: PARTITIONING_SUPPORT Field Bit Descriptions Table 82: MAX_ENH_SIZE_MULT Field Byte Format Table 83: PARTITIONS_ATTRIBUTE Field Byte Format Table 84: PARTITIONS_ATTRIBUTE Field Bit Descriptions Table 85: PARTITION_SETTING_COMPLETED Field Byte Format Table 86: GP_SIZE_MULT Field Byte Format Table 87: GP_SIZE_MULT Field Byte Descriptions Table 88: ENH_SIZE_MULT Field Byte Format Table 89: ENH_START_ADDR Field Byte Format Table 90: SEC_BAD_BLK_MGMNT Field Byte Format Table 91: SEC_BAD_BLK_MGMNT Field Bit Descriptions Table 92: Command Token Format Table 93: Command Types Table 94: Basic Commands (class 0) Table 95: Block-Oriented Read Commands (class 2) Table 96: Block-Oriented Write Commands (class 4) Table 97: Erase Commands (class 5) Table 98: Block-Oriented Write Protection Commands (class 6) Table 99: Lock Card (class 7) Table 100: Device State Transitions by Command Table 101: R1/R1b Response Token Format Table 102: R1/R1b Card Status Field emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 9

10 Table 103: R2 Response Token Format Table 104: R3 Response Token Format Table 105: Operating Modes, Bus Modes, and Device States Table 106: ECSD Register Access Modes Table 107: Example of Host Command Token to Enable High-Speed Timing on the Bus Table 108: Example of Host Command Token to Switch from 1-Bit to 8-Bit I/O Operation Table 109: Bus Testing Pattern Table 110: 1-Bit Bus Testing Pattern Table 111: 4-Bit Bus Testing Pattern Table 112: 8-Bit Bus Testing Pattern Table 113: ERASE Command Valid Arguments Table 114: ERASE Command Comparison Table 115: ERASE Command Argument Definitions Table 116: Write Protection Hierarchy (disable bits cleared) Table 117: Write Protection Types (disable bits cleared) Table 118: LOCK/UNLOCK Data Structure Table 119: LOCK/UNLOCK Data Descriptions Table 120: RPMB Access Data Frame Table 121: RPMB Access Data Frame Field Descriptions Table 122: RPMB Operation Result Field Data Structure Table 123: RPMB Operation Result Field Defined Results Table 124: RPMB Request/Response Message Types Table 125: RPMB Memory Map Table 126: MAC Request Frames Table 127: Authentication Key Information Data Packet Table 128: Authentication Key Request Type Information Data Packet Table 129: Authentication Key Result Information Data Packet Table 130: Counter Read Request Type Information Data Packet Table 131: Counter Value Read Data Packet Table 132: Authenticated Data Write Data Packet Table 133: Authenticated Data Write Request Type Information Data Packet Table 134: Authenticated Data Write Result Information Data Packet Table 135: Authenticated Data Read Request Type Information Data Packet Table 136: Authenticated Data Read Information Data Packet Table 137: Interruptible Commands Table 138: Host and Bus Resistance Values (MLC e MMC) Table 139: Bus Operating Conditions (MLC e MMC) Table 140: Open-Drain Mode Bus Signal Levels (MLC e MMC) Table 141: Push-Pull Mode Bus Signal Levels (MLC e MMC, V CCQ = V) Table 142: Push-Pull Mode Bus Signal Levels (MLC e MMC, V CCQ = V) Table 143: Absolute Maximum Ratings (MLC e MMC) Table 144: Device Power Supply Voltages (MLC e MMC) Table 145: Timing Values Table 146: Command Set Timing Parameters and Example Equation Table 147: Hardware Reset Timing Parameters Table 148: Interface Timing (high-speed interface) Table 149: Interface Timing (standard interface) Table 150: Command Timing Symbols and Definitions emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 10

11 List of Figures Figure 1: Micron e MMC Device... 1 Figure 2: e MMC Part Numbering... 2 Figure 3: 153-Ball FBGA (top view, ball down) Figure 4: 169-Ball FBGA (top view, ball down) Figure 5: 153-Ball FBGA (package code DM) Figure 6: 169-Ball FBGA (package code DH) Figure 7: 169-Ball FBGA (package code DI) Figure 8: e MMC Functional Block Diagram Figure 9: Typical Bus Protocol Figure 10: Command Token Format Figure 11: Response Token Format Figure 12: Data Packet Transfer Figure 13: Data Packet Format: 1-Bit Bus (only DAT0 used) Figure 14: Data Packet Format: 4-Bit Bus (DAT[3:0] used) Figure 15: Data Packet Format: 8-Bit Bus (DAT[7:0] used) Figure 16: CRC7 Generator/Checker Figure 17: CRC16 Generator/Checker Figure 18: CRC Status Figure 19: MMC Mode NO RESPONSE Operation Figure 20: MMC Mode NO DATA Operation Without a Busy Indicator Figure 21: MMC Mode NO DATA Operation With a Busy Indicator Figure 22: MMC Mode Multiple-Block Read Operation Figure 23: MMC Mode Multiple-Block Write Operation Figure 24: e MMC Memory Partitions Prior to PARTITION Operation Figure 25: Example of Partitions and User Data Area Configuration Figure 26: General-Purpose and Enhanced User Data Area Parameter-Setting Flow Chart Figure 27: Write Protect Condition Transition Due to Assertion of RST_n Signal Figure 28: Boot Partitions Figure 29: Boot Mode Operation Timing Figure 30: Alternative Boot Mode Timing Figure 31: Boot Mode State Diagram Figure 32: Card Identification Mode State Diagram Figure 33: Data Transfer Mode State Diagram Figure 34: Relationships Between Write Blocks, Erase Groups, and WPGs Figure 35: Bus Circuitry Diagram (MLC e MMC) Figure 36: Bus Signal Levels (MLC e MMC) Figure 37: Device Power Diagram (MLC e MMC) Figure 38: Power-On Sequence Figure 39: RST_n Signal During Power-On Period Figure 40: Power Cycle Figure 41: Bus and Device Interface Timing Figure 42: BOOT Operation Timing with Termination Between Consecutive Data Blocks Figure 43: BOOT Operation Timing with Termination During Transfer Figure 44: Alternative BOOT Operation Timing with Termination Between Consecutive Data Blocks Figure 45: Alternative BOOT Operation Timing with Termination During Transfer Figure 46: Bus Mode Change Timing (push-pull to open drain) Figure 47: SEND_OP_COND (CMD1) and ALL_SEND_CID (CMD2) Timing Figure 48: SET_RCA (CMD3) Timing Figure 49: Data Transfer Mode Timing Figure 50: R1b Response Timing emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 11

12 Figure 51: Timing Response End to Next Command Start (data transfer mode) Figure 52: Command Sequences Timing (all modes) Figure 53: READ_SINGLE_BLOCK (CMD17) Timing Figure 54: READ_MULTIPLE_BLOCK (CMD18) Timing Figure 55: STOP_TRANSMISSION (CMD12) Timing Figure 56: WRITE_BLOCK (CMD24) Timing Figure 57: WRITE_MULTIPLE_BLOCK (CMD25) Timing Figure 58: STOP_TRANSMISSION (CMD12) Timing During Data Transfer From the Host Figure 59: STOP_TRANSMISSION (CMD12) Timing During CRC Status Transmission to the Host Figure 60: STOP_TRANSMISSION (CMD12) Timing After Last Data Block While Device is Programming Figure 61: STOP_TRANSMISSION (CMD12) Timing After Last Data Block When Device is Idle Figure 62: BUSTEST_W (CMD19) and BUSTEST_R (CMD14) Timing (example of 4-bit bus test) Figure 63: Hardware Reset Waveform Figure 64: Hardware Reset Noise Filtering Timing Figure 65: Scenario 1: e MMC Device Fails to Reset Figure 66: Scenario 2: e MMC Device Resets emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 12

13 General Description 4GB, 8GB, 16GB, 32GB: e MMC General Description Micron e MMC is a communication and mass data storage device that includes a Multi- MediaCard (MMC) interface, a NAND Flash component, and a controller on an advanced 11-signal bus, which is compliant with the MMC system specification. Its low cost, small size, Flash technology independence, and high data throughput make e MMC ideal for smart phones, digital cameras, PDAs, MP3 players, and other portable applications. The nonvolatile e MMC draws no power to maintain stored data, delivers high performance across a wide range of operating temperatures, and resists shock and vibration disruption. emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 13

14 Signal Descriptions Signal Descriptions Table 1: Signal Descriptions Symbol Type Description CLK Input Clock: Each cycle of the clock directs a transfer on the command line and on the data line(s). The frequency can vary between the minimum and the maximum clock frequency. CMD I/O Command: This signal is a bidirectional command channel used for command and response transfers. The CMD signal has two bus modes: open-drain mode and push-pull mode (see Operating Modes). Commands are sent from the MMC host to the device, and responses are sent from the device to the host. DAT[7:0] I/O Data I/O: These are bidirectional data signals. The DAT signals operate in push-pull mode. By default, after power-on or assertion of the RST_n signal, only DAT0 is used for data transfer. The MMC controller can configure a wider data bus for data transfer either using DAT[3:0] (4-bit mode) or DAT[7:0] (8-bit mode). e MMC includes internal pull-up resistors for data lines DAT[7:1]. Immediately after entering the 4-bit mode, the device disconnects the internal pull-up resistors on the DAT[3:1] lines. Upon entering the 8-bit mode, the device disconnects the internal pull-ups on the DAT[7:1] lines. RST_n Input Reset: The RST_n signal is used by the host for resetting the device, moving the device to the preidle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it. V CC Supply V CC : NAND interface (I/F) I/O and NAND Flash power supply. V CCQ Supply V CCQ : e MMC controller core and e MMC I/F I/O power supply. V SS 1 Supply V SS : NAND I/F I/O and NAND Flash ground connection. V SSQ 1 Supply V SSQ : e MMC controller core and e MMC I/F ground connection. V DDI Internal voltage node: At least a 0.1μF capacitor is required to connect V DDI to ground. A 1μF capacitor is recommended. Do not tie to supply voltage or ground. No connect: No internal connection is present. RFU Reserved for future use: No internal connection is present. Leave it floating externally. Note: 1. V SS and V SSQ are connected internally. emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 14

15 153-Ball Signal Assignments 153-Ball Signal Assignments Figure 3: 153-Ball FBGA (top view, ball down) A DAT0 DAT1 DAT2 RFU RFU B DAT3 DAT4 DAT5 DAT6 DAT7 C V DDI V SSQ RFU V CCQ D E RFU V CC V SS RFU RFU RFU F V CC RFU G RFU V SS RFU H RFU V SS J RFU V CC K RST_n RFU RFU V SS V CC RFU L M V CCQ CMD CLK N V SSQ V CCQ V SSQ P V CCQ V SSQ V CCQ V SSQ RFU RFU Notes: 1. Some test pads on the device are not shown. They are not solder balls and are for Micron internal use only. 2. Some previous versions of the JEDEC product or mechanical specification had defined reserved for future use (RFU) balls as no connect () balls. balls assigned in the previous specifications could have been connected to ground on the system board. To enable new feature introduction, some of these balls are assigned as RFU in the v4.4 mechanical specification. Any new PCB footprint implementations should use the new ball assignments and leave the RFU balls floating on the system board. emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 15

16 169-Ball Signal Assignments 169-Ball Signal Assignments Figure 4: 169-Ball FBGA (top view, ball down) A B 1 C D E F G H DAT0 DAT1 DAT2 RFU RFU J DAT3 DAT4 DAT5 DAT6 DAT7 K V DDI V SSQ RFU V CCQ L M RFU V CC V SS RFU RFU RFU N V CC RFU P RFU V SS RFU R RFU V SS T RFU V CC U RST_n RFU RFU V SS V CC RFU V W V CCQ CMD CLK Y V SSQ V CCQ V SSQ AA V CCQ V SSQ V CCQ V SSQ RFU RFU AB AC AD AE AF AG AH Notes: 1. Empty balls do not denote actual solder balls; they are position indicators only. emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 16

17 169-Ball Signal Assignments 2. Some test pads on the device are not shown. They are not solder balls and are for Micron internal use only. 3. Some previous versions of the JEDEC product or mechanical specification had defined reserved for future use (RFU) balls as no connect () balls. balls assigned in the previous specifications could have been connected to ground on the system board. To enable new feature introduction, some of these balls are assigned as RFU in the v4.4 mechanical specification. Any new PCB footprint implementations should use the new ball assignments and leave the RFU balls floating on the system board. emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 17

18 153-Ball DM Package Dimensions 153-Ball DM Package Dimensions Figure 5: 153-Ball FBGA (package code DM) 0.91 ±0.1 Seating plane 0.08 A A 153X Ø0.3 Solder ball material: LF35. Dimensions apply to solder balls post-reflow on Ø0.27 SMD ball pads. Index Index 13 ± CTR A B C D E F G H J K L M N P 0.5 TYP Test pads 0.5 TYP 6.5 CTR 11.5 ± MAX 0.17 MIN Notes: 1. Dimensions are in millimeters. 2. Test pads are for Micron internal use only; these are not solder balls. emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 18

19 169-Ball DH Package Dimensions 169-Ball DH Package Dimensions Figure 6: 169-Ball FBGA (package code DH) Seating plane 0.08 A A 1.05 ± X Ø0.3 Solder ball material: LF35. Dimensions apply to solder balls post-reflow on Ø0.27 SMD ball pads CTR TYP A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH Ball A1 ID 18 ±0.1 Ball A1 ID 6.5 CTR 0.5 TYP 12 ± MAX 0.17 MIN Notes: 1. Dimensions are in millimeters. 2. Test pads are for Micron internal use only; these are not solder balls. emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 19

20 169-Ball DI Package Dimensions 169-Ball DI Package Dimensions Figure 7: 169-Ball FBGA (package code DI) Seating plane 0.08 A A 0.91 ± X Ø0.3 Solder ball material: LF35. Dimensions apply to solder balls post-reflow on Ø0.27 SMD ball pads Index Index 13.5 CTR TYP A B C D E F G H J K L M N P R 16 ±0.1 T U V W Y AA AB AC AD AE AF AG AH 36X Ø0.325 on pitch Ni/Au plated test pads 0.5 TYP 6.5 CTR 1.2 MAX 0.17 MIN 12 ±0.1 Notes: 1. Dimensions are in millimeters. 2. Test pads are for Micron internal use only; these are not solder balls. emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 20

21 Architecture Architecture Figure 8: e MMC Functional Block Diagram e MMC RST_n CMD CLK V DDI MMC controller Registers OCR CSD RCA CID ECSD DSR V CC V CCQ DAT[7:0] V 1 SS V 1 SSQ NAND Flash Note: 1. These are internally connected. MMC Protocol Independent of NAND Flash Technology The MMC specification defines the communication protocol between a host and a device. The protocol is independent of the NAND Flash features included in the device. The device has an intelligent on-board controller that manages the MMC communication protocol. The controller also handles block management functions such as logical block allocation and wear leveling. These management functions require complex algorithms and depend entirely on NAND Flash technology (generation or memory cell type). The device handles these management functions internally, making them invisible to the host processor. emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 21

22 Defect and Error Management MMC Controller Registers Micron e MMC incorporates advanced technology for defect and error management. If a defective block is identified, the device completely replaces the defective block with one of the spare blocks. This process is invisible to the host and does not affect data space allocated for the user. The device also includes a built-in error correction code (ECC) algorithm to ensure that data integrity is maintained. To make the best use of these advanced technologies and ensure proper data loading and storage over the life of the device, the host must exercise the following precautions: Check the status after WRITE, READ, and ERASE operations. Avoid power-down during WRITE and ERASE operations. 4GB, 8GB, 16GB, 32GB: e MMC Architecture The MMC controller includes six registers: the operating conditions (OC) register, the card identification (CID) register, the card-specific data (CSD) register, the extended cardspecific data (ECSD) register, the relative card address (RCA) register, and the driver stage (DS) register. These can be accessed only by corresponding commands. The OC, CID, and CSD registers carry the device- and content-specific information, while the DS and RCA registers are configuration registers used for storing actual configuration parameters. The ECSD register carries both device-specific information and actual configuration parameters. emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 22

23 OC Register OC Register The 32-bit operating conditions (OC) register always shows the fixed data (shown below). This does not reflect any e MMC voltage ranges. In addition, this register includes a status bit. This status bit is set if the device power-on sequence has completed. The OC register will be implemented in all e MMC devices. Table 2: OC Register Settings OC Bits Voltage Window OC Value [6:0] Reserved b V 1b [14:8] V b [23:15] V b [28:24] Reserved b [30:29] Access mode 00b (byte mode) 10b (sector mode) 31 Device power-on status bit (busy) 1 00b (1GB, 2GB) 10b (>2GB) Note: 1. Bit 31 is set to LOW if the device has not completed the power-on routine. emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 23

24 CID Register CID Register The card identification (CID) register is 128 bits wide. It contains the device identification information used during the card identification phase as required by e MMC protocol. Each device is created with a unique identification number. Table 3: CID Register Field Parameters Name Field Width CID Bits CID Value Manufacturer ID MID 8 [127:120] 0x13 Reserved 6 [119:114] Card/BGA CBX 2 [113:112] OEM/application ID OID 8 [111:104] Product name PNM 48 [103:56] Product revision PRV 8 [55:48] Product serial number PSN 32 [47:16] Manufacturing date MDT 8 [15:8] CRC7 checksum CRC 7 [7:1] Not used; always CID Register Fields MID Field (bits[127:120]) CBX Field (bits[113:112]) The MID field in the CID register is an 8-bit binary number that identifies the device manufacturer. The MID number is controlled, defined, and allocated to each device manufacturer by JEDEC. The CBX field in the CID register indicates the device type. Table 4: CBX Field Device Types CBX Bytes [113:112] Type 00 Card (removable) 01 BGA/MCP 10 PoP 11 Reserved Description OID Field (bits[111:104]) The OID field in the CID register is an 8-bit binary number that identifies the device OEM and the device contents when used as distribution media on ROM or NAND Flash devices. The OID number is controlled, defined, and allocated to a device manufacturer by JEDEC. emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 24

25 PNM Field (bits[103:56]) PRV Field (bits[55:48]) PSN Field (bits[47:16]) MDT Field (bits[15:8]) CRC Field (bits[7:1]) The PNM field in the CID register is the controller revision code string. The string is 6 ASCII characters long. Refer to the controller revision code in Part Numbering Information. The PRV field in the CID register is the product revision, which is composed of 2 binary coded decimal (BCD) digits, 4 bits each, representing an n.m revision number. The n is the most significant nibble, and m is the least significant nibble. For example, the PRV binary value field for product revision 6.2 is The PSN field in the CID register is a 32-bit unsigned binary integer. The MDT field in the CID register is the manufacturing date, which is composed of 2 hexadecimal digits, 4 bits each, representing a 2-digit date code m/y. The most significant nibble, the m field, is the month code (1 = January). The y field is the year code (0 = 1997). For example, the binary value of the MDT field for production date April 2000 is The CRC7 field in the CID register is a 7-bit checksum. 4GB, 8GB, 16GB, 32GB: e MMC CID Register Fields emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 25

26 CSD Register (MLC e MMC) The card-specific data (CSD) register provides information about accessing the device contents. The CSD register defines the data format, error correction type, maximum data access time, and data transfer speed, as well as whether the DS register can be used. The programmable part of the register (entries marked with W or E in the following table) can be changed by the PROGRAM_CSD (CMD27) command. Table 5: CSD Register Field Parameters (MLC e MMC) Name Field Width Cell Type 1 CSD Bits CSD Value Value Description CSD structure CSD_STRUCTURE 2 R [127:126] 2h CSD1.2 System specification version SPEC_VERS 4 R [125:122] 4h Version 4.41 Reserved 2 2 [121:120] Data read access time 1 TAAC 8 R [119:112] 2Fh 20ms Data read access time 2 in CLK cycles (NSAC 100) 4GB, 8GB, 16GB, 32GB: e MMC CSD Register (MLC e MMC) NSAC 8 R [111:104] 01h 100 Maximum bus clock frequency TRAN_SPEED 8 R [103:96] 32h 26 MHz Card command classes CCC 12 R [95:84] 0F5h 0, 2, 4, 5, 6, 7 Maximum read data block length READ_BL_LEN 4 R [83:80] 9h 512 Partial blocks for reads supported READ_BL_PARTIAL 1 R 79 0b No Write block misalignment WRITE_BLK_MISALIGN 1 R 78 0b No Read block misalignment READ_BLK_MISALIGN 1 R 77 0b No DS register implemented DSR_IMP 1 R 76 0b No Reserved 2 [75:74] Device size: C_SIZE 12 R [73:62] FFFh 4095 Maximum read current at V DD,min VDD_R_CURR_MIN 3 R [61:59] 6h 60mA Maximum read current at V DD,max VDD_R_CURR_MAX 3 R [58:56] 6h 80mA Maximum write current at V DD,min VDD_W_CURR_MIN 3 R [55:53] 6h 60mA Maximum write current at V DD,max VDD_W_CURR_MAX 3 R [52:50] 6h 80mA Device size multiplier C_SIZE_MULT 3 R [49:47] 7h 512 Erase group size ERASE_GRP_SIZE 5 R [46:42] 1Fh 32 Erase group size multiplier ERASE_GRP_MULT 5 R [41:37] 1Fh 32 Write protect group size WP_GRP_SIZE 5 R [36:32] 07h 8 Write protect group enable WP_GRP_ENABLE 1 R 31 1b Yes Manufacturer default ECC DEFAULT_ECC 2 R [30:29] 0h None Write-speed factor R2W_FACTOR 3 R [28:26] 4h 16 Maximum write data block length WRITE_BL_LEN 4 R [25:22] 9h 512 byte Partial blocks for writes supported WRITE_BL_PARTIAL 1 R 21 0b No Reserved 4 [20:17] Content protection application CONTENT_PROT_APP 1 R 16 0b Not supported File-format group FILE_FORMAT_GRP 1 R/W 15 0b HDD-like file system emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 26

27 CSD Register Fields Table 5: CSD Register Field Parameters (MLC e MMC) (Continued) Name Field Width Cell Type 1 CSD Bits CSD Value Value Description Copy flag (OTP) COPY 1 R/W 14 1b Copy Permanent write protection PERM_WRITE_PROTECT 1 R/W 13 0b No Temporary write protection TMP_WRITE_PROTECT 1 R/W/E 12 0b No File format FILE_FORMAT 2 R/W [11:10] 0h HDD-like file system ECC ECC 2 R/W/E [9:8] 0h None CRC CRC 7 R/W/E [7:1] Not used; always b 1 Notes: 1. R = Read-only R/W = One-time programmable and readable R/W/E = Multiple writable with value kept after a power cycle, assertion of the RST_n signal, and any CMD0 reset, and readable TBD = To be determined CSD Register Fields 2. Reserved bits should be read as 0. CSD_STRUCTURE Field (bits[127:126]) Field descriptions detail CSD fields and data types. All bit strings are interpreted as binarycoded numbers starting with the left bit first, unless stated otherwise. The CSD_STRUCTURE field in the CSD register describes the version of the CSD structure. Table 6: CSD_STRUCTURE Field Values CSD_STRUCTURE CSD Structure Version Valid for System Specification Version 0 CSD version 1.0 Versions CSD version 1.1 Versions CSD version 1.2 Versions 3.1, 3.2, 3.31, 4.0, 4.1, 4.2, 4.3, 4.4, Version is coded in the CSD_STRUCTURE byte in the ECSD register emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 27

28 SPEC_VERS Field (bits[125:122]) TAAC Field (bits[119:112]) The SPEC_VERS field in the CSD register defines the e MMC system specification version supported by the device. Table 7: SPEC_VERS Field Values SPEC_VERS System Specification Version Number 0 Versions Versions Versions Versions 3.1, 3.2, Versions 4.0, 4.1, 4.2, 4.3, 4.4, 4.41 [15:5] Reserved The TAAC field in the CSD register defines the asynchronous part of the data access time. Table 8: TAAC Field Bit Position Codes TAAC Bit Position Code [2:0] Time unit 0 = 1ns 1 = 10ns 2 = 100ns 3 = 1μs 4 = 10μs 5 = 100μs 6 = 1ms 7 = 10ms [6:3] Multiplier factor 0 = Reserved 1 = = = = = = = = = 4.0 A = 4.5 B = 5.0 C = 5.5 D = 6.0 E = 7.0 F = Reserved 4GB, 8GB, 16GB, 32GB: e MMC CSD Register Fields emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 28

29 NSAC Field (bits[111:104]) TRAN_SPEED Field (bits[103:96]) The NSAC field in the CSD register defines the typical case for the clock dependency of the data access time. The unit for the NSAC field is 100 clock cycles. Therefore, the maximum value for the clock-dependent part of the data access time is 25,500 clock cycles. The total access time is calculated based on both the TAAC and NSAC fields. The access time must be computed by the host for the actual clock rate. The read access time should be interpreted as a typical delay for the first data bit of a data block or stream. The TRAN_SPEED field in the CSD register defines the maximum bus clock frequency. The following table shows the clock frequency when the device is not in high-speed mode. For devices supporting specification version 4.0 and higher, the value is 20 MHz (0x2A). Table 9: TRAN_SPEED Field Bit Position Codes TRANS_SPEED Bit Code [2:0] Frequency unit 0 = 100 KHz 1 = 1 MHz 2 = 10 MHz 3 = 100 MHz [7:4] = Reserved [6:3] Multiplier factor 0 = Reserved 1 = = = = = = = = = 4.0 A = 4.5 B = 5.2 C = 5.5 D = 6.0 E = 7.0 F = Reserved 4GB, 8GB, 16GB, 32GB: e MMC CSD Register Fields emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 29

30 CCC Field (bits[95:84]) The e MMC command set is divided into subsets or command classes. The card command class (CCC) field in the CSD register defines which e MMC command classes are supported by the device. A value of 1 in a CCC bit means that the corresponding command class is supported. For command class definitions, see Command Classes. Table 10: CCC Field Bit Codes READ_BL_LEN Field (bits[83:80]) CCC Bit Supported Card Command Class 0 Class 0 2 Class 2 4 Class 4 5 Class 5 6 Class 6 7 Class 7 10 Class Class 11 The READ_BL_LEN field in the CSD register indicates the supported maximum read data block length. The data block length is computed as 2 READ_BL_LEN and is most likely in the range of 1, 2, 4, Support for 512-byte read access is mandatory for all devices, and the devices must be in 512-byte block length mode by default after poweron or a software reset. Table 11: READ_BL_LEN Field Block Length Codes READ_BL_LEN Block Length = 1 byte = 2 4GB, 8GB, 16GB, 32GB: e MMC CSD Register Fields = 2048 [15:12] Reserved emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 30

31 READ_BL_PARTIAL Field (bit 79) WRITE_BLK_MISALIGN Field (bit 78) READ_BLK_MISALIGN Field (bit 77) DSR_IMP Field (bit 76) The READ_BL_PARTIAL field in the CSD register determines whether partial block sizes can be used in block read commands. For densities up to 2GB in byte access mode: READ_BL_PARTIAL = 0 means that the READ_BL_LEN block size can be used for blockoriented data transfers. READ_BL_PARTIAL = 1 means that smaller blocks can also be used. The minimum block size is equal to the minimum addressable unit (1 byte). For densities greater than 2GB in sector access mode: READ_BL_PARTIAL = 0 means that only the 512 and the READ_BL_LEN block size can be used for block-oriented data transfers. READ_BL_PARTIAL = 1 means that smaller blocks than indicated in READ_BL_LEN can also be used. The minimum block size is equal to the minimum addressable unit (1 sector or 512 ). The WRITE_BLK_MISALIGN field in the CSD register determines whether the data block to be written by one command can be spread over more than one physical block of the memory device. The size of the memory block is defined in WRITE_BL_LEN. WRITE_BLK_MISALIGN = 0 means that crossing physical block boundaries is invalid. WRITE_BLK_MISALIGN = 1 means that crossing physical block boundaries is supported. The READ_BLK_MISALIGN field in the CSD register determines whether the data block to be read by one command can be spread over more than one physical block of the memory device. The size of the memory block is defined in READ_BL_LEN. READ_BLK_MISALIGN = 0 means that crossing physical block boundaries is invalid. READ_BLK_MISALIGN = 1 means that crossing physical block boundaries is supported. The DSR_IMP field in the CSD register determines whether the configurable driver stage is integrated on the device. If DSR_IMP is set to 1, a driver stage register must also be implemented. Table 12: DSR_IMP Field Codes DSR_IMP DS Register Type 0 DS register is not implemented 1 DS register implemented 4GB, 8GB, 16GB, 32GB: e MMC CSD Register Fields emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 31

32 C_SIZE Field (bits[73:62]) The C_SIZE field computes the device memory capacity for device densities up to 2GB. See SEC_COUNT Field ([215:212]) (page 50) for densities higher than 2GB. For densities higher than 2GB, this register should be set to the maximum possible value (0xFFF). The memory capacity of the device is computed from the entries C_SIZE, C_SIZE_MULT, and READ_BL_LEN as follows: Memory capacity = BLOCKNR BLOCK_LEN where BLOCKNR = (C_SIZE + 1) MULT MULT = 2 C_SIZE_MU LT + 2, (C_SIZE_MU LT < 8) BLOCK_LEN = 2 READ_BL_LEN, (READ_BL_LEN < 12) Therefore, the maximum capacity that can be coded is = 4GB. Example: A 4MB device with BLOCK_LEN = 512 can be coded by C_SIZE_MULT = 0 and C_SIZE = VDD_R_CURR_MIN Field (bits[61:59]), VDD_W_CURR_MIN Field (bits[55:53]) The values in these fields in the CSD register are valid when the device is not in highspeed mode. When the device is in high-speed mode, the current consumption is determined by the host from the power classes defined in the PWR_CL_ff_vvv fields in the ECSD register. The maximum values for read and write currents at the minimum power supply are coded in the following table. Table 13: VDD_R_CURR_MIN, VDD_W_CURR_MIN Field Values VDD_R_CURR_MIN VDD_W_CURR_MIN 2:0 0 = 0.5mA 1 = 1mA 2 = 5mA 3 = 10mA 4 = 25mA 5 = 35mA 6 = 60mA 7 = 100mA 4GB, 8GB, 16GB, 32GB: e MMC CSD Register Fields Codes for Maximum Read/Write Current Consumption Values emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 32

33 VDD_R_CURR_MAX Field (bits[58:56]), VDD_W_CURR_MAX Field (bits[52:50]) The values in these fields in the CSD register are valid when the device is not in highspeed mode. When the device is in high-speed mode, the current consumption is determined by the host from the power classes defined in the PWR_CL_ff_vvv fields in the ECSD register. The maximum values for read and write currents at the maximum power supply are coded in the following table. Table 14: VDD_R_CURR_MAX, VDD_W_CURR_MAX Field Values VDD_R_CURR_MAX VDD_W_CURR_MAX C_SIZE_MULT Field (bits[49:47]) [2:0] 0 = 1mA 1 = 5mA 2 = 10mA 3 = 25mA 4 = 35mA 5 = 45mA 6 = 80mA 7 = 200mA Codes for Maximum Read/Write Current Consumption Values The C_SIZE_MULT field in the CSD register is used for coding the factor MULT for computing the total device size. The MULT is defined as 2 (C_SIZE_MULT + 2). For device densities greater than 2GB, this field should be set to the maximum possible value (0x7). Table 15: C_SIZE_MULT Field Values C_SIZE_MULT Codes MULT Computations = = = = = = = = 512 4GB, 8GB, 16GB, 32GB: e MMC CSD Register Fields emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 33

34 ERASE_GRP_SIZE Field (bits[46:42]) ERASE_GRP_MULT Field (bits[41:37]) WP_GRP_SIZE Field (bits[36:32]) WP_GRP_ENABLE Field (bit 31) DEFAULT_ECC Field (bits[30:29]) R2W_FACTOR Field (bits[28:26]) The ERASE_GRP_SIZE field in the CSD register contains a 5-bit binary coded value used to compute the size of the erasable unit of the device. The size of the erasable unit, or the erase group, is determined by the ERASE_GRP_SIZE and the ERASE_GRP_MULT entries in the CSD register. The size of the erasable unit is computed as follows: Size of erasable unit = (ERASE_GRP_SIZE + 1) (ERASE_GRP_MULT + 1) This size is defined as the minimum number of write blocks that can be erased with a single ERASE command. The ERASE_GRP_MULT field in the CSD register is a 5-bit binary coded value used to calculate the size of the erasable unit of the device. The WP_GRP_SIZE field in the CSD register is the size of a write-protected group. This register contains a 5-bit binary coded value defining the number of erase groups that can be write protected. The actual size is computed by increasing the number of erase groups by one. A value of 0 means 1 erase group; a value of 31 means 32 erase groups. The WP_GRP_ENABLE field in the CSD register indicates whether group write protection is enabled. A value of 0 indicates that no group write protection is enabled. The DEFAULT_ECC field in the CSD register is set by the device manufacturer. This field defines the error correction code that is recommended for use. The field definition is the same as for the ECC field. The R2W_FACTOR field in the CSD register defines the typical block programming time as a multiple of the read access time. Table 16: R2W_FACTOR Field Values R2W_FACTOR Multiples of Read Access Time GB, 8GB, 16GB, 32GB: e MMC CSD Register Fields emmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 34