A25LMQ64 Series. 64M-BIT (x1 / x2 / x4) 3.3V CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY. Document Title. Revision History. AMIC Technology Corp.

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1 A25LMQ64 eries 64M-BIT (x1 / x2 / x4) 3.3V MO MXMIO (ERIAL MULTI I/O) FLAH MEMORY Document Title 64M-BIT (x1 / x2 / x4) 3.3V MO MXMIO (ERIAL MULTI I/O) FLAH MEMORY Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 8, 2013 Preliminary 0.1 hange Figure 7. unique ID to 64 bytes July 3, Add AE-Q100 Grade 3 ertification pending in FEATURE August 20, 2014 Add Part Numbering cheme Remove 16-pin OP (300mil) package type 0.3 hange fast read spec. from 104MHz to 84MHz eptember 30, 2014 hange tlqv from 10ns(max.) to 12ns(max.) 1.0 Final version release November 18, 2015 Final (November, 2015, Version 1.0) AMI Technology orp. AMI reserves the right to change products and specifications discussed herein without notice.

2 A25LMQ64 eries 64M-BIT (x1 / x2 / x4) 3.3V MO MXMIO (ERIAL MULTI I/O) FLAH MEMORY FEATURE GENERAL erial Peripheral Interface compatible -- Mode 0 and Mode 3 64Mb: 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four I/O mode) structure Equal ectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually ingle Power upply Operation to 3.6 volt for read, erase, and program operations Latch-up protected to 100mA from -1V to V +1V Low V write inhibit is from 2.2V to 2.4V PERFORMANE High Performance - Fast read for PI mode - 1 I/O: 84MHz with 8 dummy cycles - 2 I/O: 84MHz with 4 dummy cycles, equivalent to 168MHz - 4 I/O: 84MHz with 2+4 dummy cycles, equivalent to 336MHz - Fast read for QPI mode - 4 I/O: 84MHz with 2+2 dummy cycles, equivalent to 336MHz - 4 I/O: 84MHz with 2+4 dummy cycles, equivalent to 336MHz - Fast program time: 0.35ms (typ.) and 3ms (max.)/page (256-byte per page) - Byte program time: 6μs (typical) - 8/16/32/64 byte Wrap-Around Burst Read Mode - Fast erase time: 40ms (typ.)/sector (4K-byte per sector); 80ms (typ.)/block (32K-byte per block), 120ms (typ.) / block (64K-byte per block); 12s(typ.) /chip Low Power onsumption - Low active read current: 15mA (max.) at 84MHz (1 I/O), 25mA (max.) at 84MHz (4 I/O) - Low active erase/programming current: 20mA (typ.) - tandby current: 2μA (typ.) Deep Power Down: 2μA(typ.) Typical 100,000 erase/program cycles 10 years data retention OFTWARE FEATURE Input Data Format - 1-byte ommand code Advanced ecurity Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions - Additional 4k-bit secured OTP - 1K bit FDP serial flash definition parameter - 64 bytes unique ID for each device Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector or block - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programmed should have page in the erased state first) tatus Register Feature ommand Reset Program/Erase uspend Electronic Identification - JEDE 1-byte manufacturer ID and 2-byte device ID - RE command for 1-byte Device ID - REM command for 1-byte manufacturer ID and 1-byte device ID HARDWARE FEATURE erial lock () - erial clock input DI (IO0) - erial Data Input or erial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode DO (IO1) - erial Data Output or erial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode W (IO2) - Hardware write protection or serial data Input/Output for 4 x I/O read mode IO3 - erial input & Output for 4 x I/O read mode AE-Q100 Grade 3 ertification PAKAGE - 8-pin DIP (300mil), 8-pin OP (209mil), 8-pin WON (6*5mm) or 24-ball BGA (6*8mm) - All Pb-free (Lead-free) products are RoH2.0 compliant (November, 2015, Version 1.0) 1 AMI Technology orp.

3 A25LMQ64 eries GENERAL DERIPTION A25LMQ64 is 67,108,864 bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in two or four I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. A25LMQ64 feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a erial lock (), a serial data input (DI), and a serial data output (DO). erial access to the device is enabled by input. When it is in two I/O read mode, the DI pin and DO pin become IO0 pin and IO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the DI pin, DO pin and W pin become IO0 pin, IO1 pin, IO2 pin and IO3 pin for address/dummy bits input and data output. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte), or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and is high, it is put in standby mode and draws less than 30μA D current. Table 1. Additional Feature omparison Additional Features Protection and ecurity PI Read Performance QPI Part Name Flexible Block Protection (BP0-BP3) 4K-bit security OTP 1 I/O (84 MHz) 2 I/O (84 MHz) 4 I/O (84 MHz) 4 I/O (84 MHz) 4 I/O (84 MHz) A25LMQ64 V V V V V V V Additional Features Identifier Part Name RE (command: AB hex) REM (command: 90 hex) RDID (command: 9F hex) QRIID (ommand: AF hex) A25LMQ64 16 (hex) (hex) (if ADD=0) (November, 2015, Version 1.0) 2 AMI Technology orp.

4 A25LMQ64 eries Pin onfiguration 8-pin DIP / OP 8-pin WON A25LMQ64 A25LMQ64 DO (IO1) W (IO2) V V IO3 DI (IO0) DO (IO1) W (IO2) V V IO3 DI (IO0) 24-ball BGA A1 A2 A3 A4 N N N N B1 B2 B3 B4 N V V N N W (IO2) D1 D2 D3 D4 N DO (IO1) DI (IO0) IO3 E1 E2 E3 E4 N N N N F1 F2 F3 F4 N N N N Top View, Balls Facing Down (November, 2015, Version 1.0) 3 AMI Technology orp.

5 A25LMQ64 eries Pin Descriptions Pin Name Description DI (IO0) DO (IO1) W (IO2) IO3 V V N hip elect erial Data Input (for 1 x I/O) / erial Data Input & Output (for 2 x I/O or 4 x I/O read mode) erial Data Output (for 1 x I/O) / erial Data Input & Output (for 2 x I/O or 4 x I/O read mode) erial lock Write protection: connect to V or erial Data Input & Output (for 4 x I/O read mode) erial Data Input & Output (for 4 x I/O read mode) + 3.3V Power upply Ground No onnect Block Diagram Address Generator X-Decoder Memory Array Page Buffer DI (IO0) Data Register Y-Decoder RAM Buffer W (IO2) IO3 Mode Logic tate Machine HV Generator ense Amplifier lock Generator DO (IO1) Output Buffer (November, 2015, Version 1.0) 4 AMI Technology orp.

6 A25LMQ64 eries DATA PROTETION The A25LMQ64 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from V power-up and power-down transition or system noise. Power-on reset and tpuw: to avoid sudden power switch by system power supply transition, the power-on reset and tpuw (internal timer) may protect the Flash. Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write tatus Register (WRR) command completion - Page Program (PP) command completion - ector Erase (E) command completion - Block Erase 32KB (BE32K) command completion - Block Erase (BE) command completion - hip Erase (E) command completion - Program/Erase uspend - oftreset command completion - Write ecurity Register (WRUR) command completion Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic ignature command (RE) and softreset command. Block lock protection and additional 4K-bit secured OTP: there are block protection and 4K secured OTP which protect content from inadvertent write and hostile access. I. Block lock protection - The oftware Protected Mode (PM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as table of "Protected Area izes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "protected area sizes". - The Hardware Protected Mode (HPM) use W (IO2) to protect the (BP3, BP2, BP1, BP0) bits and tatus Register Write Protect bit. - In four I/O and QPI mode, the feature of HPM will be disabled (November, 2015, Version 1.0) 5 AMI Technology orp.

7 A25LMQ64 eries Table 2. Protected Area izes tatus Bit Protect Area BP3 BP2 BP1 BP0 64Mb (none) (2 blocks, block 126th~127th) (4 blocks, block 124th~127th) (8 blocks, block 120th~127th) (16 blocks, block 112th~127th) (32 blocks, block 96th~127th) (64 blocks, block 64th~127th) (128 blocks, all) (128 blocks, all) (128 blocks, all) (128 blocks, all) (128 blocks, all) (128 blocks, all) (128 blocks, all) (128 blocks, all) (128 blocks, all) II. Additional 4K-bit secured OTP: to provide 4K-bit one-time program area - Which may be locked by customer through WRUR command. The address range and size please refer to Table 3. 4K-bit secured OTP definition. - ecurity register bit 1 (LDO) indicates whether the 4K-bit secured OTP is locked or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with Enter ecurity OTP command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing Exit ecurity OTP command. - ustomer may lock-down the customer lockable secured OTP by writing WRUR (write security register) command to set bit 1 (LDO) as "1". Please refer to Table 8. ecurity register definition for security register bit definition. - Note: Once lock-down by LDO bit, it cannot be changed any more. While in 4K-bit secured OTP mode, array access is not allowed. Table 3. 4K-bit ecured OTP Definition ector ize Address Range 4096 bit xxx000 xxx1ff (November, 2015, Version 1.0) 6 AMI Technology orp.

8 A25LMQ64 eries Memory Organization Table 4. Memory Organization (64Mb) Block (64K-byte) Block (32K-byte) ector (4K-byte) Address Range FF000h 7FFFFFh F8000h 7F8FFFh F7000h 7F7FFFh F0000h 7F0FFFh EF000h 7EFFFFh E8000h 7E8FFFh E7000h 7E7FFFh E0000h 7E0FFFh DF000h 7DFFFFh D8000h 7D8FFFh D7000h 7D7FFFh D0000h 7D0FFFh F000h 02FFFFh h 028FFFh h 027FFFh h 020FFFh 31 01F000h 01FFFFh h 018FFFh h 017FFFh h 010FFFh 15 00F000h 00FFFFh h 008FFFh h 007FFFh h 000FFFh (November, 2015, Version 1.0) 7 AMI Technology orp.

9 A25LMQ64 eries DEVIE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LI, this LI becomes standby mode and keeps the standby mode until next falling edge. In standby mode, DO pin of this LI should be High-Z. 3. When correct command is inputted to this LI, this LI becomes active mode and keeps the active mode until next rising edge. 4. Input data is latched on the rising edge of erial lock () and data shifts out on the falling edge of erial lock (). The difference of erial mode 0 and mode 3 is shown as Figure 1. "erial Modes upported". 5. For the following instructions: RDID, RDR, RDUR, READ, FAT READ, 2READ, 4READ, RE, REM, QPIID, the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the can be high. For the following instructions: WREN, WRDI, WRR, E, BE32K, BE, E, PP, 4PP, DP, ENO, EXO, WRUR, UPEND, REUME, NOP, RTEN, RT, EQIO, RTQIO the must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write tatus Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write tatus Register, Program, Erase. Figure 1. erial Modes upported POL PHA hit in hit out Mode Mode DI MB DO MB Note: POL indicates clock polarity of erial master, POL=1 for erial lock () high while idle, POL=0 for erial lock () low while not transmitting. PHA indicates clock phase. The combination of POL bit and PHA bit decides which erial mode is supported. (November, 2015, Version 1.0) 8 AMI Technology orp.

10 A25LMQ64 eries Quad Peripheral Interface (QPI) Read Mode QPI protocol enables user to take full advantage of Quad I/O erial Flash by providing the Quad I/O interface in command cycles, address cycles and as well as data output cycles. Enable QPI mode (EQIO) By issuing 35H command, the QPI mode is enable. Figure 2. Enable QPI equence (ommand 35H) IO h IO[3:1] Quad Peripheral Interface (QPI) operation To use QPI protocol, the host drives low then sends the Fast Read command, 0BH, followed by 6 address cycles and four dummy cycles. Most significant bit (MB) comes first, as shown in figure 3. After the dummy cycle, the Quad Peripheral Interface (QPI) Flash Memory outputs data on the falling edge of the erial lock () signal starting from the specified address location. The device continually streams data output through all addresses until terminated by a low-to-high transition on. The internal address pointer automatically increases until the highest memory address is reached. When reached the highest memory address, the address pointer returns to the beginning of the address space. Figure 3. High-peed Read equence (QPI) (ommand 0BH) IO[3:0] 0B A5 A4 A3 A2 A1 A0 X X X X H0 L0 H1 L1 H2 L2 H3 L3 Data In MB Data Out (November, 2015, Version 1.0) 9 AMI Technology orp.

11 A25LMQ64 eries Read Data Bytes at Higher peed by Dual Output (FAT READ DUAL OUTPUT) The FAT READ DUAL OUTPUT (3Bh) instruction is similar to the FAT READ (0Bh) instruction except the data is output on two pins, IO0 and IO1, instead of just DO. This allows data to be transferred from the A25LMQ64 at twice the rate of standard PI devices. imilar to the FAT READ instruction, the FAT READ DUAL OUTPUT instruction can operate at the highest possible frequency of f (ee A haracteristics). This is accomplished by adding eight dummy clocks after the 24-bit address as shown in figure 4. The dummy clocks allow the device s internal circuits additional time for setting up the initial address. The input data during the dummy clocks is don t care. However, the IO0 and IO1 pins should be high-impedance prior to the falling edge of the first data out clock. Figure 4. FAT READ DUAL OUTPUT Instruction equence and Data-Out equence DI DO Instruction (3Bh) High Impedance MB 24-Bit Address Dummy Byte DIO switches from input to output DI DO MB MB Data Out 1 Data Out 2 Data Out 3 Data Out 4 7 MB Note: Address bit A23 is Don t are, for A25LMQ64 (November, 2015, Version 1.0) 10 AMI Technology orp.

12 A25LMQ64 eries Reset QPI mode (RTQIO) By issuing F5H command, the device is reset to 1-I/O PI mode. Figure 5. Reset QPI Mode (ommand F5H) IO[3:0] F5 Fast QPI Read mode (FATRDQ) To increase the code transmission speed, the device provides a "Fast QPI Read Mode" (FATRDQ). By issuing command code EBH, the FATRDQ mode is enable. The number of dummy cycle increase from 4 to 6 cycles. The read cycle frequency will increase from 84MHz. Figure 6. Fast QPI Read Mode (FATRDQ) (ommand EBH) IO[3:0] EB A5 A4 A3 A2 A1 A0 X X X X X X H0 L0 H1 L1 H2 L2 H3 L3 Data In MB Data Out (November, 2015, Version 1.0) 11 AMI Technology orp.

13 A25LMQ64 eries OMMAND DERIPTION Table 5. ommand et Read ommands I/O Read Mode PI PI PI PI PI PI ommand (byte) READ (normal read) FAT READ * (fast read data) FDP UNIQUE ID 2READ (2 x I/O read command) Note1 FAT READ DAUL OUTPUT * (fast read data) lock rate (MHz) st byte 03 (hex) 0B (hex) 5A (hex) 4B (hex) BB (hex) 3B (hex) 2nd byte AD1(8) AD1(8) AD1 (8) Dummy (8) AD1(4) AD1(8) 3rd byte AD2(8) AD2(8) AD2 (8) Dummy (8) AD2(4) AD2(8) 4th byte AD3(8) AD3(8) AD3 (8) Dummy (8) AD3(4) AD3(8) 5th byte Dummy(8) Dummy(8) Dummy (8) Dummy(4) Dummy(8) Action n bytes read out n bytes read out n bytes read out n bytes read out until goes highuntil goes highuntil goes highuntil goes high n bytes read out by 2 x I/O until goes high n bytes read out by 2 x I/O until goes high PI PI QPI QPI W4READ 4READ * (4 x I/O read command) Note1 FAT READ * (fast read data) 4READ * (4 x I/O read command) Note E7 (hex) EB (hex) 0B (hex) EB (hex) AD1(2) AD1(2) AD1(2) AD1(2) AD2(2) AD2(2) AD2(2) AD2(2) AD3(2) AD3(2) AD3(2) AD3(2) Dummy(4) Dummy(6) Dummy(4) Dummy(6) Quad I/O read with 4 dummy cycles in 84MHz Quad I/O read with 6 dummy cycles in 84MHz Quad I/O read with 4 dummy cycles in 84MHz Quad I/O read with 6 dummy cycles in 84MHz (November, 2015, Version 1.0) 12 AMI Technology orp.

14 A25LMQ64 eries Program/Erase ommands ommand (byte) WREN* (write enable) WRDI * (write disable) RDR * (read status register) WRR * (write status register) 4PP (quad page program) E * (sector erase) BE 32K * (block erase 32KB) 1st byte 06 (hex) 04 (hex) 05 (hex) 01 (hex) 38 (hex) 20 (hex) 52 (hex) 2nd byte Values AD1 AD1 AD1 3rd byte AD2 AD2 AD2 4th byte AD3 AD3 AD3 Action sets the (WEL) write enable latch bit resets the (WEL) write enable latch bit to read out the values of the status register to write new values of the status register quad input to program the selected page to erase the selected sector to erase the selected 32K block ommand (byte) BE * (block erase 64KB) E * (chip erase) PP * (page program) DP * (Deep power down) RDP * (Release from deep power down) PGM/ER uspend * (uspends Program/ Erase) PGM/ER Resume * (Resumes Program/ Erase) 1st byte D8 (hex) 60 or 7 (hex) 02 (hex) B9 (hex) AB (hex) B0 (hex) 30 (hex) 2nd byte AD1 AD1 3rd byte AD2 AD2 4th byte AD3 AD3 Action to erase the selected block to erase whole chip to program the selected page enters deep power down mode release from deep power down mode (November, 2015, Version 1.0) 13 AMI Technology orp.

15 A25LMQ64 eries ecurity/id/mode etting/reset ommands ommand (byte) RDID (read identification) RE (read electronic ID) REM (read electronic manufacturer & device ID) ENO * (enter secured OTP) EXO * (exit secured OTP) RDUR * (read security register) WRUR * (write security register) 1st byte 9F (hex) AB (hex) 90 (hex) B1 (hex) 1 (hex) 2B (hex) 2F (hex) 2nd byte x x 3rd byte x x 4th byte x ADD (Note 2) 5th byte Action outputs JEDE ID: 1-byte Manufacturer ID & 2-byte Device ID to read out 1-byte Device ID output the Manufacturer ID & Device ID to enter the 4K-bit secured OTP mode to exit the 4Kbit secured OTP mode to read value of security register to set the lock-down bit as "1" (once lock- down, cannot be update) ommand (byte) NOP * RTEN * (No Operation) (Reset Enable) RT * (Reset Memory) EQIO (Enable Quad I/O) RTQIO (Reset Quad I/O) QPIID (QPI ID Read) BL * (et Burst Length) 1st byte 00 (hex) 66 (hex) 99 (hex) 35 (hex) F5 (hex) AF (hex) 0 (hex) 2nd byte Value 3rd byte 4th byte Action Entering the QPI mode Exiting the QPI mode ID in QPI interface to set Burst length Note 1: ommand set highlighted with (*) are supported both in PI and QPI mode. Note 2: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MB is on DI (IO0) which is different from 1 x I/O condition. Note 3: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. Note 4: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. Note 5: RT command only executed if RTEN command is executed first. Any intervening command will disable Reset. (November, 2015, Version 1.0) 14 AMI Technology orp.

16 A25LMQ64 eries Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, E, BE32K, BE, E, and WRR, which are intended to change the device content WEL bit should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: goes low sending WREN instruction code goes high. Both PI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The DO[3:1] are don't care in PI mode. (Please refer to Figure 15-1 and Figure 15-2) Write Disable (WRDI) The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: goes low sending WRDI instruction code goes high. Both PI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The DO[3:1] are don't care in PI mode. (Please refer to Figure 16-1 and Figure 16-2) The WEL bit is reset by following situations: - Power-up - ompletion of Write Disable (WRDI) instruction - ompletion of Write tatus Register (WRR) instruction - ompletion of Page Program (PP) instruction - ompletion of Quad Page Program (4PP) instruction - ompletion of ector Erase (E) instruction - ompletion of Block Erase 32KB (BE32K) instruction - ompletion of Block Erase (BE) instruction - ompletion of hip Erase (E) instruction - Pgm/Ers uspend Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as Table 7. ID Definitions. The sequence of issuing RDID instruction is: goes low sending RDID instruction code 24-bits ID data out on DO to end RDID operation can drive to high at any time during data out. While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on the cycle of Program/Erase operation which is currently in progress. When goes high, the device is at standby stage. Read tatus Register (RDR) The RDR instruction is for reading tatus Register Bits. The Read tatus Register can be read at any time (even in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDR instruction is: goes low sending RDR instruction code tatus Register data out on DO. Both PI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The DO[3:1] are don't care when during PI mode. (Please refer to Figure 18-1 and Figure 18-2) For user to check if Program/Erase operation is finished or not, RDR instruction flow are shown as follows: (November, 2015, Version 1.0) 15 AMI Technology orp.

17 A25LMQ64 eries Program/ Erase flow with read array data tart WREN ommand RDR ommand* WREN=1? No Yes Program/erase command Write program data/address (Write erase address) RDR command WIP=0? No Yes RDR command Read WEL=0, BP[3:0], QE, and RWD data Read array data (same address of PGM/ER) Verify OK? No Yes Program/erase successfully Program/erase fail Program/erase another block? No Yes *Issue RDR to check BP[3:0] Program/erase completed (November, 2015, Version 1.0) 16 AMI Technology orp.

18 A25LMQ64 eries Program/ Erase flow without read array data (read REGPFAIL/REGEFAIL flag) tart WREN ommand RDR ommand* WREN=1? No Yes Program/erase command Write program data/address (Write erase address) RDR command WIP=0? No Yes RDR command Read WEL=0, BP[3:0], QE, and RWD data RDUR command REGPFAIL/ REGEFAIL=1? Yes No Program/erase successfully Program/erase fail Program/erase another block? No Yes *Issue RDR to check BP[3:0] Program/erase completed (November, 2015, Version 1.0) 17 AMI Technology orp.

19 A25LMQ64 eries WRR flow tart WREN ommand RDR ommand WREN=1? No Yes WRR command Write status register data RDR command WIP=0? No Yes RDR command Read WEL=0, BP[3:0], QE, and RWD data Verify OK? No Yes WRR successfully WRR fail (November, 2015, Version 1.0) 18 AMI Technology orp.

20 A25LMQ64 eries The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next program/ erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs to be confirm to be 0. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in table 2) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write tatus Register (WRR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), ector Erase (E), Block Erase 32KB (BE32K), Block Erase (BE) and hip Erase (E) instructions (only if Block Protect bits (BP3:BP0) set to 0, the E instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is unprotected. QE bit. The Quad Enhance (QE) bit, non-volatile bit, enhances PI Quad modes. It controls only hardware protect function in PI mode. It is reset to "0" (factory default) to enable hardware protect function or is set to "1" to disable hardware protect function. The PI Quad I/O commands will be always accepted by flash no matter QE bit is 1 or 0. The QE bit has to be set the through WRR command tatus Register bit 6. In PI mode and QE bit is 0. ( W ) pin should not keep floating in case incidentally hardware protected when RWD bit is 1. RWD bit. The tatus Register Write Disable (RWD) bit, non-volatile bit, is operated together with Write Protection ( W ) pin for providing hardware protection mode. The hardware protection mode requires RWD sets to 1 and W pin signal is low stage. In the hardware protection mode, the Write tatus Register (WRR) instruction is no longer accepted for execution and the RWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The RWD bit defaults to be "0". tatus Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RWD (status register write protect) 1=status register write disable QE (Quad Enhance) 1=Quad Enhance 0=not Quad Enhance BP3 (level of protected block) BP2 (level of protected block) BP1 (level of protected block) BP0 (level of protected block) (note 1) (note 1) (note 1) (note 1) WEL (write enable latch) 1=write enable 0=not write enable WIP (write in progress bit) 1=write operation 0=not in write operation Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit volatile bit volatile bit Note 1: ee the Table 2. Protected Area ize. (November, 2015, Version 1.0) 19 AMI Technology orp.

21 A25LMQ64 eries Write tatus Register (WRR) The WRR instruction is for changing the values of tatus Register Bits. Before sending WRR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in Table 2). The WRR also can set or reset the Quad Enhance (QE) bit and set or reset the tatus Register Write Disable (RWD) bit in accordance with Write Protection ( W ) pin signal, but has no effect on bit1(wel) and bit0 (WIP) of the status register. The WRR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRR instruction is: goes low sending WRR instruction code tatus Register data on DI goes high. (Please refer to Figure 19-1 and Figure 19-2) The must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write tatus Register cycle time (tw) is initiated as soon as hip elect ( ) goes high. The Write in Progress (WIP) bit still can be check out during the Write tatus Register cycle is in progress. The WIP sets 1 during the tw timing, and sets 0 when Write tatus Register ycle is completed, and the Write Enable Latch (WEL) bit is reset. Table 6. Protection Modes Mode tatus register condition W and RWD bit status Memory oftware protection mode (PM) tatus register can be written in (WEL bit is set to "1") and the RWD, BP0-BP3 bits can be changed W =1 and RWD bit=0, or W =0 and RWD bit=0, or W =1 and RWD=1 The protected area cannot be program or erase. Hardware protection mode (HPM) The RWD, BP0-BP3 of status register bits cannot be changed W =0, RWD bit=1 The protected area cannot be program or erase. Note: 1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the tatus Register, as shown in Table 2. As the above table showing, the summary of the oftware Protected Mode (PM) and Hardware Protected Mode (HPM). oftware Protected Mode (PM): - When RWD bit=0, no matter W is low or high, the WREN instruction may set the WEL bit and can change the values of RWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (PM). - When RWD bit=1 and W is high, the WREN instruction may set the WEL bit can change the values of RWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (PM). Note: If RWD bit=1 but W is low, it is impossible to write the tatus Register even if the WEL bit has previously been set. It is rejected to write the tatus Register and not be executed. Hardware Protected Mode (HPM): - When RWD bit=1, and then W is low (or W is low before RWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the W to against data modification. Note: To exit the hardware protected mode requires W driving high once the hardware protected mode is entered. If the W pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. If the system enter QPI or set QE=1, the feature of HPM will be disabled. (November, 2015, Version 1.0) 20 AMI Technology orp.

22 A25LMQ64 eries Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of erial lock (), and data shifts out on the falling edge of erial lock () at a maximum frequency fr. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: goes low sending READ instruction code 3-byte address on DI data out on DO to end READ operation can use to high at any time during data out. (Please refer to Figure 20) Read Data Bytes at Higher peed (FAT READ) The FAT READ instruction is for quickly reading data out. The address is latched on rising edge of erial lock (), and data of each bit shifts out on the falling edge of erial lock () at a maximum frequency f. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAT READ instruction. The address counter rolls over to 0 when the highest address has been reached. Read on PI Mode The sequence of issuing FAT READ instruction is: goes low sending FAT READ instruction code 3-byte address on DI 1-dummy byte (default) address on DI data out on DO to end FAT READ operation can use to high at any time during data out. (Please refer to Figure 21-1) Read on QPI Mode The sequence of issuing FAT READ instruction in QPI mode is: goes low sending FAT READ instruction, 2 cycles 24-bit address interleave on IO3, IO2, IO1 & IO0 4 dummy cycles data out interleave on IO3, IO2, IO1 & IO0 to end QPI FAT READ operation can use to high at any time during data out. (Please refer to Figure 21-2) In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h and afterwards is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. While Program/Erase/Write tatus Register cycle is in progress, FAT READ instruction is rejected without any impact on the Program/Erase/Write tatus Register current cycle. 2 x I/O Read Mode (2READ) The 2READ instruction enable double throughput of erial Flash in read mode. The address is latched on rising edge of erial lock (), and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of erial lock () at a maximum frequency ft. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: goes low sending 2READ instruction 24-bit address interleave on IO1 & IO0 4 dummy cycles on IO1 & IO0 data out interleave on IO1 & IO0 to end 2READ operation can use to high at any time during data out (Please refer to Figure 22. for 2 x I/O Read Mode Timing Waveform). While Program/Erase/Write tatus Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write tatus Register current cycle. 4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of erial Flash in read mode. The address is latched on rising edge of erial lock (), and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of erial lock () at a maximum frequency fq. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. 4 x I/O Read on PI Mode (4READ) The sequence of issuing 4READ instruction is: goes low sending 4READ instruction 24-bit address interleave on IO3, IO2, IO1 & IO0 2+4 dummy cycles data out interleave on IO3, IO2, IO1 & IO0 to end 4READ operation can use to high at any time during data out. W4READ instruction (E7) is also available is PI mode for 4 I/O read. The sequence is similar to 4READ, but with only 4 dummy cycles. The clock rate runs at 84MHz. 4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence of issuing 4READ instruction QPI mode is: goes low sending 4READ instruction 24-bit address interleave IO3, IO2, IO1 & IO0 2+4 dummy cycles data out interleave on IO3, IO2, IO1 & IO0 to end 4READ operation can use to high at any time during data out (Please refer to Figure 23. for 4 x I/O Read Mode Timing Waveform). Another sequence of issuing 4 READ instruction especially useful in random access is : goes low sending 4 READ instruction 3-bytes address interleave on IO3, IO2, IO1 & IO0 performance enhance toggling bit P[7:0] 4 dummy cycles data out still goes high goes low (reduce 4 Read instruction) 24-bit random access address (Please refer to Figure 24-1 and Figure 24-2 for 4 x I/O Read Enhance Performance Mode Timing Waveform). In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make (November, 2015, Version 1.0) 21 AMI Technology orp.

23 A25LMQ64 eries this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h and afterwards is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. While Program/Erase/Write tatus Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write tatus Register current cycle. Burst Read This device supports Burst Read in both PI and QPI mode. To set the Burst length, following command operation is required.. Issuing command: 0h in the first Byte (8-clocks), following 4 clocks defining wrap around enable with 0h and disable with 1h. Next 4 clocks is to define wrap around depth. Definition as following table: Data Wrap Around Wrap Depth Data Wrap Around Wrap Depth 1xh No X 00h Yes 8-byte 1xh No X 01h Yes 16-byte 1xh No X 02h Yes 32-byte 1xh No X 03h Yes 64-byte The wrap around unit is defined within the 256Byte page, with random initial address. It s defined as wrap-around mode disable for the default state of the device. To exit wrap around, it is required to issue another 0 command in which data= 1xh. Otherwise, wrap around status will be retained until power down or reset command. To change wrap around depth, it is required to issue another 0 command in which data= 0xh. QPI 0Bh EBh and PI EBh E7h support wrap around feature after wrap around enable. Burst read is supported in both PI and QPI mode. The device id default without Burst read. PI Mode IO[3:0] H H H H L L L L QPI Mode IO[3:0] 1 0 H0 L0 MB LB Note: MB = Most ignificant Bit LB = Least ignificant Bit (November, 2015, Version 1.0) 22 AMI Technology orp.

24 A25LMQ64 eries Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note Figure 24-1 and Figure x I/O Read enhance performance mode sequence). Performance enhance mode is supported in both PI and QPI mode. In QPI mode, EBh 0Bh and PI EBh E7h commands support enhance mode. The performance enhance mode is not supported in dual I/O mode. After entering enhance mode, following B go high, the device will stay in the read mode and treat B go low of the first clock as address instead of command cycle. To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue FFh command to exit enhance mode. Performance Enhance Mode Reset (FFh) To conduct the Performance Enhance Mode Reset operation in PI mode, FFh command code, 8 clocks, should be issued in 1I/O sequence. In QPI Mode, FFFFFFFFh command code, 8 clocks, in 4I/O should be issued. (Please refer to Figure 38) If the system controller is being Reset during operation, the flash device will return to the standard PI operation. Upon Reset of main chip, PI instruction would be issued from the system. Instructions like Read ID (9Fh) or Fast Read (0Bh) would be issued. Both PI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The IO[3:1] are don't care when during PI mode. (Please refer to Figure 38) ector Erase (E) The ector Erase (E) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the ector Erase (E). Any address of the sector (see table of memory organization) is a valid address for ector Erase (E) instruction. The must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits (A22-A12) select the sector address. The sequence of issuing E instruction is: goes low sending E instruction code 3-byte address on DI goes high. Both PI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The IO[3:1] are don't care when during PI mode. (Please refer to Figure 27-1 and Figure 27-2) The self-timed ector Erase ycle time (te) is initiated as soon as hip elect ( ) goes high. The Write in Progress (WIP) bit still can be check out during the ector Erase cycle is in progress. The WIP sets 1 during the te timing, and sets 0 when ector Erase ycle is completed, and the Write Enable Latch (WEL) bit is reset. If the sector is protected by BP3, BP2, BP1, BP0 bits, the ector Erase (E) instruction will not be executed on the sector. Block Erase (BE32K) The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see table of memory organization) is a valid address for Block Erase (BE32K) instruction. The must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE32K instruction is: goes low sending BE32K instruction code 3-byte address on DI goes high. Both PI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The IO[3:1] are don't care when during PI mode. (Please refer to Figure 28-1 and Figure 28-2) The self-timed Block Erase ycle time (tbe32k) is initiated as soon as hip elect ( ) goes high. The Write in Progress (WIP) bit still can be check out during the Block Erase cycle is in progress. The WIP sets 1 during the tbe32k timing, and sets 0 when Block Erase ycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (tbe32k) instruction will not be executed on the block. Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to table of memory organization) is a valid address for Block Erase (BE) instruction. The must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: goes low sending BE instruction code 3-byte address on DI goes high. Both PI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The IO[3:1] are don't care when during PI mode. (Please refer to Figure 29-1 and Figure 29-2) The self-timed Block Erase ycle time (te) is initiated as soon as hip elect ( ) goes high. The Write in Progress (WIP) bit still can be check out during the Block Erase cycle is in progress. The WIP sets 1 during the te timing, and sets 0 when Block Erase ycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block. hip Erase (E) The hip Erase (E) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the hip Erase (E). The must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. The sequence of issuing E instruction is: goes low sending E instruction code goes high. Both PI (8 clocks) and QPI (2 clocks) command cycle can (November, 2015, Version 1.0) 23 AMI Technology orp.

25 A25LMQ64 eries accept by this instruction. The IO[3:1] are don't care when during PI mode. (Please refer to Figure 30-1 and Figure 30-2) The self-timed hip Erase ycle time (te) is initiated as soon as hip elect ( ) goes high. The Write in Progress (WIP) bit still can be check out during the hip Erase cycle is in progress. The WIP sets 1 during the te timing, and sets 0 when hip Erase ycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3, BP2, BP1, BP0 bits, the hip Erase (E) instruction will not be executed. It will be only executed when BP3, BP2, BP1, BP0 all set to "0". Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: goes low sending PP instruction code 3-byte address on DI at least 1-byte on data on DI goes high. (Please refer to Figure 25-1 and Figure 25-2) The must be kept to low during the whole Page Program cycle; The must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program ycle time (tpp) is initiated as soon as hip elect ( ) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tpp timing, and sets 0 when Page Program ycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. Both PI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The IO[3:1] are don't care when during PI mode. 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: IO0, IO1, IO2, and IO3 as address and data input, which can improve programmer performance and the effectiveness of application of lower clock less than 33MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 33MHz below. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: goes low sending 4PP instruction code 3-byte address on IO[3:0] at least 1-byte on data on IO[3:0] goes high. Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from IB1 to IB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When goes high, it's only in deep power-down mode not standby mode. It's different from tandby mode. The sequence of issuing DP instruction is: goes low sending DP instruction code goes high. Both PI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The IO[3:1] are don't care when during PI mode. (Please refer to Figure 31-1 and Figure 31-2) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic ignature (RE) instruction and softreset command. (those instructions allow the ID being reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For DP instruction the must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as hip elect ( ) goes high, a delay of tdp is required before entering the Deep Power-down mode. Release from Deep Power-down (RDP), Read Electronic ignature (RE) The Release from Deep Power-down (RDP) instruction is terminated by driving hip elect ( ) High. When hip elect () is driven High, the device is put in the tand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the tand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the tand-by Power mode is delayed by tre2, and hip elect ( ) must remain High for at least tre2(max), as specified in Table 12. A haracteristics. Once in the tand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction is only for releasing from Deep Power Down Mode. RE instruction is for reading out the old style of 8-bit Electronic ignature, whose values are shown as table of ID Definitions on next page. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. The sequence is shown as Figure 32, Figure 33-1 and Figure Even in Deep power-down mode, the RDP and RE are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. Only PI (8 clocks) command cycle can accept by this instruction. (November, 2015, Version 1.0) 24 AMI Technology orp.