EE178 Spring 2018 Lecture Module 1. Eric Crabill

Similar documents
(ii) Simplify and implement the following SOP function using NOR gates:

Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition

Injntu.com Injntu.com Injntu.com R16

Lecture #1: Introduction

CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT

SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS


Philadelphia University Student Name: Student Number:

R07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April

Digital System Design with SystemVerilog

PINE TRAINING ACADEMY

HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment

I 3 I 2. ! Language of logic design " Logic optimization, state, timing, CAD tools

Digital Design. Verilo. and. Fundamentals. fit HDL. Joseph Cavanagh. CRC Press Taylor & Francis Group Boca Raton London New York

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

Verilog for High Performance

R10. II B. Tech I Semester, Supplementary Examinations, May

UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan

This content has been downloaded from IOPscience. Please scroll down to see the full text.

Code No: R Set No. 1

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY

VHDL for Synthesis. Course Description. Course Duration. Goals

IA Digital Electronics - Supervision I

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs)

Henry Lin, Department of Electrical and Computer Engineering, California State University, Bakersfield Lecture 7 (Digital Logic) July 24 th, 2012

ECE 241F Digital Systems

Outline. EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) FPGA Overview. Why FPGAs?

COPYRIGHTED MATERIAL INDEX

COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I

Laboratory Finite State Machines and Serial Communication

Code No: 07A3EC03 Set No. 1

Digital Logic Design Lab

Chapter 1 Overview of Digital Systems Design

VALLIAMMAI ENGINEERING COLLEGE

DIGITAL ELECTRONICS. Vayu Education of India

Outline. EECS Components and Design Techniques for Digital Systems. Lec 11 Putting it all together Where are we now?

VALLIAMMAI ENGINEERING COLLEGE

Code No: R Set No. 1

World Class Verilog & SystemVerilog Training

Digital logic fundamentals. Question Bank. Unit I

EE178 Lecture Verilog FSM Examples. Eric Crabill SJSU / Xilinx Fall 2007

SHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI

St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad


3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0

EECS150, Fall 2004, Midterm 1, Prof. Culler. Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function.

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)

structure syntax different levels of abstraction

Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this

Institute of Engineering & Management

V1 - VHDL Language. FPGA Programming with VHDL and Simulation (through the training Xilinx, Lattice or Actel FPGA are targeted) Objectives

FPGA for Software Engineers

Digital Logic Design Exercises. Assignment 1

ii) Do the following conversions: output is. (a) (101.10) 10 = (?) 2 i) Define X-NOR gate. (b) (10101) 2 = (?) Gray (2) /030832/31034

EE178 Spring 2018 Lecture Module 4. Eric Crabill

UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A (2 MARKS)

BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS

University of Hawaii EE 361L. Getting Started with Spartan 3E Digilent Basys2 Board. Lab 4.1

END-TERM EXAMINATION

Lab 3 Sequential Logic for Synthesis. FPGA Design Flow.

Question Total Possible Test Score Total 100

WELCOME TO. ENGR 303 Introduction to Logic Design. Hello my name is Dr. Chuck Brown

ECE 156A - Syllabus. Description

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1

R a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

Department of Computer Science and Engineering Khulna University of Engineering & Technology Khulna , Bangladesh. Course Plan/Profile

ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog

Lecture (05) Boolean Algebra and Logic Gates

Course Batch Semester Subject Code Subject Name. B.E-Marine Engineering B.E- ME-16 III UBEE307 Integrated Circuits

CSCE 312 Lab manual. Lab 4 - Computer Organization and Data Path Design. Instructor: Dr. Yum. Fall 2016

R07

Digital Integrated Circuits

Computer Arithmetic andveriloghdl Fundamentals

10EC33: DIGITAL ELECTRONICS QUESTION BANK

PART B. 3. Minimize the following function using K-map and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).

Music. Numbers correspond to course weeks EULA ESE150 Spring click OK Based on slides DeHon 1. !

Memory Controller. System Integration Issues. Encoding numbers 1GB RAM FSM. Communicating FSMs Clocking, theory and practice. Combinational Logic

Verilog Hardware Description Language ROOM: B405

Microprocessor Systems

EE 1315: DIGITAL LOGIC LAB EE Dept, UMD

Elec 326: Digital Logic Design

Don t expect to be able to write and debug your code during the lab session.

The QR code here provides a shortcut to go to the course webpage.

INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad ELECTRONICS AND COMMUNICATIONS ENGINEERING

TEACHING & EXAMINATION SCHEME For the Examination COMPUTER SCIENCE. B.Sc. Part-I

קורס VHDL for High Performance. VHDL

CAD for VLSI. Debdeep Mukhopadhyay IIT Madras

: : (91-44) (Office) (91-44) (Residence)

Review. EECS Components and Design Techniques for Digital Systems. Lec 03 Field Programmable Gate Arrays

Sunburst Design - Verilog-2001 Design & Best Coding Practices by Recognized Verilog & SystemVerilog Guru, Cliff Cummings of Sunburst Design, Inc.

Indian Silicon Technologies 2013

Final Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours)

Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.

Computer Organization

Finite State Machines (FSMs) and RAMs and CPUs. COS 116, Spring 2011 Sanjeev Arora

MLR Institute of Technology

Transcription:

EE178 Spring 2018 Lecture Module 1 Eric Crabill

Goals I am here because I enjoy sharing information on how to use Xilinx silicon, software, and solutions You are here to earn elective credits, but more importantly, to gain marketable experience

Syllabus Review No paper handouts print your own URL to supplemental reading material Class format is lecture with practical exercises and project assignments Substantial effort is required of you There is no dedicated lab meeting

Academic Integrity All work is expected to be your own It is okay to talk to each other and share ideas It is not okay to cut and paste or share files See policy on academic dishonesty If you are worried about contamination then ask an instructor for help

Required Equipment Immediately order and obtain a Digilent Basys3 board (Xilinx Artix 7 FPGA) http://www.digilentinc.com Request academic pricing No optional items Labs may require access to other items (VGA display, speaker or headphones)

Required Equipment Provide your own development system Laptop or desktop PC with a USB port Windows 10 (64-bit) is the required O/S Download and install Xilinx Vivado 2016.2 Webpack Edition Described in first lab assignment Pay attention to version / edition

Prior Knowledge You should already be familiar with digital logic design from a class such as EE118 Electrical / Logical Basics Combinational Logic Sequential Logic Verilog-HDL Let s quickly review what this means to me This is not a crash course, it is a summary list Items in gray are less important for this class

Electrical Basics Simple logic circuit implementation with transistors -- basic gates, etc... Transmission gates and three-state buffers Concepts of switching thresholds, noise margin, and electrical characteristics Digital abstraction of underlying analog circuits

Logical Basics Boolean algebra (all those rules ) Number systems and representation Binary / Hexadecimal / Decimal Conversions Arithmetic

Combinational Logic Simple gates and their truth tables More complex functions and their truth tables Multiplexers Encoders, decoders Arithmetic circuits Half Adder/Subtractors, Full Adder/Subtractors Ripple Adders/Subtractors (n-bit) Magnitude and Identity Comparators

Combinational Logic Combinational circuit analysis Random logic design SOP and POS canonical forms Use of KMAP to generate canonical forms Use of Don t Cares in logic design Static and dynamic hazards

Sequential Logic Analysis of feedback sequential circuits Design of feedback sequential circuits Use of feedback sequential circuits Flip flops Latches Analysis of synchronous sequential circuits Design of synchronous sequential circuits

Sequential Logic Application of common synchronous circuits Registers (various types) Counters Models of synchronous sequential circuits Mealy Moore Finite state machine design techniques State assignment / encoding options

Verilog-HDL Notion of a hardware description language Use of Verilog-HDL for describing digital circuits and simulating their behavior Different ways to describe digital circuits Behavioral Register Transfer Level Primitive or Gate Level

Why Use FPGAs? You would use an FPGA if it is the best choice given some metric for optimal Do we know what an FPGA is? What are viable alternatives? Custom ASIC Structured ASIC (Gate Array) Microcontroller Processor system Application specific standard product Random components (e.g. SSI, MSI)

Some Metrics for Optimal Size, weight, and power Total design cost Direct component cost Board complexity / cost NRE and amortization Time to design Observability, debug Availability of IP Time to market Component mfg. time Lifetime Component availability Performance Clock frequency Throughput / parallelism Latency Reliability Hard failure rates Soft failure rates Field upgradability Product before specification Extend product lifespan Risk reduction

Commercial Applications of Programmable Logic Wired Communications Wireless Communications Wired infrastructure Data center, storage Wireless infrastructure Industrial, Scientific, Medical Audio, Video, Broadcast Ultrasound systems Motor controllers 3D cameras Video transport Automotive Consumer Infotainment Driver assistance 3D television ereaders Test & Measurement Communications instruments Semiconductor test equipment Source: Xilinx, Inc.