UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan
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1 UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UNIT I - NUMBER SYSTEMS AND LOGIC GATES Introduction to decimal- Binary- Octal- Hexadecimal number systems-inter conversions-bcd code- Excess -3 code- Gray code One s complement and two s complements- Arithmetic operations- Addition- Subtraction- Multiplication and division- Basic and derived logic gates- Symbols and their truth tables- AND-OR-NOT- NAND- NOR- XOR- XNOR- Universal NAND and NOR gates-boolean algebra Basic laws of Boolean algebra De- Morgan s theorems- Reducing Boolean expressions using Boolean laws- SOP and POS forms of expressions- Min term and max terms- Karnaugh map simplification. 1 Introduction to decimal- Ability to understand the basic Binary- Octal- concepts of number systems. Hexadecimal number systems 2 Inter conversions Ability to understand the number system conversions 3 BCD code- Excess -3 Ability to understand the code code- Gray code Malvino A.P.and conversions 4 One s complement and Leach D.P.,Digital Ability to understand the arithmetic two s complements- Principles and operations Arithmetic operations- Applications, 4 th Addition- Subtraction Edition, McGraw 5 Multiplication and division Hill, Ability to understand the arithmetic operations 6 Basic and derived logic gates- Symbols and their various logic gates truth tables- AND-OR- NOT- NAND- NOR- XOR- XNOR. 7 Universal NAND and
2 NOR gates-boolean universal logic gates algebra Basic laws of Boolean algebra 8 De- Morgan s theorems theorems 9 Reducing Boolean various expressions using Boolean Boolean laws laws 10 SOP and POS forms of Ability to simplify logic expressions expressions- Min term and max terms 11 SOP and POS forms of expressions- Min term and max terms Ability to simplify logic expressions 12 Karnaugh map Ability to simplify logic expressions simplification. UNIT II - COMBINATIONAL LOGIC GATES Half and full adders- Half and full subtractors- Binary adders and subtractors- Two s complement adder/subtractor - Binary Coded Decimal (BCD) adder- Decoder-Encoder-Multiplexer- Demultiplexer-Analog to digital (A/D) conversion- Successive approximation- Digital to analog (D/A) conversion-r-2r ladder method. 13 Half and full adders 14 Half and full subtractors Malvino A.P.and 15 Binary adders and Leach D.P.,Digital subtractors Principles and 16 Two s complement Applications, 4 th adder/subtractor Edition, McGraw 17 Binary Coded Decimal Hill, (BCD) adder 18 Decoder-Encoder 19 Multiplexer
3 20 Demultiplexer 21 Analog to digital (A/D) Ability to understand ADC conversion 22 Successive approximation Ability to understand ADC 23 Digital to analog (D/A) Ability to understand DAC conversion 24 R-2R ladder method Ability to understand DAC UNIT III - SEQUENTIAL LOGIC SYSTEMS Flip flop-rs flip flop - Clocked RS flip flop-d flip flops JK flip flop - JK as master slave flip flops- Registers- Shift registers-shift left and Shift right registers- Counters-Synchronous and asynchronous counters-ripple counter-ring counter- Down counter Decade counter-.siso and SIPO Shift registers 25 Flip flop-rs flip flop - Clocked RS flip flop 26 D flip flops JK flip flop 27 JK as master slave flip flops 28 Registers- Shift registers- Shift left and Shift right Malvino A.P.and registers Leach D.P.,Digital 29 Counters-Synchronous Principles and counters Applications, 4 th 30 Asynchronous counters Edition, McGraw Hill, Ripple counter 32 Ring counter 33 Down counter 34 Decade Counter
4 35 SISO register 36 SIPO register UNIT IV - ARCHITECTURE AND PROGRAMMING OF MICROPROCESSOR Architecture of - Register organization of - Accumulator- General purpose Registers- Special purpose Registers - Bus structure (address, data and control buses) -Control signals-pin configuration of -Arithmetic and logic units-flags (zero, sign, parity, carry, auxiliary carry) - Addressing modes (register, Immediate, direct, indirect, implicit) of. 37 Architecture of various electrodes 38 Architecture of 39 Register organization of 40 Accumulator- General purpose Registers- Special purpose Registers 41 Bus structure (address, data and control buses) - Ramesh Goyankar, biosignal recording techniques 42 Control signals Pin configuration of Microprocessor Architecture- Programming and biosignal recording techniques 43 Pin configuration of Applications, 44 Arithmetic and logic units- Flags (zero, sign, parity, Prentice Hall, shock hazards carry, auxiliary carry) 45 Arithmetic and logic units- Flags (zero, sign, parity, carry, auxiliary carry) 46 Addressing modes (register, Immediate, direct, indirect, implicit) of
5 47 Addressing modes (register, Immediate, direct, indirect, implicit) of 48 Addressing modes (register, Immediate, direct, indirect, implicit) of UNIT V - INSTRUCTION SET OF MICROPROCESSOR Instruction Set-Types of instructions- Based on the number of bytes of operations-data transfer instructions - Arithmetic and logic instructions Branch instructions-subroutines-stack I/O instructions-machine cycle- Halt and Wait state- Timing diagram for opcode fetch- Memory read and write cycle Assembly language programming-simple programs using arithmetic and logic operations- Interrupts-Maskable and Non maskable interrupts. 49 Instruction Set-Types of instructions- Based on the various electrodes number of bytes of operations-data transfer instructions 50 Arithmetic and logic instructions Ramesh Goyankar, 51 Arithmetic and logic Microprocessor instructions Architecture- 52 Branch instructions Programming and Applications, 53 Subroutines Prentice Hall, biosignal recording techniques 54 Stack biosignal recording techniques 55 I/O instructions 56 Timing diagram for shock opcode fetch- Memory hazards read and write cycle
6 57 Assembly language programming-simple programs using arithmetic and logic operations 58 Assembly language programming-simple programs using arithmetic and logic operations 59 Interrupts-Maskable and Non maskable interrupts. 60 Interrupts-Maskable and Non maskable interrupts. Faculty Incharge HOD-Dept.Physics and Nanotechnology
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