ECE 551: Digital System *

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ECE 551: Digital System * Design & Synthesis Lecture Set 5 5.1: Verilog Behavioral Model for Finite State Machines (FSMs) 5.2: Verilog Simulation I/O and 2001 Standard (In Separate File) 3/4/2003 1 Explicit and Implicit Models Explicit - declares a state register that stores the FSM state Implicit - describes state implicitly by using multiple event controls Mealy versus Moore types 3/4/2003 3 ECE 601 - Digital System Design & Synthesis Lecture 5.1 - Behavioral Models for Finite State Machines (FSMs) Explicit and Implicit Models Types of Explicit Models Examples of Explicit Models Implicit Model Example of Implicit Model Combined Datapath and Control Modeling Example of Combined Model 3/4/2003 2 Explicit FSM Building Blocks Block Continuous Procedural State register X Next state logic X X Output logic X X Output register X Combinations Next state & output logic Next state logic & state register State register & output register Connection Type Moore Mealy 3/4/2003 4

Types of Explicit Models State register - Combinational next state and output logic State register - Combinational next state logic - Combinational output logic State register - Combinational next state logic - Registered output logic 3/4/2003 5 State register - Combinational next state logic - Combinational output logic Mealy Next State Output 3/4/2003 7 State register - Combinational next state and output logic Next State and Output 3/4/2003 6 State register - Combinational next state and output logic - Output register Output Register Next State and Output 3/4/2003 8

State register - Combinational next state logic - Registered output logic Mealy Output Register Next State Output 3/4/2003 9 FSM Example: - Next State Output - 1 module fsm_sr_ns_o (clk, reset, a, b, Y, Z); output Y, Z; reg Y, Z; if (reset) state <= S0; state <= next_state; //continued on next slide 3/4/2003 11 FSM Example: State Diagram a = 0 b = 0 a and b are X, unless specified otherwise Y and Z are 0, unless specified otherwise. S0 a = 1/ Z = 1 S1 Y= 1 reset = 1 b = 1/ Z = 1 S2 3/4/2003 10 FSM Example: - Next * State Output - 2 //next state logic S0: if (a) next_state = S0; S1: if (b) next_state = S2; S2: next_state = S0; default: next_state = 2 bx; case //output logic Z = 0, Y = 0; /* fixes default output values;avoids latches*/ S0: if (a) Z = 1; S1: Y = 1; if (b) Z = 1; default: Y = 1 bx; Z = 1 bx; case module 3/4/2003 12

FSM Example: - Next State & Output 1 module fsm_sr_nso (clk, reset, a, b, Y, Z); output Y, Z; reg Y, Z; if (reset) state <= S0; state <= next_state; //continued on next slide 3/4/2003 13 Verilog - - Next State and Output - Output Register If delay of the output for one clock cycle acceptable Output register can simply be added Same output logic can feed output flip-flop inputs as fed combinational outputs If outputs are to obey specifications on a clock cycle specific basis, i. e., are not delayed Then the output flip-flop D-input functions must be defined one cycle earlier than the normal combinational output. Can be done for Moore-type FSM outputs Mealy-type outputs can be handled only by modification of FSM. 3/4/2003 15 FSM Example: - Next State & Output - 2 //next state & output logic Y = 0; Z = 0; S0: if (a) Z = 1; next_state = S0; S1: Y = 1; if (b) next_state = S2; Z = 1; S2: next_state = S0; default: next_state = 2 bx; case module 3/4/2003 14 FSM Example - - Next State & Output - Output Register Original Combinational: Y = S1 b = 0 S0 a = 1 S1 Y= 1 New Sequential: Y(t+1) = S0 a + S1 ~b Impossible to do Z! 3/4/2003 16

Verilog - - Next State and Output - Output Register - General Transformation Method Next State Mealy Output Output Register 3/4/2003 17 FSM Example - - Next State and Output logic - Output Register - 1 module fsm_sr_ns_o_or (clk, reset, a, b, Y, Z); output Y, Z; reg Y, Z; if (reset) state <= S0; Y <= 0; state <= next_state; Y <= next_y; //continued on next slide 3/4/2003 18 FSM Example - - Next State & Output - Output Register - 2 //next state logic S0: if (a) next_state <= S1; next_state <= S0; S1: if (b) next_state = S2; S2: next_state = S0; default: next_state = 2 bx; case //output logic Next_Y = 0; Z = 0; /* fixes default output value;avoids latch*/ S0: if (a) Next_Y = 1; Z = 1; /* Z cannot be a registered output */ S1: if (!b) Next_Y = 1; Z = 1; case Combined Datapath & Control Modeling For higher level modeling, easier to visualize function Next State, Datapath & Output 3/4/2003 module 19 3/4/2003 20 State & Datapath Registers Output Registers Registered Combinational

FSM Example - Combined Datapath & Control Modeling Assume for the running FSM Example that: The example circuit interacts with a datapath consisting of a 4-bit up counter COUNT[3:0] a = 1 starts the circuit activity Y = 1 enables the counter to count up. b = 1 indicates that the counter has reached value 1111. Z = 1 toggles a flip-flop that is also changed asynchronously to 0 by signal reset. 3/4/2003 21 FSM Example: Combined - 2 case (state or a or b) S0: if (a) state <= S1; R <= ~ R; state <= S0; S1: COUNT <= COUNT + 1; if (b) state <= S2; R <= ~R; state <= S1; S2: state <= S0; default: state <= 2 bx; case module 3/4/2003 23 FSM Example: Combined - 1 module cntrl_dtpth (clk, reset, a, b, COUNT, R); output[3:0] COUNT; output R; reg R; reg [3:0] COUNT; if (reset) state <= S0; COUNT <= 0; R <= 0; 3/4/2003 22 Implicit Model More abstract representation Restricted to structures in which a given state can be entered from only one other state! Yields simpler code Description of reset behavior more complex 3/4/2003 24

Implicit Model (continued) Implicit model typically advances state by use of series of @(posedge clock) conditions Example: Mod 3 counter always @(posedge clock) count = 0; @(posedge clock) count = count + 1; @(posedge clock) count = count + 1; 3/4/2003 25 FSM Example: Implicit Model - 2 * always : main //S0* if (a) Y <= 1; while (!a) if (a) ; Y <= 1; //S1* if (b) Y <= 0; while (!b) if (b) ; Y <= 0; //S2* ; module 3/4/2003 27 FSM Example: Implicit Model - 1 \\This code is not synthsizable with FPGA Express (see *). module fsm_implicit (clk, reset, a, b, Y); output Y; //Z as Mealy output is not implementable reg Y; always@(posedge reset) if (reset) Y <= 0; disable main; //* 3/4/2003 26

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