Note: Closed book no notes or other material allowed, no calculators or other electronic devices.

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1 ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL Fall 2017 Exam Review Note: Closed book no notes or other material allowed, no calculators or other electronic devices. One page of Verilog examples is provided. Note: Unless otherwise stated all Verilog descriptions must be synthesizable. Question 1 [5 marks]: Write a Verilog description of a multiplexer with a tri-state output. The Entity/module description is shown below. When the output enable (oe) is 1 the output should be equal to the input selected by the select line (input a when sel = 1, and input b when sel = 0). When the output enable is 0 the output of the multiplexer should be high-impedance (tri-state). The start of the module description is: Module mux ( input sel, input oe, input [7:0] a, input [7:0] b, output [7:0] y } ECE574: Exam Review 1

2 Question 2 [10 marks]: Write two Verilog module descriptions of a 2-line to 4-line decoder with an enable input using: An always statement with either a CASE or an IF statement; A concurrent conditional operator statement. The function table of the decoder is: Inputs Outputs Enable Select G B A Y3 Y2 Y1 Y0 1 don t care don t care The start of the module description is: module decoder( input g, input a, input b, output [3:0] y Question 3 [10 marks]: An FPGA running off its own local 100MHz oscillator is connected to a GPS device in another system with its own clock. The GPS device generates a 1PPS (one pulse per second) signal that is high for approximately 10us duration that it sends to the FPGA. It is necessary for the FPGA to generate a single 10ns pulse each time it detects the 1PPS pulse. Write a synthesizable module description for the FPGA that will convert the 10us pulse from the GPS device clock domain into the 10ns pulse inside the FPGA. The start of the module description is provided: module gps_pps( input clk, // 100 MHz clock input pps_long, // 10us PPS signal from GPS output pps_short // 10ns version of PPS signal ECE574: Exam Review 2

3 Question 4 [15 marks]: Write a complete synthesizable Verilog description of the architecture of a 4- bit ALU that can perform the following operations on two 4-bit inputs (a_bus and b_bus) ADD, OR, AND, XOR to produce a 4-bit result (c_bus). The operation is determined by the value of two mode bits (M0 and M1). There is a provision for a carry in and a carry out for the add operation. The start of the module description is provided: module alu_4( input m0, input m1, input [3:0] a_bus, input [3:0] b_bus, input ci, output co, output [3:0] c_bus Question 5 [20 marks]: Design a system that consists of: A four state state-machine controlling the loading and left shift of an 8-bit shift-register. The state machine waits in S0 until it receives an active high input control signal; It then goes from S0 to S1; In S1 it loads an 8-bit shift register with the value 0x37; In S2 it sends a signal to start the shift register; It then waits in S3 until the shift register has completed shifting out the 8 bits The state machine then returns to state 0 and waits for the control signal to go high again How many flip-flops will be required to implement this system? Notes: For the state machine use a standard two always statements for your next_state and current_state signals. Assume an active high asynchronous reset and a positive edge triggered clk. Assume the control signal is high for no more than two clock cycles. Assume the shift register shifts left and the output is connected to the most significant bit. The start of the module description is provided: module sm_shift( input input input output clk, start, reset, shift ECE574: Exam Review 3

4 Question 6 [5 marks]: As part of a test bench write one always statement containing statements that will generate the following waveforms that repeat every 25 ns Question 7 [15 marks]: You are to write a Verilog description of a test bench to verify that a combinational circuit works correctly. You need to test for each possible input/output combination. The test bench should output an error message if any errors in operation are found. The function table of the combinational circuit is: INPUTS OUTPUTS A B C D IMPORTANT: place the inputs and output in a combined array and use a FOR.. LOOP to read the inputs and check the output. Use a clk signal to help synchronize the testing. Module description of combinational circuit (you do NOT need to write the synthesis description of the combinational circuit): module comb ( input a, input b, output c, output d ECE574: Exam Review 4

5 Question 8 [20 marks]: Write a Verilog model of an SRAM memory device with the following specifications: Address bus (A0 to A8) Data bus (D0 to D7) Active low control signals: CE, OE, WE Read operation (CE and OE valid): In the model output the correct data only after an access time of tacc ns from OE and CE. Write operation (CE and WE valid - write data on the rising edge of WE) In the model check that the address bus is stable for taddr ns and the data bus is stable for tsetup ns before the rising edge of WE. If they do not meet these requirements then issue appropriate error messages. Use parameters for the access, address, and setup times with default times of 50, 70, and 25 ns. ECE574: Exam Review 5

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ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL. Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS

ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS Note: Closed book no notes or other material allowed apart from the one