Digital VLSI Design with Verilog

Digital VLSI Design with Verilog

John Michael Williams Digital VLSI Design with Verilog A Textbook from Silicon Valley Polytechnic Institute Second Edition

John Michael Williams Wilsonville, OR USA Additional material to this book can be downloaded from http://extras.springer.com. ISBN 978-3-319-04788-1 ISBN 978-3-319-04789-8 (ebook) DOI 10.1007/978-3-319-04789-8 Springer Cham Heidelberg New York Dordrecht London Library of Congress Control Number: 2014938203 Springer International Publishing Switzerland 2014 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)

To my loving grandparents, William Joseph Young (ne Jung) and Mary Elizabeth Young (nee Egan) who cared for my brother Kevin and me when they didn t have to.

Preface to the Second Edition Like the first edition, this book is based on the lab exercises and order of presentation of a course developed and given by the author over a period of years at what is now Silicon Valley Polytechnic Institute, San Jose, California. To the author s best knowledge, this course was and still is the only one ever given which (a) presented the entire verilog language; (b) involved implementation of a full-duplex serdes simulation model; or (c) included design of a synthesizable digital PLL. The author wishes to thank the owner and CEO of Silicon Valley Polytechnic Institute, Dr. Ali Iranmanesh, for his patience and encouragement during the course development and in the preparation of this book. In the second edition, many minor typographical errors have been corrected, as have been several other errors newly discovered in the text and figures. Major upgrades in the second edition are: Modified Day 1 presentation making it more useful to verilog beginners Dozens of new figures Expansion or clarification of explanations on almost every page Upgrade of the simulation figures to be in color New coverage of the features of SystemVerilog and VerilogA/MS A new summary introduction to each chapter and lab exercise IEEE Stds references including SystemVerilog as well as verilog A new, optional lab checklist for recording learning progress As was done for the first edition, corrections, changes, and teaching information will be posted online at Scribd.

Table of Contents Chapter 1: Introductory Material... 1 1 Course Description... 1 2 Using this book... 1 2.1 Textbook Extras... 2 2.2 Performing the lab exercises... 3 2.3 Proprietary Information and Licensing Limitations... 3 3 Textbook References... 4 3.1 Supplementary Textbooks... 4 3.2 Interactive Language Tutorial... 4 3.3 Recommended Free Verilog Simulator... 5 3.4 Reading References... 5 4 Lab Checklist... 9 Chapter 2: Week 1 Class 1... 13 2 Today's Agenda:... 13 2.1 Introductory Lab 1... 14 2.2 Lab 1 Postmortem and Lecture... 25 2.3 Verilog vectors... 29 2.4 Logical (Boolean) Operators... 32 2.5 Bitwise Operators: Vectors and Reduction... 33 2.6 Operator Lab 2... 34 2.6.1 Lab postmortem... 35 2.7 First-Day Wrapup... 35 2.7.1 VCD File Dump... 35 2.7.2 SDF File Dump... 36 2.7.3 The Importance of Synthesis... 37 2.8 Additional Study... 37 Chapter 3: Week 1 Class 2... 39 3 Today's Agenda:... 39 3.1 More Language Constructs... 40 3.1.1 Traditional module header format... 40 3.1.2 Modern module header format... 40 3.1.3 Header formats contrasted... 41 3.1.4 Verilog comments... 43 3.1.5 always blocks... 44 3.1.6 Initial blocks... 44 3.1.7 Continuous assignments... 45 3.1.8 Vectors and vector values... 45 3.1.9 Parameters... 48 3.1.10 Commenting with verilog macroes... 48 3.2 Parameter and Conversion Lab 3... 50 3.2.1 Lab postmortem... 52 3.3 Procedural control... 53 3.3.1 Procedural Control Constructs... 53

x Table of Contents 3.3.2 Conditional Expression Operator... 53 3.3.3 Combinational and Sequential Logic... 54 3.3.4 Verilog Strings and Messages... 56 3.3.5 Shift Registers... 58 3.3.6 Reconvergence Design Note... 59 3.4 Nonblocking Control Lab 4... 60 3.4.1 Lab postmortem... 65 3.5 Additional Study... 66 Chapter 4: Week 2 Class 1... 67 4 Today's Agenda:... 67 4.1 Net Types, Simulation, and Scan... 67 4.1.1 Variables and Constants... 69 4.2 Identifiers... 69 4.3 Concurrent vs Procedural Blocks... 70 4.4 Miscellaneous Other Verilog Features... 70 4.5 Backus-Naur Format (BNF)... 70 4.6 Verilog Semantics... 70 4.7 Modelling Sequential Logic... 73 4.8 Design for Test (DFT): Scan Lab Introduction... 76 4.9 Simple Scan Lab 5... 79 4.9.1 Lab postmortem... 88 4.10 Additional Study... 88 Chapter 5: Week 2 Class 2... 89 5 Today's Agenda:... 89 5.1 PLLs and the SerDes Project... 89 5.1.1 Phase-Locked Loops... 89 5.1.2 A 1x Digital PLL... 90 5.1.3 Introduction to SerDes and PCI Express... 96 5.1.4 The SerDes of this course... 98 5.1.5 A 32 x Digital PLL... 100 5.2 PLL Clock Lab 6... 101 5.2.1 Note on Synthesis don t_touch... 108 5.2.2 Lab postmortem... 112 5.3 Additional Study... 113 Chapter 6: Week 3 Class 1... 115 6 Today's Agenda:... 115 6.1 Data Storage and Verilog Arrays... 115 6.1.1 Memory: Hardware and Software Description... 115 6.1.2 Definitions of Memory Size... 116 6.1.3 Verilog Arrays... 116 6.2 A Simple RAM Model... 119 6.2.1 Verilog Concatenation... 120 6.3 Memory Data Integrity... 120 6.3.1 Error Checking and Correcting (ECC)... 123 6.3.2 ECC from parity... 123 6.3.3 Parity for SerDes Frame Boundaries... 127

Table of Contents xi 6.4 Memory Lab 7... 128 6.4.1 Lab postmortem... 132 6.5 Additional Study... 132 Chapter 7: Week 3 Class 2... 133 7 Today's Agenda:... 133 7.1 Counter Types and Structures... 133 7.1.1 Introduction to Counters... 133 7.1.2 Terminology: Behavioral, Procedural, RTL, Structural... 135 7.1.3 Adder Expression vs Counter Statement... 137 7.1.4 Counter Structures... 137 7.1.5 Ripple Counter... 138 7.1.6 Carry Look-Ahead (Synchronous) Counter... 139 7.1.7 One-Hot and Ring Counters... 140 7.1.8 Gray Code Counter... 140 7.2 Counter Lab 8... 141 7.2.1 Lab postmortem... 146 7.3 Additional Study... 146 Chapter 8: Week 4 Class 1... 147 8 Today's Agenda:... 147 8.1 Contention and Operator Precedence... 147 8.1.1 Verilog Net Types and Strengths... 148 8.1.2 Verilog Strength Usage... 149 8.1.3 Race Conditions, Again... 151 8.1.4 Unknowns in Relational Expressions... 155 8.1.5 Verilog Operators and Precedence... 156 8.2 Digital Basics: Decoder and Three-State Buffer... 157 8.3 Strength and Contention Lab 9... 157 8.3.1 Strength Lab postmortem... 165 8.4 Back to the PLL and the SerDes... 165 8.4.1 Named Blocks... 165 8.4.2 The PLL in a SerDes... 166 8.4.3 The SerDes Packet Format Revisited... 168 8.4.4 Behavioral PLL Synchronization (language digression)... 168 8.4.5 Unsynthesizability of the Behavioral PLL Code... 177 8.4.6 Synthesizable, Pattern-Based PLL Synchronization... 177 8.5 PLL Behavioral Lock-In Lab 10... 178 8.5.1 Lock-in Lab postmortem... 181 8.6 Additional Study... 181 Chapter 9: Week 4 Class 2... 183 9 Today's Agenda:... 183 9.1 State Machine and FIFO design... 183 9.1.1 Verilog Tasks and Functions... 183 9.1.2 A Function For Synthesizable PLL Synchronization... 186 9.1.3 Concurrency by fork-join... 187 9.1.4 Verilog State Machines... 189 9.1.5 FIFO Functionality... 190 9.1.6 FIFO Operational Details... 192

xii Table of Contents 9.1.7 A Verilog FIFO... 197 9.2 FIFO Lab 11... 205 9.2.1 Lab postmortem... 209 9.3 Additional Study... 209 Chapter 10: Week 5 Class 1... 211 10 Today's Agenda:... 211 10.1 Rise-Fall Delays and Event Scheduling... 211 10.1.1 Types of Delay Expression... 211 10.1.2 Verilog Simulation Event Queue... 215 10.1.3 Simple Stratified Queue Example... 217 10.1.4 Event Controls... 220 10.1.5 Event Queue Summary... 221 10.2 Scheduling Lab 12... 222 10.2.1 Lab postmortem... 228 10.3 Additional Study... 229 Chapter 11: Week 5 Class 2... 231 11 Today's Agenda:... 231 11.1 Built-in Gates and Net Types... 231 11.1.1 Verilog Built-in Gates... 231 11.1.2 Implied Wire Names... 232 11.1.3 Net Types and Their Default... 233 11.1.4 Structural Use of Wire vs Reg... 234 11.1.5 Port and Parameter Syntax Note... 235 11.1.6 A D Flip-flop from SR Latches... 236 11.2 Netlist Lab 13... 239 11.2.1 Lab postmortem... 242 11.3 Additional Study... 242 Chapter 12: Week 6 Class 1... 245 12 Today's Agenda:... 245 12.1 Verilog Procedural Control Statements... 245 12.1.1 Verilog case Variants... 249 12.1.2 Procedural Concurrency... 253 12.1.3 Verilog Name Space... 257 12.2 Concurrency Lab 14... 258 12.2.1 Lab postmortem... 261 12.3 Additional Study... 261 Chapter 13: Week 6 Class 2... 263 13 Today's Agenda:... 263 13.1 Hierarchical Name Access... 263 13.1.1 Verilog Arrayed Instances... 266 13.1.2 generate Statements... 267 13.1.3 Conditional Macroes and Conditional generates... 267 13.1.4 Looping generate Statements... 269 13.1.5 generate Blocks and Instance Names... 269 13.1.6 A Decoding Tree with generate... 274

Table of Contents x iii 13.2 Generate Lab 15... 278 13.2.1 Lab postmortem... 284 13.3 Additional Study... 285 Chapter 14: Week 7 Class 1... 287 14 Today's Agenda:... 287 14.1 Serial-Parallel Conversion... 287 14.1.1 Simple Serial-Parallel Converter... 287 14.1.2 Deserialization by function and task... 289 14.2 Lab Preface: The Deserialization Decoder... 291 14.2.1 Some Deserializer Redesign An Early ECO.... 293 14.2.2 A Partitioning Question... 294 14.3 Serial-Parallel Lab 16... 295 14.3.1 Lab postmortem... 300 14.4 Additional Study... 300 Chapter 15: Week 7 Class 2... 301 15 Today's Agenda:... 301 15.1 UDP's, Timing Triplets, and Switch-level Models... 301 15.1.1 User-Defined Primitives (UDP's)... 301 15.1.2 Delay Pessimism... 305 15.1.3 Gate-Level Timing Triplets... 305 15.1.4 Switch-Level Components... 307 15.1.5 Switch-Level Net: The trireg... 312 15.2 Component Lab 17... 313 15.2.1 Lab postmortem... 321 15.3 Additional Study... 321 Chapter 16: Week 8 Class 1... 323 16 Today's Agenda:... 323 16.1 Parameter Types and Module Connection... 324 16.1.1 Summary of Parameter Characteristics... 324 16.1.2 ANSI Header Declaration Format... 324 16.1.3 Traditional Header Declaration Format... 324 16.1.4 Instantiation Formats... 325 16.1.5 Parameter Format Values... 325 16.1.6 ANSI Port and Parameter Options... 326 16.1.7 Traditional Module Header Format and Options... 326 16.1.8 defparam... 327 16.2 Connection Lab 18... 327 16.2.1 Connection Lab postmortem... 333 16.3 Hierarchical Names and Design Partitions... 333 16.3.1 Hierarchical Name References... 333 16.3.2 Scope of Declarations... 334 16.3.3 Design Partitioning... 335 16.3.4 Synchronization Across Clock Domains... 337 16.4 Hierarchy Lab 19... 340 16.4.1 Lab postmortem... 344 16.5 Additional Study... 344

xiv Table of Contents Chapter 17: Week 8 Class 2... 345 17 Today's Agenda:... 345 17.1 Verilog configurations... 345 17.1.1 Libraries... 345 17.1.2 Verilog Configuration... 346 17.2 Timing Arcs and specify Delays... 347 17.2.1 Arcs and Paths... 347 17.2.2 Distributed and Lumped Delays... 348 17.2.3 specify Blocks... 351 17.2.4 specparams... 352 17.2.5 Parallel vs. Full Path Delays... 353 17.2.6 Conditional and Edge-Dependent Delays... 354 17.2.7 Conflicts of specify with Other Delays... 356 17.2.8 Conflicts Among specify Delays... 356 17.2.9 Conflicts with SDF Delays... 357 17.3 Timing Lab 20... 357 17.3.1 Lab postmortem... 361 17.4 Additional Study... 361 Chapter 18: Week 9 Class 1... 363 18 Today's Agenda:... 363 18.1 Timing Checks... 363 18.1.1 Timing Checks and Assertions... 363 18.1.2 Timing Check Rationale... 364 18.1.3 The Twelve Verilog Timing Checks... 365 18.1.4 Negative Time Limits... 369 18.1.5 Timing Check Conditioned Events... 371 18.1.6 Timing Check Notifiers... 371 18.2 Pulse Filtering... 372 18.2.1 PATHPULSE Syntax... 373 18.2.2 specparam Improved Pessimism... 374 18.3 Miscellaneous time-related Types... 375 18.4 Timing Check Lab 21... 376 18.5 Additional Study... 380 Chapter 19: Week 9 Class 2... 381 19 Today's Agenda:... 381 19.1 The Sequential Deserializer... 381 19.2 PLL Redesign... 382 19.2.1 Improved VFO Clock Sampler... 383 19.2.2 Synthesizable Variable-Frequency Oscillator... 384 19.2.3 Synthesizable Frequency Comparator... 387 19.2.4 Modifications for a 400 MHz 1x PLL... 389 19.2.5 Wrapper Modules for Portability... 393 19.3 Sequential Deserializer I Lab 22... 393 19.3.1 Lab postmortem... 413 19.4 Additional Study... 413

Table of Contents xv Chapter 20: Week 10 Class 1... 415 20 Today's Agenda:... 415 20.1 The Concurrent Deserializer... 415 20.1.1 Dual-porting the Memory... 416 20.1.2 Dual-clocking the FIFO State Machine... 416 20.1.3 Upgrading the FIFO for Synthesis... 417 20.1.4 Upgrading the Deserialization Decoder for Synthesis... 417 20.2 Concurrent Deserializer II Lab 23... 418 20.2.1 Lab postmortem... 444 20.3 Additional Study... 444 Chapter 21: Week 10 Class 2... 445 21 Today's Agenda:... 445 21.1 The Serializer and The SerDes... 445 21.1.1 The SerEncoder Module... 446 21.1.2 The SerialTx Module... 447 21.1.3 The SerDes... 447 21.2 SerDes Lab 24... 447 21.2.1 Lab postmortem... 467 21.3 Additional Study... 467 Chapter 22: Week 11 Class 1... 469 22 Today's Agenda:... 469 22.1 Design for Test (DFT)... 469 22.1.1 Design for Test Introduction... 469 22.1.2 Assertions and Constraints... 470 22.1.3 Observability... 470 22.1.4 Coverage... 471 22.1.5 Corner-Case vs. Exhaustive Testing... 472 22.1.6 Boundary Scan... 473 22.1.7 Internal Scan... 475 22.1.8 BIST... 476 22.1.9 Design For Test Summary... 479 22.2 Scan and BIST Lab 25... 479 22.2.1 Lab postmortem... 489 22.3 DFT for a Full-Duplex SerDes... 490 22.3.1 Full-Duplex SerDes... 490 22.3.2 Test Logic Questions... 491 22.4 Tested SerDes Lab 26... 491 22.4.1 Lab postmortem... 505 22.5 Additional Study... 505 Chapter 23: Week 11 Class 2... 507 23 Today's Agenda:... 507 23.1 SDF Back-Annotation... 507 23.1.1 Back-Annotation... 507 23.1.2 SDF Files in Verilog Design Flow... 508 23.1.3 Verilog Simulation Back-Annotation... 509

xvi Table of Contents 23.2 SDF Lab 27... 509 23.2.1 Lab postmortem... 515 23.3 Additional Study... 515 Chapter 24: Week 12 Class 1... 517 24 Today's Agenda:... 517 24.1 Wrap-up: The Verilog Language... 517 24.1.1 Verilog-1995 vs 2001 (or 2005) Differences... 517 24.1.2 Verilog Synthesizable Subset Review... 517 24.1.3 Constructs Not Exercised in this Course... 518 24.1.4 List of all verilog system tasks and functions... 520 24.1.5 List of all verilog compiler directives... 521 24.1.6 Verilog PLI... 521 24.2 Continued Lab Work (Lab 23 or later)... 523 24.3 Additional Study... 523 Chapter 25: Week 12 Class 2... 525 25 Today's Agenda:... 525 25.1 Deep-Submicron Problems and Verification... 525 25.2 Deep Submicron Design Problems... 525 25.3 The Bigger Problem... 527 25.3.1 Modern Verification... 528 25.3.2 Formal Verification... 529 25.3.3 Nonlogical Factors On The Chip... 529 25.4 System Verilog... 531 25.4.1 Some Features of SystemVerilog... 531 25.4.2 SystemVerilog Conclusion... 538 25.5 Verilog-AMS... 538 25.5.1 Introduction... 538 25.5.2 Relationship to Other Languages... 539 25.5.3 Analogue Functionality Overview... 540 25.5.4 Analogue and Digital Interaction... 540 25.5.5 Example: VAMS DFF... 541 25.5.6 Benefits of VAMS... 541 25.6 Continued Lab Work (Lab 23 or later)... 542 25.7 Additional Study... 542 Index... 543