A Tutorial Introduction 1

Transcription

1 Preface From the Old to the New Acknowledgments xv xvii xxi 1 Verilog A Tutorial Introduction 1 Getting Started A Structural Description Simulating the binarytoeseg Driver Creating Ports For the Module Creating a Testbench For a Module Behavioral Modeling of Combinational Circuits Procedural Models Rules for Synthesizing Combinational Circuits Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines Rules for Synthesizing Sequential Systems Non-Blocking Assignment ("<=") Module Hierarchy The Counter A Clock for the System Tying the Whole Circuit Together Tying Behavioral and Structural Models Together Logic Synthesis 35 Overview of Synthesis Register-Transfer Level Systems Disclaimer Combinational Logic Using Gates and Continuous Assign Procedural Statements to Specify Combinational Logic The Basics

2 viii The Verilog Hardware Description Language Complications Inferred Latches Using Case Statements Specifying Don' t Care Situations Procedural Loop Constructs Inferring Sequential Elements Latch Inferences Flip Flop Inferences Inferring Tri-State Devices Describing Finite State Machines An Example of a Finite State Machine An Alternate Approach to FSM Specification Finite State Machine and Datapath A Simple Computation A Datapath For Our System Details of the Functional Datapath Modules Wiring the Datapath Together Specifying the FSM on Logic Synthesis Behavioral Modeling 73 Process Model If-Then-Else Where Does The ELSE Belong? The Conditional Operator Loops Four Basic Loop Statements Exiting Loops on Exceptional Conditions Multi-way Branching If-Else-If Case Comparison of Case and If-Else-If Casez and Casex Functions and Tasks Tasks Functions A Structural View Rules of Scope and Hierarchical Names Rules of Scope Hierarchical Names

3 ix Concurrent Processes 109 Concurrent Processes Events Event Control Statement Named Events The Wait Statement A Complete Producer-Consumer Handshake Comparison of the Wait and While Statements Comparison of Wait and Event Control Statements A Concurrent Process Example A Simple Pipelined Processor The Basic Processor Synchronization Between Pipestages Disabling Named Blocks Intra-Assignment Control and Timing Events Procedural Continuous Assignment Sequential and Parallel Blocks Module Hierarchy 143 Module Instantiation and Port Specifications Parameters Arrays of Instances Generate Blocks

4 x The Verilog Hardware Description Language 6 Logic Level Modeling 157 Introduction Logic Gates and Nets Modeling Using Primitive Logic Gates Four-Level Logic Values Nets A Logic Level Example Continuous Assignment Behavioral Modeling of Combinational Circuits Net and Continuous Assign Declarations A Mixed Behavioral/Structural Example Logic Delay Modeling A Gate Level Modeling Example Gate and Net Delays Specifying Time Units Minimum, Typical, and Maximum Delays Delay Paths Across a Module of Assignment Statements Cycle-Accurate Specification 195 Cycle-Accurate Behavioral Descriptions Specification Approach A Few Notes Cycle-Accurate Specification Inputs and Outputs of an Always Block Input/Output Relationships of an Always Block Specifying the Reset Function Mealy/Moore Machine Specifications A Complex Control Specification Data and Control Path Trade-offs Introduction to Behavioral Synthesis

5 xi 8 Advanced Timing 211 Verilog Timing Models Basic Model of a Simulator Gate Level Simulation Towards a More General Model Scheduling Behavioral Models Non-Deterministic Behavior of the Simulation Algorithm Near a Black Hole It's a Concurrent Language Non-Blocking Procedural Assignments Contrasting Blocking and Non-Blocking Assignments Prevalent Usage of the Non-Blocking Assignment Extending the Event-Driven Scheduling Algorithm Illustrating Non-Blocking Assignments User-Defined Primitives 239 Combinational Primitives Basic Features of User-Defined Primitives Describing Combinational Logic Circuits Sequential Primitives Level-Sensitive Primitives Edge-Sensitive Primitives Shorthand Notation Mixed Level- and Edge-Sensitive Primitives

6 xii The Verilog Hardware Description Language 10Switch Level Modeling 251 A Dynamic MOS Shift Register Example Switch Level Modeling Strength Modeling Strength Definitions An Example Using Strengths Resistive MOS Gates Ambiguous Strengths Illustrations of Ambiguous Strengths The Underlying Calculations The minisim Example Overview The minisim Source Simulation Results Projects 283 Modeling Power Dissipation Modeling Power Dissipation What to do Steps A Floppy Disk Controller Introduction Disk Format Function Descriptions Reality Sets In Everything You Always Wanted to Know about CRC's Supporting Verilog Modules Appendix A: Tutorial Questions and Discussion 293 Structural Descriptions Testbench Modules Combinational Circuits Using always

7 xiii Sequential Circuits Hierarchical Descriptions Appendix B: Lexical Conventions 309 White Space and Comments Operators Numbers Strings Identifiers, System Names, and Keywords Appendix C: Verilog Operators 315 Table of Operators Operator Precedence Operator Truth Tables Expression Bit Lengths Appendix D: Verilog Gate Types 323 Logic Gates BUF and NOT Gates BUFIF and NOTIF Gates MOS Gates Bidirectional Gates CMOS Gates Pullup and Pulldown Gates Appendix E: Registers, Memories, Integers, and Time 329 Registers Memories Integers and Times Appendix F: System Tasks and Functions 333 Display and Write Tasks Continuous Monitoring Strobed Monitoring File Output Simulation Time Stop and Finish Random Reading Data From Disk Files Appendix G: Formal Syntax Definition 339 Tutorial Guide to Formal Syntax Specification 339

8 xiv The Verilog Hardware Description Language Source text Declarations Primitive instances Module and generated instantiation UDP declaration and instantiation Behavioral statements Specify section Expressions General Index 373