THERMAL EXPLORATION AND SIGN-OFF ANALYSIS FOR ADVANCED 3D INTEGRATION Cristiano Santos 1, Pascal Vivet 1, Lee Wang 2, Michael White 2, Alexandre Arriordaz 3 DAC Designer Track 2017 Pascal Vivet Jun/2017 1 CEA-LETI, Grenoble (FR) 2 Mentor, A Siemens Business, Fremont (USA) 3 Mentor, A Siemens Business, Grenoble (FR)
THERMAL CHALLENGES IN 3D IC DESIGNS design & analysis should be considered throughout the design flow to avoid thermal-related issues Early thermal exploration for die and package co-design Accurate sign-off analysis prior to tape-out and package fabrication issues in 3D ICs: Higher power density Heat is removed through stacked dies Die bonding vertical thermal resistance Thinned dies lateral thermal resistance Non-homogeneous distribution of 3D connections 3D stacked IC -related issues 2
EXISTING SOLUTIONS FOR THERMAL ANALYSIS OF 3D ICS Traditional package-centric approaches are no longer valid in advanced technologies and modern applications Hotspots become prominent as integration density increases: Tradeoff between hotspot size, power density, and substrate thickness Die-level thermal analysis is a must in scenarios like: 2.5D/3D ICs, thinned substrates or non-uniform power distribution Main gaps in the existing thermal analysis flows: Complex setup with no support for the ASIC design flow in traditional FEM/CFD multiphysics simulation tools Packaged 3D IC with nonuniform power distribution Limited/simplistic support for package and boundary conditions, and/or no support for 3D integrationin the ASIC design flow 3
OUTLINE Heat dissipation issues in 3D ICs issues in 3D ICs Existing solutions for thermal analysis of 3D ICs Proposed thermal modeling methodology Overview of Project Sahara Key features & differentiators aware package co-design & sign-off thermal analysis INTACT: 3D IC for massive parallel computing Early 3D partitioning and package co-design Sign-off thermal analysis Main achievements Summary & Overall conclusions Your 4 Initials, Presentation Title, Month Year 4
PROPOSED THERMAL ANALYSIS FLOW Objective is to enable die-leveldetailed thermal analysis with accurate package and boundary conditions: Compatible with 3D integration technologies Fully integrated into the ASIC design flow Package Design Physical Implementation exploration : 3D partitioning, die assembly, block and TSV floorplan, interface layer design, package selection Sign-off analysis : Fine-grain power maps, detailed package and die layout representation, package material optimization Package selection Package optimization exploration Sign-off Partitioning Floorplaning Place&CTS Signal routing Timing closure Sign-off Package-Die Design Flow 5
THERMAL MODELING METHODOLOGY Material Properties Package model & air flow conditions Optional for higher accuracy LEF/DEF GDSII Constraints IPF parser 3D Geometry Specification Die-level Power Maps Project Sahara Static and Transient Simulations Gate-level / Device-level Power Analysis 3D IC/package Assembly View Violations Maps Waveforms Detailed & Summary reports Results Database 6
ACCURATE DIE-LEVEL THERMAL ANALYSIS FLOW How to account for fine-grain details while performing a complete chip-package-system thermal simulation? EFFP: thermal property extraction from layout Compute equivalent anisotropic thermal properties to reduce thermal model complexity Dramatic reduction of geometry count leads to significant simulation speed up Adjustable granularity for accuracy vs. CPU time tradeoff Areas with fine-grain structures Areas with anisotropic thermal propertites after EFFP EFFP: reduces model complexity and accelerates simulations Support for IPF: from gate-level/device-level power analysis Fine-grain power maps to capture hotspot effects Automatic compression of power sources in very high instance count designs to accelerate simulation Automation Automatic constraint checks to avoid error-prone and timeconsuming manual verification of thermal constraints Automatic gridding and automatic time step generation Hotspots in non-uniform power distribution captured in gate-level thermal analysis 7
INTACT: A 3D IC FOR MASSIVE PARALLEL COMPUTING 28FDSOI chiplets (6x) 3D-stacked over a 65nm active interposer 16 MIPS cores per chiplet thus offering a total 96-core compute fabric µ-bumps Ø 10 µm Pitch 20 µm Power budget (worst-case): 6x 9W + 18W = 72W Chiplet Active interposer «Active» Interposer : cost and feature driven. Which added value? Heterogeneous 3D - Advanced tech node for computation within chiplets - Mature tech node for communication/power/dft/etc Chip-to-Chip Interconnect - Hierarchical NoC, for energy efficient communications System IOs - With Interposer, for off-chip memory accesses Power Management - Embedded power supply, without any external passives 8 TSV Ø 10µm Height 100µm [D. Dutoit, 3DASIP 16] 8
THERMAL-AWARE 3D PACKAGE CO-DESIGN Early thermal-aware 3D partitioning Chiplet placement, die-to-die interface Coarse-grain power maps Package Design Package selection exploration Physical Implementation Partitioning Floorplaning Package & heat sink co-design in complex air flow conditions Optimization of TIM layers Copper lid and heat sink design Package optimization Sign-off Place&CTS Signal routing Timing closure Sign-off 9 Package: 3D chip stack + BGA substrate + Cu lid -aware 3D partitioning Heat sink design 9
DETAILED SIGN-OFF THERMAL ANALYSIS Automatic model simplification using EFFP to account for 150K+ fine-grain 3D structures, such as TSVs and µ-bumps, and very complex BEOL (9 layers) Revealed important anisotropic thermal properties of the die-to-die layers Compressed power maps from sign-off gate-level power analysis Power map conversion from IPF files (3M instances each) Captured the thermal impact of heterogeneous hotspots in multiple power application scenarios Original detailed layout (BEOL) Detailed gate-level power maps Chiplet: Calibre thermal results database 10
MAIN ACHIEVEMENTS 11 Using Project Sahara in a complex 3D-IC design enabled: -aware 3D partitioning and early package co-design Sign-off thermal analysis in a design with 20M instances and 150K+ 3D elements EFFP and smart power map conversion features reduced simulation time from many hours/days to less than an hour: property extraction (EFFP): 30min Power map generation from IPF: less than 2min (per application scenario) simulation of complete packaged 3D IC: 50min Key features: Steady-state & Transient analyses Support for ASIC design flows LEF/DEF, GDS and OASIS layout databases Support IPF format from gate-level power simulations Integration within the Calibre tool suite Automation automatic constraint checks, gridding and time step generation Accurate package modeling and air flow conditions 11
SUMMARY & OVERALL CONCLUSIONS Package-centric approaches are no longer valid in advanced technologies and modern applications, mainly in advanced 3D ICs Project Sahara is a powerful and flexible platform enabling accurate thermal analysis: Detailed die-level thermal modeling compatible with advanced 3D integration technologies Complete chip-package-system thermal simulation with realistic boundary conditions Easy integration with standard ASIC design flows EFFP feature useful for accurate modeling of very complex designs Tight integration with FloTHERM for detailed thermal assessment Silicon correlation results: Avg. error ~2% / Worst-case error ~4% (steady-state) 12 12
Acknowledgements Part of this work was funded thanks to the French national program Programme d Investissements d Avenir, IRT Nanoelec ANR-10-AIRT-05 Leti, technology research institute Commissariat à l énergie atomique et aux énergies alternatives Minatec Campus 17 rue des Martyrs 38054 Grenoble Cedex France www.leti.fr
SILICON CORRELATION RESULTS: 3DNOC TESTCASE 3DNOC : a logic-on-logic multicore Heterogeneous multi-core architecture (4G-Telecom application) Stack 2 similar dies on top of each others 65nm technology, 2000 TSVs & micro-bumps, 70mm2 3D Characterization Heaters & Sensors and characterization flow model and simulation of the 3D Stack 3DNOC Circuit, with 2 layers : 8 Heaters (up to 8 Watts) 7 Sensors per die (1 C accuracy after calibration) [P.Vivet et al, JSSC17] 15 C difference between bottom & top dies 3DNOC Model Simulation Measurement correlation: - 2% error for steady state analysis - Similar time constant for transient analysis 3DNOC Maps (bottom & top dies) 14