ECE520 VLSI Design. Lecture 1: Introduction to VLSI Technology. Payman Zarkesh-Ha

Transcription

1 ECE520 VLSI Design Lecture 1: Introduction to VLSI Technology Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment Slide: 1

2 Course Objectives We will focus mainly on CMOS integrated circuits There will be a design project assigned including: Schematic design using S-Edit Spice simulations and design verification Layout design using L-Edit (including LVS and DRC) Circuit extract and spice simulation (again) Project will be done by groups of 3-4 students Project grade will be based on: Quality of report Performance (speed/delay) Power dissipation Layout area There will be a 10% extra credit for any design that beats certain criteria for layout area, performance, or power consumption Slide: 2

3 Textbook and References Main textbook: Digital Integrated Circuits by J. M. Rabaey et al. (2nd edition) Other reference books: Physical Design of CMOS Integrated Circuits Using L-Edit by J. Uyemura Design of High-Performance Microprocessor Circuits, by A. Chandrakasan Lecture Notes: combination of slides and discussions Slides will be posted on the class webpage Class webpage: Reference papers posted on the class webpage Slide: 3

4 Grading Policy Your grade in the course will be comprised of: Homework (25%) Project (25%) Midterm Exam (25%) Final Exam (25%) Final letter grade will be based on curve and class performance No makeup exam Slide: 4

5 Homework Policy Homework will be on weekly basis and is setup for the project Learn CAD tools and basic circuits Require lab work Solutions will be posted on the class website as soon as I can Late homework and projects have 20% per day credit penalty Slide: 5

6 Class Project & Tools Use of CAD tools will be required for most assignments. Get yourself familiarized with the tools from today! This is a project oriented course. Be prepared for extensive lab work! We will be using L-Edit for our VLSI project all Tanner tools including L-Edit, S-Edit, T-SPICE, LVS, and W-Edit are installed on all machines in ECE 211 Lab The tools can also be installed on your own computer for the project use for more information about these tools, please visit class website We will be using Global Foundries 0.18um (7RF) for our process Selected projects will be submitted for manufacturing by MOSIS for more information about this process please visit Slide: 6

7 Projects Manufactured by MOSIS in 2009 Test Chip 1 Test Chip 2 Slide: 7

8 Projects Manufactured by MOSIS in 2010 Die Photograph of the Test Chip Slide: 8

9 Projects Manufactured by MOSIS in 2011 Die Photograph of the Test Chip 2 Slide: 9

10 Projects Manufactured by MOSIS in 2012 Slide: 10

11 Class Schedule Slide: 11

12 Reading Assignment Today we will review Chapter 1 and some more Introduction and history Our next class will be on Chapter 3 (MOS Physics) Skim through Diodes but focus on Section (diode transient behavior) Study Section 3.3 (MOS transistor) thoroughly We will get back to Chapter 2 (Manufacturing Process) later Slide: 12

13 VLSI Design Flow The goal of VLSI designers is to design a circuit block that meets the following objectives: Maximize speed or performance Minimize power consumption Minimize area Maximized robustness Methods that they use are: Circuit design, transistor sizing Use of new architectures, clock gating, etc Choice of circuit style, efficient layout design Interconnect design and optimization Slide: 13

14 VLSI Design Approaches Gate Arrays (Old technology, but still attractive) Pre-fabricated chips containing transistors and local wiring Upper level wires added to implement design Rapid design, but very sub-optimal, slow, and usually high power consumption Standard Cells (Used for ASIC design) Cells in a library with fixed sizes Cells pre-characterized for delay and power Design is fast and layout is done automatically Better performance, in the range of several 100 s MHz Custom Design (Used for Microprocessor design) Optimal circuit design and sizes Extensive design verification required Slowest, but densest layout design Best performance, in the range of 1-5 GHz Slide: 14

15 VLSI Design Tools Synthesis Logic, micro-architecture, automatic physical generation Static Analysis Design rule checking (DRC) Circuit extraction Timing analysis Test generation (ATPG) Dynamic Analysis Architectural simulation Logic simulation Circuit simulation (SPICE) Test verification Slide: 15

16 High Level VLSI Design Steps System Requirements Logic Design & Synthesis VLSI Design & Layout Design Verification Pass Mask Generation Silicon Manufacturing Process Wafer Test (sort) Package Final Test Slide: 16

17 Introduction Beginning of the Computer: ENIAC, the first electronic computer (1946) 333 integer multiplication/second A six-week run was equivalent to 100 person-years of manual computation Program resides in the wired connections Slide: 17

18 Intel 4004 Microprocessor um NMOS-only 2300 transistors 1 MHz Slide: 18

19 Intel Technology Advancement Slide: 19

20 Moore s Law In 1965, Gordon Moore (founder of Intel) had a very interesting observation. He noticed that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology would double its effectiveness every 18 months. Slide: 20

21 Moore s Law for Intel Microprocessors Source: Slide: 21

22 Moore s Law in Travel Industry Slide: 22

23 Projected Wafer in 2000, circa 1975 Moore was not always accurate Slide: 23

24 Die size (mm) Die Size Growth P6 Pentium proc ~7% growth per year ~2X growth in 10 years Year Die size has grown by 14% to satisfy Moor s law, BUT the growth is almost stopped because of manufacturing and cost issues Slide: 24

25 Frequency (Mhz) Clock Frequency Doubles every 2 years P6 Pentium proc Year Lead microprocessors frequency doubles every 2 year, BUT the growth is slower because of power dissipation issue Slide: 25

26 CMOS Scaling Scenario Slide: 26

27 CMOS Scaling Calculation 14 -> 10 -> Slide: 27

28 The Evolution of Foundry Market Slide: 28

29 Intel s 22nm and 14nm Fin-FET Technology Slide: 29

30 65nm SRAM Memory Cell 10 million of these transistors could fit in a square millimeter about the size of the tip of a ballpoint pen Slide: 30

31 MOS in 65nm of Core Due Processor Distance between Si atoms = 5.43 ºA No. of atoms in channel = 35 nm / nm = 64 Atoms! Problem: Uncertainty in transistor behavior and difficult to control variation! Slide: 31

32 Gate Insulator Thickness 1.2 nm SiO 2 ~ 5 atomic layers! Problem: Electrons can easily jump over the 5 atomic layers! This is known as leakage current Slide: 32

33 Benefit of Smaller Transistors 1) More transistors in the same foot-print 2) More functionality 3) Reduced cost per function 4) Faster devices and higher performance 5) Lower switching energy per transistor Slide: 33

34 Transistor Scaling Challenges 1) Feature sizes down to few atomic layers 2) Increase uncertainty of transistor behavior 3) Increase leakage power consumption 4) Difficult to maintain performance enhancement 5) Thermal limit issue Slide: 34

35 New Method to Deal with Scaling Slide: 35

36 Far-future Alternative Logic Devices 1) Spintronics (spin-based electronics) 2) Quantum Computing 3) DNA Computing 4) Optical Computing Slide: 36

37 Power (Watts) Power Dissipation 100 P6 Pentium proc Year Lead microprocessors power dissipation continue to increase, BUT it is getting too hard (and expensive) to keep up Slide: 37

38 Power Density Problem Power density too high to keep junction at low temperature. Power reaching limits of air cooling. Slide: 38

39 Heat Management Consideration Slide: 39

40 Power Consumption Scenario Slide: 40

41 Some Calculations! Power = 115 Watts Supply Voltage = 1.2 V Supply Current = 115 W / 1.2 V = 96 Amps! Problem: Current density becomes a serious problem! This is known as electromigration Note: Fuses used for household appliances = 15 to 40 Amps Slide: 41

42 Another Calculations! Power = 115 Watts Chip Area = 2.2 Cm 2 Heat Flux = 115 W / 2.2 Cm 2 = 50 W/Cm 2! Problem: Heat flux is another serious issue! Notes: Heat flux in iron = 0.2 W/Cm 2 Heat flux in frying pan = 10 W/Cm 2 Slide: 42

43 Method of Heat Management 1) Proper heat removal system (expensive) 2) Improve manufacturing for low power MOS 3) Architectural solutions (multi-cores) Slide: 43

44 Hitachi Water Cooling Laptop Slide: 44

45 Manufacturing Solution Slide: 45

46 Architectural Solution Slide: 46

47 Architectural Solution Slide: 47

48 Interconnect Architecture Metal stack over Silicon Real wiring cross section photograph Slide: 48

49 Interconnect Scaling Scenario Technology 45 nm (2008) 35 nm (2010) 22 nm (2012) Wire width 45 nm 32 nm 22 nm Wire Thickness Total Number of Wires Total wire length 80 nm 60 nm 40 nm 150 Million 300 Million 600 Million 1.4 mile 2 mile 2.8 mile Slide: 49

50 V dd R int Delay versus Interconnect Scaling C b C b C l /2 C l /2 V dd R int V dd C b C b V d V dd V d V dd Delay R int C b Slide: 50

51 Interconnect versus Gate Delay Gate Interconnect Al & SiO 2 Interconnect Cu & Low [Bohr, IEDM 95] Al 3.0 cm Cu SiO = 4.0cm SiO Al = 4.0 Thick Al Line 43 Long Low = 2.0 Al & Cu 0.8 Thick Al & CU Line 43 Long Slide: 51

52 Interconnect Challenges 1) Slows down with scaling 2) Consume more power 3) Generate more heat 4) Electromigration Slide: 52

53 Far-future Alternative Interconnects 1) Carbon nanotubes 2) Optical Interconnect 3) Molecular wires 4) Spintronics interconnect system Slide: 53

54 Process Defects and Yield Loss Process Defect Causing Fault (Short) Original layout A particle or a process defect Short defect Slide: 54

55 Process Defects and Yield Loss Process Defect Causing Fault (Opens) Original layout A particle or a process defect open defect Slide: 55

56 Process Defect Photograph Slide: 56

57 Manufacturing Issues 1) Smaller feature size requires ultra-clean manufacturing facility (expensive) 2) Because of the increase in complexity, defects could drastically reduces the manufacturing yield (% of working chips) 3) There are much more issues related to Design for Manufacturability (DFM) Slide: 57

58 Die Cost Single die Wafer Going up to 12 (30cm) From Slide: 58

59 Cost per Transistor cost: -per per-transistor Fabrication capital cost per transistor (Moore s law) Cost per transistor is reducing exponentially following Moor s law. Slide: 59

60 Yield Diesper wafer No. of good chips per wafer Y 100% Totalnumber of chipsper wafer Wafer cost Die cost Diesper wafer Die yield wafer diameter/2 die area 2 wafer diameter 2 die area Slide: 60

61 Defects and Die Cost die yield 1 defectsper unit area die area is approximately 3 die cost f 4 (die area) Slide: 61

62 Some Examples (1994) Chip Metal layers Line width Wafer cost Def./ cm 2 Area mm 2 Dies/ wafer Yield Die cost 386DX $ % $4 486 DX $ % $12 Power PC $ % $53 HP PA $ % $73 DEC Alpha $ % $149 Super Sparc $ % $272 Pentium $ % $417 Slide: 62

63 Summary Digital IC Business is Unique Things Get Better Every Few Years Companies Have to Stay on Moore s Law Curve to Survive Benefits of Transistor Scaling Higher Frequencies of Operation Massive Functional Units, Increasing On-Die Memory Cost/Functionality Going Down Downside of Transistor Scaling Power (Dynamic and Static) Design and Manufacturing Cost. Slide: 63