A Text Book of Computer Organization and Architecture Prof. JATINDER SINGH Director, GGI, Dhaliwal Er. AMARDEEP SINGH M.Tech (IT) AP&HOD, Deptt.of CSE, SVIET, Banur Er. GURJEET SINGH M.Tech (CSE) Head, Deptt. of Computer Science SGHS Khalsa College for Women, Mattewal-Amritsar UDH Publishers & Distributors (P) Ltd.
Contents Preface Acknowledgments xi xiii Boolean Algebra 1 1.1 Introduction 2 1.2 Difference between Boolean Algebra and Switching Algebra 2 1.3 Binary Valued Quantities and Bistable Devices 3 1.4 What is a Truth Table? 5 1.5 The Principle of Duality 6 1.6 Duality Theorem 6 1.7 Canonical Forms for Boolean Function 12 1.8 Karnaugh Map (K Map) 16 1.9 Logic Gates 26 1.10 Derived Gates 27 1.11 Combinational Circuit 32 1.12 Sequential Circuits 32 1.13 Digital Components 33 1.14 Half Adder and Full Adder 34 1.15 Parallel Binary Adders 37 1.16 Subtraction 38 1.17 Encoders and Decoders 39 1.18 Decoder 41 Exercise 44 Computer System Architecture 43 2.1 Introduction 44 2.2 What is Computer Architecture? 44 2.3 Structural Hierarchy 45 2.4 Computer Organization Vs Computer Architecture 46 2.5 Computer Systems 47 2.6 General Computer System Architecture 48 2.7 IPO (Input-Process-Output) Model 49 2.8 Operations on Digital Process 50 2.9 Detailed Computer System Organization/Computer Architecture 50 2.10 Elements of Computer System 55
vi A Text Book of Computer Organization and Architecture 2.11 Software 56 2.12 Types of Computers 2.13 Milestones in Computer Architecture 58 2.14 Basic Computer Architectures 59 2.15 Basic Computer Organization 61 2.16 Simplified Computer Architecture 64 2.17 Design Levels 64 2.18 Combinational or Sequential Design 65 2.19 Measuring Computer Performance 65 2.20 System Performance 66 2.21 The Moore's Law 66 Exercise 68 57 3. Combinational and Sequential Circuits 69 3.1 Introduction 70 3.2 Combinational Circuits 70 3.3 Decoders 72 3.4 Encoders 75 3.5 Multiplexers (MUX) 76 3.6 Demultiplexer 77 3.7 Sequential Circuits 78 3.8 Flip-flops 78 3.9 Edge-Triggered Flip-flops 79 3.10 Pulse-Triggered (Master-Slave) Flip-flops 81 3.11 Registers 82 3.12 Counters 84 3.13 Memory Unit, RAM, ROM 88 Exercise 90 4. Data Represetation 91 4.1 Introduction 92 4.2 Number Systems 92 4.3 Decimal Numbers 93 4.4 Binary Numbers 94 4.5 Octal Numbers 96 4.6 Hexadecimal Numbers 98 4.7 Binary Number Formats 101 4.8 More About Binary Numbers 101 4.9 Binary Arithmetic 106 4.10 Overview of Hexadecimal Arithmetic 108 4.11 Signed and Unsigned Binary Numbers 109 4.12 Addition and Subtraction Operations with Signed Binary 114 4.13 Range of Signed and Unsigned Binary Numbers 115 Exercise 115
Contents vii 5. Register Transfer and Microoperations 116 5.1 Introduction 117 5.2 Register Transfer Language 117 5.3 Register Transfer 118 5.4 Bus and Memory Transfer 119 5.5 Three-State Bus Buffers 120 5.6 Memory Transfer 121 5.7 Arithmetic Microoperations 122 5.8 Logic Microoperations 126 5.9 Shift microoperations 130 5.10 Arithmetic Logic Shift Unit 133 5.11 Hardware Description Languages 135 Exercise 138 6. Basic Organization and Design 139 6.1 Introduction 140 6.2 Memory Organization 140 6.3 Instruction Codes 141 6.4 Computer Registers 143 6.5 Computer Instructions 146 6.6 Timing and Control 148 6.7 Instruction Cycle 149 6.8 Memory Reference Instructions 154 6.9 Input-Output and Interrupt 156 6.10 Complete Computer Description 164 6.11 Design of Basic Computer 165 6.12 Design of Accumulator Logic 168 Exercise 170 7. Central Processing Unit 171 7.1 Central Processing Unit 172 7.2 Processor Design 176 7.3 Instruction Set Architecture 178 7.4 Internal Storage in CPU 184 7.5 General Purpose Register Organization 187 7.6 Single Accumulator Organization 189 7.7 Stack Organization 190 7.8 Memory Stack 191 7.9 Reverse Polish Notation 192 7.10 Instruction Formats 193 7.11 What is an Instruction Format 194 7.12 Three-Address Instruction Format 195 7.13 Two-address Instructions Format 195 7.14 One-Address Instructions Format 195
viii A Text Book of Computer Organization and Architecture 7.15 Zero-Address Instruction Format 196 7.16 Addressing Modes 197 Exercise 204 Input Output Organization 205 8.1 Input 8Devices 206 8.2 Output Devices 208 8.3 Audio Devices 210 8.4 System Components 211 8.5 System Buses 213 8.6 Synchronous Data Transfers 213 8.7 Asynchronous Data Transfers 214 8.8 I/O Modules 215 8.9 Interface Modules 216 8.10 I/O and Memory Buses 216 8.11 Interrupts 217 8.12 Types of Interrupts 218 8.13 Advantages of Interrupts 218 8.14 Uses of Interrupts 219 8.15 DMA (Direct Memory Access) 219 8.16 Input/Output Processor 221 8.17 Input/Output Channels 222 Exercise 222 9. Memory Organization 224 9.1 Introduction 225 9.2 Memory Hierarchies 225 9.3 Characteristics of the Memory Hierarchy 226 9.4 Secondary Storage 227 9.5 Self-Monitoring, Analysis and Reporting Technology System 230 9.6 Organization of Data on a Hard Drive 231 9.7 RAM 237 9.8 Primary Memory 239 9.9 Organization of Memory Devices 242 9.10 Interfacing Memory to a Processor 243 Exercise 246 10. Cache and Virtual Memory 247 10.1 Introduction 248 10.2 Cache Organization 250 10.3 Cache Operation 253 10.4 Cache Write Policy 261 10.5 Registers 261 10.6 Virtual Memory 262 10.7 Paging and Segmentation 263
Contents ix 10.8 Detailed Description of Virtual memory 265 10.9 Translation Lookaside Buffer 268 10.10 Segmentation 269 10.11 Combined Paging and Segmentation 270 10.12 Maintaining Track of Free Memory 271 10.13 Page replacement Algorithms 271 10.14 NRU (Not Recently Used) Algorithm 272 Exercise 273 Parallel Processing 274 li.l Introduction 275 11.2 Flynn's Classification 278 11.3 Pipelining 281 11.4 Array Processor/Vector Processor 290 11.5 Interprocessor Communication and Synchronization 294 11.6 Multiprocessor 302 11.7 Symmetric Multi-Processor (SMP) 306 11.8 Super Scalar Processor 308 11.9 VUW Architecture 311 11.10 Super Computers 315 11.11 Pentium 319 11.12 Server System 322 Exercise 324 Glossary 326 Index 339