Question Bank Microprocessor and Microcontroller

QUESTION BANK - 2 PART A 1. What is cycle stealing? (K1-CO3) During any given bus cycle, one of the system components connected to the system bus is given control of the bus. This component is said to be the master during that cycle and the component it is communicating with is said to be the slave. The CPU with its bus control logic is normally the master, but other specially designed components can gain control of the bus by sending a bus request to the CPU. After the current bus cycle is completed the CPU will return a bus grant signal and the component sending the request will become the master. Taking control of the bus for a bus cycle is called cycle stealing. 2. How DMA operations are performed? (K1-CO3) Following is the sequence of operations performed by a DMA. Initially, when any device has to send data between the device and the memory, the device has to send DMA request (DRQ) to DMA controller. The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the HLDA. Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU leaves the control over bus and acknowledges the HOLD request through HLDA signal. Now the CPU is in HOLD state and the DMA controller has to manage the operations over buses between the CPU, memory, and I/O devices. The chip support four DMA channels, i.e. four peripheral devices can independently request for DMA data transfer through these channels at a time. 3. Compare Burst transfer and Hidden DMA. (K2-CO3) Burst Transfer: To achieve block transfers, some DMAC's incorporate an automatic sequencing of the value presented on the address bus. A register is used as a byte count, being decremented for each byte transfer, and upon the byte count reaching zero, the DMAC will release the bus. When the DMAC operates in burst mode, the CPU is halted for the duration of the data transfer. Prepared by : R. Kavitha Page 1

Hidden DMA: Question Bank Microprocessor and Microcontroller It is possible to perform hidden DMA, which is transparent to the normal operation of the CPU. In other words, the bus is grabbed by the DMAC when the processor is not using it. The DMAC monitors the execution of the processor, and when it recognises the processor executing an instruction which has sufficient empty clock cycles to perform a byte transfer; it waits till the processor is decoding the op code, then grabs the bus during this time. 4. Show the interfacing diagram of 8257with 8086? (K1-CO3) 5. Show the internal architecture of 8257? (K1-CO3) Prepared by : R. Kavitha Page 2

6. Show the internal architecture of 8259? (K1-CO3) Prepared by : R. Kavitha Page 3

7. Summarize about cascade connection of 8259. (K2-CO3) Cascade buffer/comparator: This section generates control signal necessary for cascade operations. 8259A can be cascaded with the other 8259 to increase the interrupt handling capability. In such case, the former is called as master, and the later are called as slaves. The 8259 can be set up as a master or a slave by the SP*/EN*. 8. Show the structure of ICW1. (K1-CO3) 9. Show the structure of ICW4. (K1-CO3) Prepared by : R. Kavitha Page 4

10. Summarize the features of 8259. (K2-CO3) 1)Handle eight interrupt inputs. This is equivalent to providing eight interrupt pins on the processor in place of one INTR/INT pin. 2)It is possible to locate vector table for these additional interrupts request anywhere in the memory map. However, all the eight interrupt are spaced at the interval of either four or eight location. 3)By cascading 8259, it is possible to get 64 priority interrupts. 4) Mask each interrupt request individually. 5) 8259 can be programmed to accept either the level triggered or edge triggered interrupt request. 6) With the help of 8259 user can get information of pending interrupts, in service interrupt and masked interrupts. 7) It minimize the software and real-time overhead in handling multiple interrupt priorities. 11. How does the master slave concept work? (K1-CO3) Prepared by : R. Kavitha Page 5

12. Explain the interrupt sequence of 8259? (K2-CO3) Prepared by : R. Kavitha Page 6

13. Show the flowchart to initialize 8259. (K2-CO3) 14. Compare Microprocessor and Microcontroller. (K2-CO4) Prepared by : R. Kavitha Page 7

15. List out the application of 8051. (K1-CO4) 16. Summarize about CISC of 8051. (K2-CO4) Memory in those days was expensive. Bigger programs required more storage which included more money. There was a need to reduce the number of instructions per program. This was achieved by having multiple operations within single instruction. Multiple operations lead to many different kinds of instructions. Access to memory in turn makes the instruction length variable and fetch-decode execute time unpredictable making it more complex. Thus hardware was made to understand the complexity of instruction set. The computer having such instruction set was named as Complex Instruction Set Computer (CISC). Intel 8051 is an example for CISC architecture. 17. Compare Von Neumann and Harward architecture. (K2-CO4) Prepared by : R. Kavitha Page 8

18. What is an instruction cycle of 8051? (K1-CO4) The time taken to complete any instruction is called as machine cycle or instruction cycle. In 8051 one instruction cycle consists of 6 states or 12 clock cycles, instruction cycle is also referred as Machine cycle. 19. How Many Ways the Keyboard is Interfaced with the CPU? (K1-CO5) The Keyboard can be interfaced either in the interrupt or the polled mode. In the Interrupt mode, the processor is requested service only if any key is pressed, otherwise the CPU will continue with its main task. Prepared by : R. Kavitha Page 9

In the Polled mode, the CPU periodically reads an internal flag of 8279 to check whether any key is pressed or not with key pressure. 20. Summarize about Left entry and right entry mode. (K2-CO3) 1. Left Entry Mode In the Left entry mode, the data is entered from the left side of the display unit. Address 0 of the display RAM contains the leftmost display character and address 15 of the RAM contains the rightmost display character. 2. Right Entry Mode In the right entry mode, the first entry to be displayed is entered on the rightmost display. The next entry is also placed in the right most display but after the previous display is shifted left by one display position. 21. Show the structure of PSW of 8051. (K2-CO4) 22. List out the features of 8051. (K1-CO4) 8-bit CPU Prepared by : R. Kavitha Page 10

16-bit Program Counter 8-bit Processor Status Word (PSW) 8-bit Stack Pointer Internal RAM of 128bytes Special Function Registers (SFRs) of 128 bytes 32 I/O pins arranged as four 8-bit ports (P0 - P3) Two 16-bit timer/counters : T0 and T1 Two external and three internal vectored interrupts One full duplex serial I/O 23. Outline an Exchange instruction of 8051. (K2-CO4) The content of source ie., register, direct memory or indirect memory will be exchanged with the contents of destination ie., accumulator. i. XCH A,R3, ii. XCH A,@R1, iii. XCH A,54h 24. Summarize about DAA of 8051 with an example. (K2-CO4) DAA (Decimal Adjust After Addition). When two BCD numbers are added, the answer is a non-bcd number. To get the result in BCD, we use DA A instruction after the addition. DA A works as follows. If lower nibble is greater than 9 or auxiliary carry is 1, 6 is added to lower nibble. If upper nibble is greater than 9 or carry is 1, 6 is added to upper nibble. Eg 1: MOV A,#23H MOV R1,#55H ADD A,R1 // [A]=78 DA A // [A]=78 no changes in the accumulator after da a Eg 2: MOV A,#53H MOV R1,#58H ADD A,R1 // [A]=ABh DA A // [A]=11, C=1. ANSWER IS 111. Accumulator data is changed after DA A Prepared by : R. Kavitha Page 11

1. Explain the architecture of 8051. (K2-CO4) PART B Features: 8-bit CPU 16-bit Program Counter 8-bit Processor Status Word (PSW) Prepared by : R. Kavitha Page 12

8-bit Stack Pointer Internal RAM of 128bytes Special Function Registers (SFRs) of 128 bytes 32 I/O pins arranged as four 8-bit ports (P0 - P3) Two 16-bit timer/counters : T0 and T1 Two external and three internal vectored interrupts One full duplex serial I/O The heart of 8051 is the circuitry that generates the clock pulses by which all internal operations are synchronised. Pins XTAL1 and XTAL2 are provided for connecting resonator to form an oscillator. The time taken to complete any instruction is called as machine cycle or instruction cycle. In 8051 one instruction cycle consists of 6 states or 12 clock cycles, instruction cycle is also referred as Machine cycle. Instruction cycle of 8051 (Instruction cycle has six states (S 1 - S 6 ). Each state has two pulses (P1 and P2)) 128 bytes of Internal RAM Structure Prepared by : R. Kavitha Page 13

The lower 32 bytes are divided into 4 separate banks. Each register bank has 8 registers of one byte each. A register bank is selected depending upon two bank select bits in the PSW register. (RS1,RS0 bits of PSW) Next 16bytes are bit addressable. In total, 128bits (16X8) are available in bit addressable area. Each bit can be accessed and modified by suitable instructions.a bit variable can be set with a command such as SETB and cleared with a command such as CLR. Example instructions are: SETB 25h ; sets the bit 25h (becomes 1) CLR 25h ; clears bit 25h (becomes 0) The bit addresses are from 00H (LSB of the first byte in 20H) to 7FH (MSB of the last byte in 2FH). Remaining 80bytes of RAM are available for general purpose. The general purpose RAM can be accessed using direct or indirect addressing modes. Internal Data Memory and Special Function Register (SFR) Map Prepared by : R. Kavitha Page 14

The special function registers (SFRs) are mapped in the upper 128 bytes of internal data memory address. Hence there is an address overlap between the upper 128 bytes of data RAM and SFRs. Note that the upper 128 bytes of data RAM are present only in the 8052 family. The lower128 bytes of RAM (00H - 7FH) can be accessed both by direct or indirect addressing while the upper 128 bytes of RAM (80H - FFH) are accessed by indirect addressing. The SFRs (80H - FFH) are accessed by direct addressing only. This feature distinguishes the upper 128 bytes of memory from the SFRs, as shown in figure. The set of Special Function Registers (SFRs) contains important registers such as Accumulator, Register B, I/O Port latch registers, Stack pointer, Data Pointer, Processor Status Word (PSW) and various control registers. Processor Status Word (PSW) Prepared by : R. Kavitha Page 15

Accumulator is an 8 bit register widely used for all arithmetic and logical operations. Accumulator is also used to transfer data between external memory. B register is used along with Accumulator for multiplication and division. A and B registers together is also called MATH registers. Stack Pointer (SP) it contains the address of the data item on the top of the stack. Stack may reside anywhere on the internal RAM. On reset, SP is initialized to 07 so that the default stack will start from address 08 onwards. Data Pointer (DPTR) DPH (Data pointer higher byte), DPL (Data pointer lower byte). This is a 16 bit register which is used to furnish address information for internal and external program memory and for external data memory. Program Counter (PC) 16 bit PC contains the address of next instruction to be executed. On reset PC will set to 0000. After fetching every instruction PC will increment by one. 2. Explain the following addressing modes of 8051 with an Example. ( K2-CO4) 1. Immediate addressing, 2. Register addressing, 3. Direct addressing, 4. Indirect addressing, 5. Relative addressing. 1. Immediate addressing. In this addressing mode the data is provided as a part of instruction itself. In other words data immediately follows the instruction. Eg. MOV A,#30H ADD A, #83 # Symbol indicates the data is immediate. 2. Register addressing. Prepared by : R. Kavitha Page 16

In this addressing mode the register will hold the data. One of the eight general registers (R0 to R7) can be used and specified as the operand. Eg. MOV A,R0 ADD A,R6 R0 R7 will be selected from the current selection of register bank. The default register bank will be bank 0. 3. Direct addressing There are two ways to access the internal memory. Using direct address and indirect address. Using direct addressing mode we can not only address the internal memory but SFRs also. In direct addressing, an 8 bit internal data memory address is specified as part of the instruction and hence, it can specify the address only in the range of 00H to FFH. In this addressing mode, data is obtained directly from the memory. Eg. MOV A,60h ADD A,30h 4. Direct addressing There are two ways to access the internal memory. Using direct address and indirect address. Using direct addressing mode we can not only address the internal memory but SFRs also. In direct addressing, an 8 bit internal data memory address is specified as part of the instruction and hence, it can specify the address only in the range of 00H to FFH. In this addressing mode, data is obtained directly from the memory. Eg. MOV A,60h ADD A,30h 5. Indexed addressing. In indexed addressing, either the program counter (PC), or the data pointer (DTPR) is used to hold the base address, and the A is used to hold the offset address. Adding the value of the base address to the value of the offset address forms the effective address. Indexed addressing is used with JMP or MOVC instructions. Look up tables are easily implemented with the help of index addressing. Eg. MOVC A, @A+DPTR // copies the contents of memory location pointed by the sum of the accumulator A and the DPTR into accumulator A. MOVC A, @A+PC // copies the contents of memory location pointed by the sum of the accumulator A and the program counter into accumulator A. 3. Explain the following addressing modes of 8051 with an Example. (K2-CO4) 1. Absolute addressing, 2. Long addressing 3. Indexed addressing, 4. Bit inherent addressing, 5. Bit direct addressing. Prepared by : R. Kavitha Page 17

1. Relative Addressing. Relative addressing is used only with conditional jump instructions. The relative address, (offset), is an 8 bit signed number, which is automatically added to the PC to make the address of the next instruction. The 8 bit signed offset value gives an address range of +127 to 128 locations. The jump destination is usually specified using a label and the assembler calculates the jump offset accordingly. The advantage of relative addressing is that the program code is easy to relocate and the address is relative to position in the memory. Eg. SJMP LOOP1 2. Absolute addressing Absolute addressing is used only by the AJMP (Absolute Jump) and ACALL (Absolute Call) instructions. These are 2 bytes instructions. The absolute addressing mode specifies the lowest 11 bit of the memory address as part of the instruction. The upper 5 bit of the destination address are the upper 5 bit of the current program counter. Hence, absolute addressing allows branching only within the current 2 Kbyte page of the program memory. Eg. AJMP LOOP1 ACALL LOOP2 3. Long Addressing The long addressing mode is used with the instructions LJMP and LCALL. These are 3 byte instructions. The address specifies a full 16 bit destination address so that a jump or a call can be made to a location within a 64 Kbyte code memory space. Eg. LJMP FINISH LCALL DELAY 4. Bit Inherent Addressing In this addressing, the address of the flag which contains the operand, is implied in the opcode of the instruction. Eg. CLR C ; Clears the carry flag to 0 5. Bit Direct Addressing In this addressing mode the direct address of the bit is specified in the instruction. The RAM space 20H to 2FH and most of the special function registers are bit addressable. Bit address values are between 00H to 7FH. Eg. CLR 07h ; Clears the bit 7 of 20h RAM space SETB 07H ; Sets the bit 7 of 20H RAM space. Prepared by : R. Kavitha Page 18

4. Show the structure of registers in Timer and Counter of 8051. ( K3-CO5) 1. Timer Timers/Counters are used generally for Time reference Creating delay Wave form properties measurement Periodic interrupt generation Waveform generation The two timers in 8051 share two SFRs (TMOD and TCON) which control the timers, and each timer also has two SFRs dedicated solely to itself (TH0/TL0 and TH1/TL1). 8051 has two 16-bit programmable UP timers/counters. They can be configured to operate either as timers or as event counters In the "timer" function mode, the counter is incremented in every machine cycle. In the "counter" function mode, the register is incremented in response to a 1 to 0 transition at its corresponding external input pin (T0 or T1). It requires 2 machine cycles to detect a high to low transition. 1.1.Timer Mode control (TMOD) Special Function Register Gate: Based on the status of the signal. Timer starts counting using either internal clock (timer mode) or external pulses (counter mode). C/T*: It is used for the selection of Counter/Timer mode. Mode Select Bits: 1.2. Timer control (TCON) Special function register: TCON is bit addressable. The address of TCON is 88H. It is partly related to Timer and partly to interrupt. Prepared by : R. Kavitha Page 19

2. Interrupt 8051 has five interrupts. They are maskable and vectored interrupts. Out of these five, two are external interrupt and three are internal interrupts. 8051 makes use of two registers to deal with interrupts. 2.1. IE Register - Interrupt Enable register Prepared by : R. Kavitha Page 20

This is an 8 bit register used for enabling or disabling the interrupts. The structure of IE is 2.2. IP Register. This is an 8 bit register used for setting the priority of the interrupts. Prepared by : R. Kavitha Page 21

5. Construct the architecture diagram of 8279. (K2-CO3) I/O Control and Data Buffer This unit controls the flow of data through the microprocessor. It is enabled only when D is low. Its data buffer interfaces the external bus of the system with the internal bus of the microprocessor. The pins A0, RD, and WR are used for command, status or data read/write operations. Prepared by : R. Kavitha Page 22

Control and Timing Register These registers store the keyboard and display modes and other operating conditions programmed by CPU. Timing Control The timing control consists of the basic timing counter chain. The internal frequency gives the internal timings as given in table Parameter Key scan time Display scan time Digit on time Blanking time Timings 80 micro sec 10.3 msec 480 micro sec 10 micro sec Scan Counter The Scan Counter has two modes to scan the key matrix and refresh the display. In the Encoded mode, the counter provides a binary count that is to be externally decoded to provide the scan lines for keyboard and display (four externally decoded scan lines may drive up to 16 displays). In the decoded scan mode, the counter internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan on SL0-SL3 (four internally decoded scan lines may drive up to 4 Displays). These four active low output lines can be used directly to interface 4 digit 7 segment display. Keyboard Section: Return Buffers and Keyboard Debounce and Control This unit first scans the key closure row-wise, if found then the keyboard debounce unit debounces the key entry. In case, the same key is detected, then the code of that key is directly transferred to the sensor RAM along with SHIFT & CONTROL key status. FIFO/Sensor RAM and Status Logic Prepared by : R. Kavitha Page 23

This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every pressed key is entered into the RAM as per their sequence. The status logic generates an interrupt request after each FIFO read operation till the FIFO gets empty. In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is loaded with the status of their corresponding row of sensors into the matrix. When the sensor changes its state, the IRQ line changes to high and interrupts the CPU. Display Address Registers and Display RAM. The Display address registers hold the addresses of the word currently being written or read by the CPU to or from the display RAM. 6. Construct flowchart for initialization of keyboard and display mode and explain the program for interfacing 8279 with 8086. ( K3-CO3) PART C 1. Develop General algorithm for ADC interfacing. ( CO3- K3) 1. Ensure the stability of analog input, applied to the ADC. 2. Issue start of conversion pulse to ADC 3.Read end of conversion signal to mark the end of conversion processes. 4. Read digital data output of the ADC as equivalent digital output. 5. Analog input voltage must be constant at the input of the ADC right from the start of conversion till the end of the conversion to get correct results. This may be ensured by a sample and hold circuit which samples the analog signal and holds it constant for a specific time duration. The microprocessor may issue a hold signal to the sample and hold circuit. 6. If the applied input changes before the complete conversion process is over, the digital equivalent of the analog input calculated by the ADC may not be correct. 2. Develp an assembly language program to perform 8 bit addition, subtraction Multiplication and division with neat flowchart. (K1-CO3) Prepared by : R. Kavitha Page 24

3. Identify the OUT signal of different modes of Timer 8253. (K3-CO3) Prepared by : R. Kavitha Page 25

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