CS/IT DIGITAL LOGIC DESIGN

Similar documents
Code No: R Set No. 1

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

Code No: R Set No. 1

R10. II B. Tech I Semester, Supplementary Examinations, May

Code No: 07A3EC03 Set No. 1

Code No: R Set No. 1

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

R a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)

Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.

II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.

END-TERM EXAMINATION

R07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April

II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Discrete Mathematical Structures. Answer ONE question from each unit.

Hours / 100 Marks Seat No.


Scheme G. Sample Test Paper-I

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY

UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A (2 MARKS)

SHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI

COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I

HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment

1. Mark the correct statement(s)

SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3

(ii) Simplify and implement the following SOP function using NOR gates:

Injntu.com Injntu.com Injntu.com R16

R07

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS

VALLIAMMAI ENGINEERING COLLEGE

VALLIAMMAI ENGINEERING COLLEGE

PART B. 3. Minimize the following function using K-map and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).

MULTIMEDIA COLLEGE JALAN GURNEY KIRI KUALA LUMPUR

Philadelphia University Student Name: Student Number:

Digital logic fundamentals. Question Bank. Unit I

Programmable Logic Devices

Hours / 100 Marks Seat No.

NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni

QUESTION BANK FOR TEST

Switching Theory & Logic Design/Digital Logic Design Question Bank

EECS150 Homework 2 Solutions Fall ) CLD2 problem 2.2. Page 1 of 15

COPYRIGHTED MATERIAL INDEX

2008 The McGraw-Hill Companies, Inc. All rights reserved.

CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES.

R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai

DE Solution Set QP Code : 00904

3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0

CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)

10EC33: DIGITAL ELECTRONICS QUESTION BANK

Combinational Circuits

5. (a) What is secondary storage? How does it differ from a primary storage? (b) Explain the functions of (i) cache memory (ii) Register

Gate Level Minimization Map Method

CS8803: Advanced Digital Design for Embedded Hardware

ELCT201: DIGITAL LOGIC DESIGN

LOGIC CIRCUITS. Kirti P_Didital Design 1

CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

ELCT 501: Digital System Design

Chapter 2: Combinational Systems

ADIKAVI NANNAYA UNIVERSITY:: RAJAMAHENDRAVARAM II BTech (CSE) I Semester BTCSE301 DIGITAL LOGIC DESIGN MODEL QUESTION PAPER

DIGITAL ELECTRONICS. P41l 3 HOURS

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT

Digital Logic Design Exercises. Assignment 1

Combinational Circuits Digital Logic (Materials taken primarily from:

CS470: Computer Architecture. AMD Quad Core

1) What is the role of Information Technology in modern business? 2) Define computer? Explain the Block Diagram of computer with a neat diagram?

DIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER.

IT 201 Digital System Design Module II Notes

B.Sc.-IT (Part I) EXAMINATION, 2010 Computing Logics And Reasoning

(DMCA 101) M.C.A. DEGREE EXAMINATION, DEC First Year. Time : 03 Hours Maximum Marks : 75. Paper - I : INFORMATION TECHNOLOGY

COMBINATIONAL LOGIC CIRCUITS

ii) Do the following conversions: output is. (a) (101.10) 10 = (?) 2 i) Define X-NOR gate. (b) (10101) 2 = (?) Gray (2) /030832/31034

1. Draw general diagram of computer showing different logical components (3)

Unit 6 1.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2.Programmable Logic

ECE 331: N0. Professor Andrew Mason Michigan State University. Opening Remarks

Computer Architecture: Part III. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University

Experiment 3: Logic Simplification

LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology

ELCT201: DIGITAL LOGIC DESIGN

Experiment 4 Boolean Functions Implementation

Chapter 2 Combinational Logic Circuits

EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE

APPENDIX A SHORT QUESTIONS AND ANSWERS

Chapter 4. Combinational Logic. Dr. Abu-Arqoub

Combinational Logic Circuits

Written exam for IE1204/5 Digital Design Thursday 29/

Total No. of Questions : 18] [Total No. of Pages : 02. M.Sc. DEGREE EXAMINATION, DEC First Year COMPUTER SCIENCE.

Chapter 3. Gate-Level Minimization. Outlines

6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )

Recitation Session 6

Presentation 4: Programmable Combinational Devices

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

Course Batch Semester Subject Code Subject Name. B.E-Marine Engineering B.E- ME-16 III UBEE307 Integrated Circuits

Programmable Logic Devices (PLDs)

Topics. Midterm Finish Chapter 7

Gate Level Minimization

MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s. 2. Why the decimal number system is also called as positional number system?

SECTION-A

Transcription:

CS/IT 214 (CR) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester CS/IT DIGITAL LOGIC DESIGN Time: Three Hours 1. a) Flip-Flop Answer Question No.1 Compulsory. Answer One Question from each Unit. b) Universal Gates c) Hamming distance d) Purpose of Multiplexer e) Purpose of state table and state diagram f) Purpose of counter g) PAL UNIT-I 2. a) Convert the following number with indicated bases to decimal Maximum marks:70 7X2=14 M 4X14=56 M i. (1 0 1 1 1 1) 2 ii. (A 3 B) 16 iii. (2 3 7) 8 (iv) (4 3) 8 b) Simplify the following Boolean expression to a minimum number of literals. i. F=(BC + A D) (AB + CD ) ii. F=WYZ+ XY +XZ +YZ 3. a) Express the following function in sum of minterms and product of maxterms. F(A, B, C, D)= B D +A D + BD b) Simplify the following Boolean function using four-variable map. F(w, x, y, z) = (1,2,5,10,12)(0,4,8) d UNIT-II 4. What is meant by encoder? Design a 4-input priority encoder. 5. a) Implement a Boolean function F(x, y, z)= (2,4,6) with a Multiplexer. b) Explain about Tri-state gates in digital systems. UNIT-III 6. Design a sequential circuit with two JK flip-flos A,B with one input X and one output Y. A(t+1) =Ax+Bx B(t+1)=A x Y=Ax +Bx 1 P.T.O

7. A Sequential circuit with two D flip-flops A and B, two inputs x and y and one output z is specified by the following next-state and output equation. A(t+1)=x y+xa z=b B(t+1)=x B+xA a) Draw the logic diagram of the circuit. b) List the state table for the sequential circuit c) Draw the corresponding state diagram. UNIT-IV 8. a) Design a 4-bit ring counter using T-flip flops and draw the circuit diagram and timing diagrams. b) Draw and explain 4-bit universal shift register. 9. a) Draw the block diagram and explain the operation of serial transfer between two shift registers and draw its timing diagram. b) Write a brief on EPROM and EEPROM and their characteristics. 2

CS/IT 214 (RR) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester CS/IT OBJECT ORIENTED PROGRAMMING Time: Three Hours Answer Question No.1 Compulsory. Answer One Question from each Unit. 1. a) Define class and object b) new and delete with suitable example code c) Copy constructor d) Concept of early binding and late binding e) Define stream f) Casting operators g) Define Namespace UNIT-I 2. a) What is infinite regression in OOP? Explain Maximum marks:70 7X2=14 M 4X14=56 M b) What are the differences between conventional programming and object-oriented programming? Explain. 3. a) Write a brief on nested classes and explain with an example how nested classes can be implemented. b) Explain with an example code how array of objects, pointer, references can be implemented UNIT-II 4. a) What is a virtual method? Discuss with an example the significance of using virtual methods in C++. b) Write a program to overload * operator such that when an expression of the form University *3 will replicate the string for three time. 5. State and explain different forms of Inheritance. Which forms of inheritance are supported by C++. Give suitable example code for each. 1 P.T.O

UNIT-III 6. a) What is RTTI (Run-time type identification) in C++? Explain. b) Define exception and explain with suitable code how exception handling is implemented. 7. Define template and explain its purpose in creating generic functions and generic classes with suitable code. UNIT-IV 8. a) Explain different operations on files. Write a program to copy content of one text file to another. b) Write a brief on Dynamic_cast and Reinterpret_cast 9. Write a brief on the following and give suitable example code of their implementation: a) Volatile member functions b) Binary I/O with array based streams. 2

CSE/IT 214 (CR) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, APRIL/MAY- 2016 First Semester CSE/IT DIGITAL LOGIC DESIGN Time: Three Hours Answer Question No.1 Compulsory Answer ONE question from each Unit Maximum marks:70 7X2=14 M 4X14=56 M 1. a. Product of sum and Sum of Products b. Truth table for XOR gate c. Latch, Race condition in Flip-Flop d. Draw 1X4 Encoder e. DRAM f. Purpose of Register g. Purpose of Mod10 counter. UNIT-I 2. a. Convert the following numbers. i. (53) 10 = ( ) 2 ii. (231) 8 = ( ) 10 iii. (1 1 0 1 1 0 1) 2 = ( ) 8 iv. (4D. 56) 16 = ( ) 2 b. Implement the following Boolean function using AND, OR and inverter gates. F = xy + x y + y z. 3. a. Using the rules of boolean algebra, simplify the expressions that follow to the fewest total number of literals. i. f = AB + ABC + AC D ii. f = B + AD + BC +(B+A(C+D)) b. Simplify the following Boolean function using four-variable map. F(w, x, y, z) =. (1,3,7,11,15)(0,2,5) d UNIT-II 4. a. Explain carry propagation in parallel adder with a neat diagram. b. What is a decoder? Construct a 4X16 decoder with two 3x8 decoders. 5. Design a code converter that converts BCD to excess-3 code. 1 P.T.O

UNIT-III 6. a. Discuss in detail about sequential circuit. Construct a JK flip-flop using a D flip-flop, a 2 to-1 multiplexer and inverter. b. Write a brief on Edge triggered FlipFlops. 7. a. Define the following terms related to flip-flops. i. hold time ii. propagation delay iii. clock and iv direct inputs. b. A combinational logic circuit is defined by the following Boolean functions. F1= (ABC) +AC F2 = A(BC) + A B F3 = AB C + AB Design the circuit with a decoder and external gates. UNIT-IV 8. a. Explain different types of shift registers. Draw and explain 4-bit universal shift register b. Write a brief on PLA. 9. a. Explain the construction of a basic memory cell and also explain with diagram the construction of a 4*4 RAM b. Explain the difference between asynchronous and synchronous sequential circuits. 2

CSE/IT 214(R-15) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester CSE/IT DISCRETE MATHEMATICAL STRUCTURES Time: Three Hours Answer Question No.1 Compulsory. Answer One Question from each Unit. 1. Write short notes on: a) Disjoint sets b) Chromatic number c) Digraph d) Planar graph e) Predicate f) Permutation 2. a) Is (( PV(P -> Q))->Q) a tautology? UNIT-I Maximum marks:60 6X2=12 M 4X12=48 M b) Construct a truth table for converse, inverse and contrapositive and a proposition. 3. a) State and prove DeMorgan s law. b) Show that the propositions P->Q and ~PVQ are logically equivalent. UNIT-II 4. a) State and prove Pigeonhole principle. b) How many different strings can be made by reordering the letters of the word SUCCESSOR? 5. a) What is the expansion of (X+Y) 4. b) What is the coefficient of X 12 Y 13 in the expansion of (2X-3Y) 25? UNIT-III 6. a) What is the solution of the recurrence relation a n =6a n-1-9a n-2 With initial conditions a 0 =1 and a 1 =6? b) Show that congruence modulo relation is an equivalence relation. 7. Explain a) injective relation b) surjective relation c) bijective relation with examples. 1 P.T.O

UNIT-IV 8. Explain a) Lattices b) Adjacency matrix. 9. a) Explain the four colour problem b) Explain topological sorting. 2

CSE/IT 214 (RR) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, APRIL/MAY- 2016 First Semester CSE/IT OBJECT ORIENTED PROGRAMMING Time: Three Hours Answer Question No.1 Compulsory Answer ONE question from each Unit 1. a. General form of C++ program b. Object assignment c. Virtual base class d. Terminate ( ) e. Dynamic cast f. Pure virtual function g. Namespace UNIT-I Maximum marks:70 7X2=14 M 4X14=56 M 2. a. Explain the concept of constructors and destructors and explain how to define and their purpose. b. Write a program explaining the purpose of friend function with suitable code. 3. a. Define class, object. Explain the characteristics of Object oriented programming. b. Write a program to explain the concept of how to create an array of objects and use of dynamic memory allocation. UNIT-II 4. Explain different types of inheritance that are supported in C++ with suitable example code for each. 5. a. Explain operator overloading and write a program to overload the operator multiplica tion to repeat the string by given number of times (Ex. University 3 should result in UniversityUniversityUniversity ). b. Write a brief on default argument and explain their purpose. UNIT-III 6. a. Explain the purpose of virtual function with an example and explain the concept of early and late binding. 1 P.T.O

b. Write a program that implements exception handling showing the hierarchy of exceptions. 7. a. Explain the concept of templates and write a program to explain their purpose. b. Write a brief on unexpected( ) and uncaught_exception(). UNIT-IV 8. a. Define stream and explain different types of streams that are supported in C++. b. Write a brief on ignore(), peak ( ), flush ( ) with suitable example explaining their purpose. 9. Write a brief on the following: a. Binary I/O with array based streams b. Explicit constructors c. Volatile member functions 2