ELCT 501: Digital System Design
|
|
- Sabrina Osborne
- 5 years ago
- Views:
Transcription
1 ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany,
2 Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2
3 1-bit adder Inputs: A (1 bit) B (1 bit) Cin (1 bit) Cout A B Cin Outputs Sum = A xor B xor Cin Cout = AB + BC + AC SUM 3
4 1-bit adder 4
5 1-bit adder VHDL Code (1-Bit Adder) entity <File Name> is Port ( <Define Inputs & Outputs>); end <File Name>; architecture < > of <Entity Name> is begin {Code implementation} end < >; 5
6 4-bit adder A3 B3 A2 B2 A1 B1 A0 B0 Cout 1-Bit Adder w3 1-Bit Adder w2 1-Bit Adder w1 1-Bit Adder Cin= 0 SUM 3 SUM 2 SUM 1 SUM 0 Unit 4 Unit 3 Unit 2 Unit 1 6
7 4-bit adder A3 B3 A2 B2 A1 B1 A0 B0 Cout 1-Bit Adder 1-Bit Adder 1-Bit Adder w3 w2 w1 1-Bit Adder Cin= 0 SUM 3 Unit 4 SUM 2 SUM 1 SUM 0 Unit 3 Unit 2 Unit 1 7
8 4-bit adder - VHDL entity adder4 is Port ( A : in STD_LOGIC_VECTOR (3 downto 0); B : in STD_LOGIC_VECTOR (3 downto 0); sum : out STD_LOGIC_VECTOR (3 downto 0); cout : out STD_LOGIC); end adder4; 8
9 Basic VHDL Concept Via an Example Problem: write VHDL code to specify the circuit of one-digit BCD (Binary Coded Decimal) adder (shown in the following figure) 9
10 Binary Coded Decimal Representation Z= X+Y IF Z <= 9, then S = Z and carry-out = 0 IF Z > 9, then X = Z + 6 and carry-out = 1 X Y Z S = 2 10
11 Binary Coded Decimal Representation Z= X+Y IF Z <= 9, then S = Z and carry-out = 0 IF Z > 9, then X = Z + 6 and carry-out = 1 X Y Z S = 7 11
12 Binary Coded Decimal Representation 12
13 Basic VHDL Concept Via an Example Problem: write VHDL code to specify the circuit in the following figure comparator circuit 13
14 Comparator Circuit X< Y is detected by N xor V=1 X=Y is detected by Z=1 X Y is detected by Z+(N xor V)=1 X>Y is detected by Z+(N xor V)=1 X Y is detected by N xor V=1 14
15 Comparator Circuit 15
16 Digital Logic Classification Digital Logic Combinational o/p s depend on i/p s only E.g. Logic Gates Sequential o/p s depend on i/p s & state of storage elements Asynchronous E.g. Latches Synchronous E.g. Flip Flops 16
17 VHDL for Combinational Circuit Selected Signal Assignment A selected signal assignment allows a signal to be assigned one of several values, based on a selection criterion W0 f W1 s 2-to 1 multiplexer 17
18 VHDL for Combinational Circuit Selected Signal Assignment W0 W1 W2 W3 f 2 s 4-to 1 multiplexer 18
19 VHDL for Combinational Circuit Conditional Signal Assignment Similar to the selected signal assignment, a conditional signal assignment allows a signal to be set to one of several values The priority level associated with each WHEN clause in the conditional signal assignment is a key difference from the selected signal assignment 19
20 VHDL for Combinational Circuit Think about the efficient code Less efficient code 20
21 VHDL for Combinational Circuit CASE Statement Similar to the selected signal assignment- the case statement has a selection signal and includes WHEN clause for various valuations of this selection signal. 2-to-4 binary decoder 21
22 VHDL for Combinational Circuit VHDL operators. Operator category Operator symbol Operation performed Logical AND OR NAND NOR XOR XNOR NOT AND OR Not AND Not OR XOR Not XOR NOT 22
23 VHDL for Combinational Circuit VHDL operators. Operator category Operator symbol Operation performed = Equality /= Inequality Relational > Greater than < Less than >= Greater than or equal to <= Less than or equal to 23
24 VHDL for Combinational Circuit VHDL operators. Operator category Operator symbol Operation performed Arithmetic + Addition - Subtraction Concatenation & Concatenation Examples:. C <= A B; Puts the difference of A and B into C D <= A & B; using three-bit vectors; A(2 downto 0), B(2 downto 0), the output D will be: D= a 1 a 2 a 3 b 1 b 2 b 3 (six-bit vector) 24
25 VHDL for Combinational Circuit VHDL operators. Operator category Operator symbol Operation performed SLL Shift left logical Shift and Rotate Examples:. B <= A SLL; SRL ROL ROR B <= A ROR 2; Shift right logical Rotate left Rotate right b2=a1, b1= a0, and b0= 1 b2=a1, b1= a0, and b0= a2 25
26 VHDL for Sequential Circuit With the info we encountered so far, can we build this? button When the button is pushed: 1) Turn on the light if it is off 2) Turn off the light if it is on light The light should change state within a second of the button press No! 1. state i.e. the circuit should have memory 2. The o/p changes by an i/p event (pushing a button) 26
27 What is a latch? 27
28 D Latch Logic diagram Function table 28
29 VHDL for D Latch Function table 29
30 What is a FF? Simply, it is a clocked latch Function table 30
31 Alternative code for a D Flip-flop A process that uses a WAIT UNTIL statement is a special case because the sensitivity list is omitted Function table 31
32 D Flip-flop with Asynchronous reset Function table 32
33 D Flip-flop with synchronous reset 33
34 Four bit up-counter 34
35 Four bit up-counter : testing 35
36 Four bit up-counter : testing 36
37 Four bit up-counter 37
Abi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University
Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL Defined in 1980s by U.S.
More informationHardware Description Language VHDL (1) Introduction
Hardware Description Language VHDL (1) Introduction Digital Radiation Measurement and Spectroscopy NE/RHP 537 Introduction Hardware description language (HDL) Intended to describe circuits textually, for
More informationDigital Systems Design
Digital Systems Design Review of Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits Dr. D. J. Jackson Lecture 2-1 Introduction to VHDL Designer writes a logic circuit description in
More informationIT T35 Digital system desigm y - ii /s - iii
UNIT - V Introduction to Verilog Hardware Description Language Introduction HDL for combinational circuits Sequential circuits Registers and counters HDL description for binary multiplier. 5.1 INTRODUCTION
More informationLecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26)
Lecture Topics Today: Integer Arithmetic (P&H 3.1-3.4) Next: continued 1 Announcements Consulting hours Introduction to Sim Milestone #1 (due 1/26) 2 1 Overview: Integer Operations Internal representation
More informationLecture 3: Modeling in VHDL. EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationLecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)
Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable
More informationR10. II B. Tech I Semester, Supplementary Examinations, May
SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31
More informationSystems Programming. Lecture 2 Review of Computer Architecture I
Systems Programming www.atomicrhubarb.com/systems Lecture 2 Review of Computer Architecture I In The Book Patt & Patel Chapter 1,2,3 (review) Outline Binary Bit Numbering Logical operations 2's complement
More informationCOE 405 Design Methodology Based on VHDL
COE 405 Design Methodology Based on VHDL Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Elements of VHDL Top-Down Design Top-Down Design with
More informationACS College of Engineering. Department of Biomedical Engineering. Logic Design Lab pre lab questions ( ) Cycle-1
ACS College of Engineering Department of Biomedical Engineering Logic Design Lab pre lab questions (2015-2016) Cycle-1 1. What is a combinational circuit? 2. What are the various methods of simplifying
More informationVHDL 2 Combinational Logic Circuits. Reference: Roth/John Text: Chapter 2
VHDL 2 Combinational Logic Circuits Reference: Roth/John Text: Chapter 2 Combinational logic -- Behavior can be specified as concurrent signal assignments -- These model concurrent operation of hardware
More informationVHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning
VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Cengage Learning Design Flow 418_02 2 VHDL Modules 418_02 3 VHDL Libraries library IEEE; use IEEE.std_logic_1164.all; std_logic Single-bit
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationREGISTER TRANSFER LANGUAGE
REGISTER TRANSFER LANGUAGE The operations executed on the data stored in the registers are called micro operations. Classifications of micro operations Register transfer micro operations Arithmetic micro
More informationHours / 100 Marks Seat No.
17333 13141 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Illustrate your answers with neat sketches wherever necessary. (4)
More informationContents. Appendix D VHDL Summary Page 1 of 23
Appendix D VHDL Summary Page 1 of 23 Contents Appendix D VHDL Summary...2 D.1 Basic Language Elements...2 D.1.1 Comments...2 D.1.2 Identifiers...2 D.1.3 Data Objects...2 D.1.4 Data Types...2 D.1.5 Data
More informationInjntu.com Injntu.com Injntu.com R16
1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder
More informationTopics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
More informationEECE-4740/5740 Advanced VHDL and FPGA Design. Lecture 3 Concurrent and sequential statements
EECE-4740/5740 Advanced VHDL and FPGA Design Lecture 3 Concurrent and sequential statements Cristinel Ababei Marquette University Department of Electrical and Computer Engineering Overview Components hierarchy
More informationFPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
More informationReview of Digital Design with VHDL
Review of Digital Design with VHDL Digital World Digital world is a world of 0 and 1 Each binary digit is called a bit Eight consecutive bits are called a byte Hexadecimal (base 16) representation for
More informationHANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment
Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)
More informationLogic and Computer Design Fundamentals VHDL. Part 1 Chapter 4 Basics and Constructs
Logic and Computer Design Fundamentals VHDL Part Chapter 4 Basics and Constructs Charles Kime & Thomas Kaminski 24 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Overview
More informationECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level
More informationECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level
More informationLecture 12 VHDL Synthesis
CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?
More informationR a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method
SET - 1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove de-morgan laws c) Implement two input EX-OR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationDIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 3
DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 3 BEHAVIORAL DESCRIPTION Asynchronous processes (decoder, mux, encoder, etc): if-else, case, for-loop. Arithmetic expressions inside asynchronous processes.
More informationPhiladelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2018/2019 Dept. of Computer Engineering Course Title: Logic Circuits Date: 03/01/2019
More informationCOE 405, Term 062. Design & Modeling of Digital Systems. HW# 1 Solution. Due date: Wednesday, March. 14
COE 405, Term 062 Design & Modeling of Digital Systems HW# 1 Solution Due date: Wednesday, March. 14 Q.1. Consider the 4-bit carry-look-ahead adder (CLA) block shown below: A 3 -A 0 B 3 -B 0 C 3 4-bit
More informationDigital Design with SystemVerilog
Digital Design with SystemVerilog Prof. Stephen A. Edwards Columbia University Spring 25 Synchronous Digital Design Combinational Logic Sequential Logic Summary of Modeling Styles Testbenches Why HDLs?
More informationBASIC VHDL LANGUAGE ELEMENTS AND SEMANTICS. Lecture 7 & 8 Dr. Tayab Din Memon
BASIC VHDL LANGUAGE ELEMENTS AND SEMANTICS Lecture 7 & 8 Dr. Tayab Din Memon Outline Data Objects Data Types Operators Attributes VHDL Data Types VHDL Data Objects Signal Constant Variable File VHDL Data
More informationSRI SUKHMANI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DERA BASSI (MOHALI)
SRI SUKHMANI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DERA BASSI (MOHALI) VLSI LAB MANUAL ECE DEPARTMENT Introduction to VHDL It is a hardware description language that can be used to model a digital system
More informationLecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: The MIPS ISA (P&H ) Consulting hours. Milestone #1 (due 1/26)
Lecture Topics Today: Integer Arithmetic (P&H 3.1-3.4) Next: The MIPS ISA (P&H 2.1-2.14) 1 Announcements Consulting hours Milestone #1 (due 1/26) Milestone #2 (due 2/2) 2 1 Review: Integer Operations Internal
More informationVHDL 3 BASIC OPERATORS AND ARCHITECTURE BODY. Design descriptions & design constructions examples are taken from foundation series examples
1 VHDL 3 BASIC OPERATORS AND ARCHITECTURE BODY Design descriptions & design constructions examples are taken from foundation series examples 2 What we have done in Lab 1 entity AND_Gate is port ( a : in
More informationVHDL Examples Mohamed Zaky
VHDL Examples By Mohamed Zaky (mz_rasmy@yahoo.co.uk) 1 Half Adder The Half Adder simply adds 2 input bits, to produce a sum & carry output. Here we want to add A + B to produce Sum (S) and carry (C). A
More informationDigital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
More informationECE 545 Lecture 12. FPGA Resources. George Mason University
ECE 545 Lecture 2 FPGA Resources George Mason University Recommended reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional Details 2 What is an FPGA? Configurable Logic Blocks
More informationPart 4: VHDL for sequential circuits. Introduction to Modeling and Verification of Digital Systems. Memory elements. Sequential circuits
M1 Informatique / MOSIG Introduction to Modeling and erification of Digital Systems Part 4: HDL for sequential circuits Laurence PIERRE http://users-tima.imag.fr/amfors/lpierre/m1arc 2017/2018 81 Sequential
More informationMicrocomputers. Outline. Number Systems and Digital Logic Review
Microcomputers Number Systems and Digital Logic Review Lecture 1-1 Outline Number systems and formats Common number systems Base Conversion Integer representation Signed integer representation Binary coded
More information!"#$%&&"'(')"*+"%,%-".#"'/"'.001$$"
!"#$%&&"'(')"*+"%,%-".#"'/"'.001$$"!!"#$%&'#()#*+"+#,-."/0110#230#4."50",+"+#)6# 6+-+#(.6+-0#)4475.8)60#0/#.65-0#230#9+**+"+# 2.48).-0#(.6+-0#! 2+"*5."5*:#,."/0110#;)**0! *),".6*:#-.99-0*0"5."+#2+660,.40"5)#;)*)2)#
More informationECOM4311 Digital Systems Design
ECOM 4311 Digital Systems Design Eng. Monther Abusultan Computer Engineering Dept. Islamic University of Gaza Page 1 Agenda 1. VHDL : Data Types Cont d 2. VHDL : Operators 3. VHDL : Signal Assignments
More informationDIGITAL LOGIC WITH VHDL (Fall 2013) Unit 3
DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 3 BEHAVIORAL DESCRIPTION Asynchronous processes (decoder, mux, encoder, etc): if-else, case, for-loop. BEHAVIORAL DESCRIPTION (OR SEQUENTIAL) In this design style,
More informationPrinciples of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.
Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)
More informationDigital Logic Design Exercises. Assignment 1
Assignment 1 For Exercises 1-5, match the following numbers with their definition A Number Natural number C Integer number D Negative number E Rational number 1 A unit of an abstract mathematical system
More informationECE 2030B 1:00pm Computer Engineering Spring problems, 5 pages Exam Two 10 March 2010
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
More informationWritten Re-exam with solutions for IE1204/5 Digital Design Friday 10/
Written Re-exam with solutions for IE24/5 Digital Design Friday /4 25 8.-2. General Information Examiner: Teacher: Ingo Sander. Kista, William Sandvist, phone 8-79 44 87 / Fredrik Jonsson. Exam text does
More informationCPE/EE 422/522. Chapter 8 - Additional Topics in VHDL. Dr. Rhonda Kay Gaede UAH. 8.1 Attributes - Signal Attributes that return a value
CPE/EE 422/522 Chapter 8 - Additional Topics in VHDL Dr. Rhonda Kay Gaede UAH 1 8.1 Attributes - Signal Attributes that return a value A event true if a has just occurred A active true if A has, even if
More informationDigital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University
Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register
More informationWriting VHDL for RTL Synthesis
Writing VHDL for RTL Synthesis Stephen A. Edwards, Columbia University December 21, 2009 The name VHDL is representative of the language itself: it is a two-level acronym that stands for VHSIC Hardware
More information1. What is y-chart? ans: The y- chart consists of three domains:- behavioral, structural and geometrical.
SECTION- A Short questions: (each 2 marks) 1. What is y-chart? ans: The y- chart consists of three domains:- behavioral, structural and geometrical. 2. What is fabrication? ans: It is the process used
More informationContents. Chapter 9 Datapaths Page 1 of 28
Chapter 9 Datapaths Page of 2 Contents Contents... 9 Datapaths... 2 9. General Datapath... 3 9.2 Using a General Datapath... 5 9.3 Timing Issues... 7 9.4 A More Complex General Datapath... 9 9.5 VHDL for
More informationConcurrent & Sequential Stmts. (Review)
VHDL Introduction, Part II Figures in this lecture are from: Rapid Prototyping of Digital Systems, Second Edition James O. Hamblen & Michael D. Furman, Kluwer Academic Publishers, 2001, ISBN 0-7923-7439-
More informationUNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents Memory: Introduction, Random-Access memory, Memory decoding, ROM, Programmable Logic Array, Programmable Array Logic, Sequential programmable
More information5. 0 VHDL OPERATORS. The above classes are arranged in increasing priority when parentheses are not used.
Filename= ch5.doc 5. 0 VHDL OPERATORS There are seven groups of predefined VHDL operators: 1. Binary logical operators: and or nand nor xor xnor 2. Relational operators: = /= < >= 3. Shifts operators:
More information(ii) Simplify and implement the following SOP function using NOR gates:
DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be
More informationECE 545 Lecture 8. Data Flow Description of Combinational-Circuit Building Blocks. George Mason University
ECE 545 Lecture 8 Data Flow Description of Combinational-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 7, Combinational Circuit Design:
More informationSIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)
SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: II-B.Tech & I-Sem Course & Branch: B.Tech
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN
SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.2017-18 INSTRUCTOR: Sri A.M.K.KANNA
More informationLecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1
Lecture 1: VHDL Quick Start Digital Systems Design Fall 10, Dec 17 Lecture 1 1 Objective Quick introduction to VHDL basic language concepts basic design methodology Use The Student s Guide to VHDL or The
More informationIntroduction to Verilog HDL. Verilog 1
Introduction to HDL Hardware Description Language (HDL) High-Level Programming Language Special constructs to model microelectronic circuits Describe the operation of a circuit at various levels of abstraction
More informationLABORATORY MANUAL VLSI DESIGN LAB EE-330-F
LABORATORY MANUAL VLSI DESIGN LAB EE-330-F (VI th Semester) Prepared By: Vikrant Verma B. Tech. (ECE), M. Tech. (ECE) Department of Electrical & Electronics Engineering BRCM College of Engineering & Technology
More informationCSCI Lab 3. VHDL Syntax. Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\
CSCI 250 - Lab 3 VHDL Syntax Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\ Objectives 1. Learn VHDL Valid Names 2. Learn the presentation of Assignment and Comments 3. Learn Modes, Types, Array,
More informationECE 545 Lecture 5. Data Flow Modeling in VHDL. George Mason University
ECE 545 Lecture 5 Data Flow Modeling in VHDL George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 4, Concurrent Signal Assignment Statements of VHDL 2 Types of VHDL Description
More informationDepartment of Electronics & Communication Engineering Lab Manual E-CAD Lab
Department of Electronics & Communication Engineering Lab Manual E-CAD Lab Prasad V. Potluri Siddhartha Institute of Technology (Sponsored by: Siddhartha Academy of General & Technical Education) Affiliated
More informationCONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)
CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...
More informationLab Assignment 1. Developing and Using Testbenches
Lab Assignment 1 Developing and Using Testbenches Task 1 Develop a testbench in VHDL to test and verify the operation of an ALU (Arithmetic Logic Unit), specified using Fig. 1 and Tables 1 and 2. The ALU
More information[VARIABLE declaration] BEGIN. sequential statements
PROCESS statement (contains sequential statements) Simple signal assignment statement
More informationLet s put together a Manual Processor
Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce
More informationDIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6
DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6 FINITE STATE MACHINES (FSMs) Moore Machines Mealy Machines FINITE STATE MACHINES (FSMs) Classification: Moore Machine: Outputs depend only on the current state
More informationConcurrent Signal Assignment Statements (CSAs)
Concurrent Signal Assignment Statements (CSAs) Digital systems operate with concurrent signals Signals are assigned values at a specific point in time. VHDL uses signal assignment statements Specify value
More informationWritten exam for IE1204/5 Digital Design Thursday 29/
Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.00-13.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned when
More informationVHDL Objects. Lecture 8: VHDL (2) Variables. VHDL Objects - Constant. Files. EE3109 Gopi K. Manne Fall 2007
Lecture 8: VHDL (2) VHDL Objects Four types of objects in VHDL Constants Variables Computer Aided Digital Design EE3109 Gopi K. Manne Fall 2007 Signals Files The scope of an object is as follows : Objects
More informationECE 341 Midterm Exam
ECE 341 Midterm Exam Time allowed: 90 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (10 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a)
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationLab Assignment 2. Implementing Combinational and Sequential Logic in VHDL
Lab Assignment 2 Implementing Combinational and Sequential Logic in VHDL Task 1 Draw a detailed block diagram of the ALU (Arithmetic Logic Unit), specified using Fig. 1 and Tables 1 and 2. Then develop
More informationField Programmable Gate Array
Field Programmable Gate Array System Arch 27 (Fire Tom Wada) What is FPGA? System Arch 27 (Fire Tom Wada) 2 FPGA Programmable (= reconfigurable) Digital System Component Basic components Combinational
More informationEL 310 Hardware Description Languages Midterm
EL 3 Hardware Description Languages Midterm 2 3 4 5 Total Name: ID : Notes: ) Please answer the questions in the provided space after each question. 2) Duration is minutes 3) Closed books and closed notes.
More information6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )
6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Signals and Wires Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate digital signals
More informationBUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book
BUILDING BLOCKS OF A BASIC MICROPROCESSOR Part PowerPoint Format of Lecture 3 of Book Decoder Tri-state device Full adder, full subtractor Arithmetic Logic Unit (ALU) Memories Example showing how to write
More informationDIGITAL ELECTRONICS. P41l 3 HOURS
UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don
More informationHardware Modeling. VHDL Syntax. Vienna University of Technology Department of Computer Engineering ECS Group
Hardware Modeling VHDL Syntax Vienna University of Technology Department of Computer Engineering ECS Group Contents Identifiers Types & Attributes Operators Sequential Statements Subroutines 2 Identifiers
More informationECE 341 Midterm Exam
ECE 341 Midterm Exam Time allowed: 75 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (8 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a) A
More informationVHDL BASIC ELEMENTS INTRODUCTION
VHDL BASIC ELEMENTS INTRODUCTION VHDL Basic elements Identifiers Basic identifiers Extended identifiers Data Objects Constant Variable Signal File Data Types Scalar Composite Access File type Identifiers
More informationTopics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 Xilinx FPGAs Chapter 7 Spartan 3E Architecture Source: Spartan-3E FPGA Family Datasheet CLB Configurable Logic Blocks Each CLB contains four slices Each slice
More informationControl and Datapath 8
Control and Datapath 8 Engineering attempts to develop design methods that break a problem up into separate steps to simplify the design and increase the likelihood of a correct solution. Digital system
More informationC-Based Hardware Design
LECTURE 6 In this lecture we will introduce: The VHDL Language and its benefits. The VHDL entity Concurrent and Sequential constructs Structural design. Hierarchy Packages Various architectures Examples
More informationCSE 260 Introduction to Digital Logic and Computer Design. Exam 1. Your name 2/13/2014
CSE 260 Introduction to Digital Logic and Computer Design Jonathan Turner Exam 1 Your name 2/13/2014 1. (10 points) Draw a logic diagram that implements the expression A(B+C)(C +D)(B+D ) directly (do not
More information3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0
1. The number of level in a digital signal is: a) one b) two c) four d) ten 2. A pure sine wave is : a) a digital signal b) analog signal c) can be digital or analog signal d) neither digital nor analog
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More informationDESCRIPTION OF DIGITAL CIRCUITS USING VHDL
DESCRIPTION OF DIGITAL CIRCUITS USING VHDL Combinatinal circuits Sequential circuits Design organization. Generic design Iterative operations Authors: Luis Entrena Arrontes, Celia López, Mario García,
More informationThe VHDL Hardware Description Language
The VHDL Hardware Description Language p. 1/? The VHDL Hardware Description Language CSEE W4840 Prof. Stephen A. Edwards Columbia University The VHDL Hardware Description Language p. 2/? Why HDLs? 1970s:
More informationMid-Term Exam Solutions
CS/EE 26 Digital Computers: Organization and Logical Design Mid-Term Eam Solutions Jon Turner 3/3/3. (6 points) List all the minterms for the epression (B + A)C + AC + BC. Epanding the epression gives
More informationUNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A (2 MARKS)
SUBJECT NAME: DIGITAL LOGIC CIRCUITS YEAR / SEM : II / III DEPARTMENT : EEE UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1. What is variable mapping? 2. Name the two canonical forms for Boolean algebra.
More informationDepartment of Technical Education DIPLOMA COURSE IN ELECTRONICS AND COMMUNICATION ENGINEERING. Fifth Semester. Subject: VHDL Programming
Department of Technical Education DIPLOMA COURSE IN ELECTRONICS AND COMMUNICATION ENGINEERING Fifth Semester Subject: VHDL Programming Contact Hours/Week : 04 Contact Hours/Semester : 64 CONTENTS No. Of
More informationKING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT
KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class
More information