SDR Spring KOMSYS-F6: Programmable Digital Devices (FPGAs)

SDR Spring 2006 KOMSYS-F6: Programmable Digital Devices (FPGAs) Lecture 4 Jan Hvolgaard Mikkelsen Aalborg University 2006 Agenda What was the story about VHDL? o Quick recap from Lecture 3. Illustration of three different options/approaches for doing the system design and the corresponding mapping to an actual FPGA implementation. o o o Traditional VHDL approach. CORE Generator approach. SYSTEM Generator approach. There should have been a few exercises but the software is still playing tricks on me. 2/51

VHDL Abstraction Level We have seen that different hardware description languages have different abstraction levels. VHDL offers a good compromise but for large designs hardcore VHDL programming becomes a very difficult task. Again you should remember that there exist other HDL options such as Handel-C and augmented C/C++. 3/51 VHDL Basic Structure The basic structure of VHDL is simple but even for relatively simple designs the code grows. We need an entity and an architecture to define each block. Remember that regardless of textual order the lines are executed according to prescribed timing requirements. For sequential vs. parallel processing we had to make use of a process call also. Within a process execution is sequential. library IEEE; use IEEE.std_logic_1164.all; entity full_adder is port(in1, in2, c_in : in std_logic; sum, c_out : out std_logic); end full_adder; architecture dataflow of full_adder is signal s1, s2, s3 : std_ulogic; constant gate_delay : Time := 5 ns; begin L1: s1 <= (in1 xor in2) after gate_delay; L2: s2 <= (c_in and s1) after gate_delay; L3: s3 <= (in1 and in2) after gate_delay; L4: sum <= (c_in xor s1) after gate_delay; L5: c_out <= (s2 or s3) after gate_delay; end dataflow; 4/51

VHDL Structural Description It was is easy to reuse entities and ensure just a minimum of efficiency in the code simply by using VHDLs build-in hierarchal structure. This way it is possible to form more complicated structures without adding significantly to the code. Full adder Module composition. Wiring of modules. Design hierarchy. Divide and Conquer. 5/51 VHDL Structural Description In VHDL this hierarchical approach is handled through the use of a component construct. The component construct defines which external blocks that are needed within the architecture construct of a higher level block. Make the half_adder module known using the component declaration. Module instantiation. Connect ports and signals. 6/51

VHDL Simulating the Code Once the code is ready and all module descriptions have been implemented we of course want to verify the implemented code. Here we need to remember that more than just a module description is needed since a complete stimulus file also is required. A net list is required to describe the wanted module. To simulate and verify the operation of the module a complete stimulus description is required to drive the actual simulation. 7/51 VHDL Testbed To ensure that the verification runs as expected it is necessary to build a simulation test bed in VHDL also. The testbed is solely for testing the functionality of the UUT and is as such not a synthesizable part of the VHDL description. The testbed instantiates the UUT. By doing so the testbed is responsible for generating all inputs. The testbed should also contain information that would enable it to verify the outputs. This is often done graphically and by manual inspection at least for implementation that are not all too complex. 8/51

VHDL A Simple Testbed Once the signals have been wired up the actual test signals need to be defined. Since the test signals normally have to represent time events a sequential definition is required and this calls for the use of the process construct. No sensitivity list is needed. In this example the two signals a and b are first set to zero and then a time relation is established. This goes on until the single and final wait statement is encountered. This causes a single-shot run. Without the wait statement the simulation would continue in a cyclic execution loop. With this VHDL wrapper testbed script it is possible to simulate the module behavior. 9/51 FPGA Design Flow Tools VHDL is a nice tool for implementing smaller modules but for large system designs the VHDL-only tasks becomes rather cumbersome. To ease the design task almost any FPGA producer has its own software tool to support the design task. These tools are constantly being refined and current tools offer very efficient design flows. Depending on the specific tool different options may be available. o Access to huge IP libraries with a vast selection of different standard blocks. o Integration with well known simulation tool such as MATLAB/Simulink. Lattice o ispvm System o isplever Development tools Xilinx (ISE) o CORE Generator (COREgen) o System Generator (SYSgen) Altera o Quartus 10/51

Exampel LATTICE Tool There are of course differences between the different tools but there are also a lot of similarities. The tools offer access to IP blocks. They may interface to MATLAB and Simulink. The compile, place and routes the designs. The tools also enable the designer to maintain a structured overview of the system design. 11/51 Xilinx CORE Generator Here we will focus on the hardware and software tools available from Xilinx. The first step is to introduce the CORE Generator (COREgen). However, first let us recapture the design flow for a typical VHDL flow. HDL Behavioral Implement your design using VHDL or Verilog Synthesis Functional Implementation Download Timing In-Circuit Verification Two sets of code are required. The HDL code and the verification code. 12/51

Xilinx CORE Generator First the VHDL code is written and then it is tested using behavioral simulations in a test bench set up as we have seen previously. Once the (ideal) functional test is completed more realism is added. HDL Behavioral Synthesis Implementation Functional Timing Synthesize the design to create an FPGA netlist Download In-Circuit Verification 13/51 Xilinx CORE Generator After place and route a hardware simulation is possible to do the final test before downloading the finished code to the hardware for one last actual HW test. The implementation may take minutes, hours or even days depending on system complexity. 1 2 GB RAM is often required for larger designs. HDL Synthesis Implementation Download Behavioral Functional Timing In-Circuit Verification If the timing simulation fails the HDL code may have to be modified (significantly). Translate, place and route, and generate a bitstream to download in the FPGA 14/51

Xilinx CORE Generator Design verification using the Xilinx CORE Generator is very similar but it offers some short-cuts to optimize the design process. The COREgen is introduced as an integrated part of the VHDL coding task HDL COREGen Behavioral Instantiate optimized IP within the HDL code Synthesis Functional Implementation Timing Download In-Circuit Verification 15/51 Xilinx CORE Generator Through the use of COREgen very compact logic may be produced since this has been optimized by Xilinx who has the complete details on the hardware platform. Another advantage is that the different parts of COREgen are already know by the software tool (ISE). HDL COREGen Behavioral If the timing simulation fails COREgen parameters are changed and updated code is incl. Synthesis Implementation Download Functional Timing In-Circuit Verification Synthesize, Implement, and Download the bitstream, similar to the original design flow 16/51

Xilinx CORE Generator A wide range of blocks are available through COREgen. DSP Functions Math Functions Memory Functions $P Additive White Gaussian Noise (AWGN) $P Reed Solomon $ 3GPP Turbo Code $P Viterbi Decoder P Convolution Encoder $P Interleaver/De-interleaver P LFSR P 1D DCT P 2D DCT P DA FIR P MAC P MAC-based FIR filter Fixed FFTs 16, 64, 256, 1024 points P FFT 16- to 16384- points P FFT - 32 Point P Sine Cosine Look-Up Tables $P Turbo Product Code (TPC) P Direct Digital Synthesizer P Cascaded Integrator Comb P Bit Correlator P Digital Down Converter P Multiplier Generator - Parallel Multiplier - Dyn Constant Coefficient Mult - Serial Sequential Multiplier - Multiplier Enhancements P Pipelined Divider P CORDIC Base Functions P Binary Decoder P Twos Complement P Shift Register RAM/FF P Gate modules P Multiplexer functions P Registers, FF & latch based P Adder/Subtractor P Accumulator P Comparator P Binary Counter P Asynchronous FIFO P Block Memory modules P Distributed Memory P Distributed Mem Enhance P Sync FIFO (SRL16) P Sync FIFO (Block RAM) P CAM (SRL16) P CAM (Block RAM) IP CENTER http://www.xilinx.com/ipcenter Key: $ = License Fee, P = Parameterized (scalable), S = Project License Available, BOLD = Available in the Xilinx Blockset for the System Generator for DSP 17/51 Xilinx CORE Generator Illustration of the COREgen interface. COREgen is the delivery vehicle for IP blocks from Xilinx and other partners. Fully Parameterizable List of available IP from or 18/51

Xilinx CORE Generator Exercise 1: 1: Generating a MAC You will be generating the Multiply and Accumulate (MAC) using three different methods o Using VHDL and the Xilinx CORE Generator (Lecture 4). o Using the Xilinx System Generator (Lecture 5). You will compare the implementation procedures and contrast the design methodologies. You will compare the implementation results. 19/51 Xilinx CORE Generator Exercise 1: 1: Tasks and and Objectives Creating a MAC using a combination of VHDL and CORE Generator. Become familiar with the HDL and CORE Generator design flows which includes: Coding a piece of HDL. Generating CORE Generator macros. Instantiating the macros in HDL. Synthesizing a design using Xilinx XST. Implementation using Xiling ISE tools. Performing an on-chip verification with Chipscope-Pro. 20/51

Industry trends. o Trend towards platform chips (both FPGA and DPS) which leads to more complexity. o Highly flexible systems are required to meet many design tasks. o Challenges in modeling and implementing entire platforms. System design challenges. o Leveraging legacy HDL code. o Modeling and implementing control logic and data paths. o No experts exists that can cover all facets of a complete system design. It is therefore that we all strive for tools that have a high user abstraction level but where all the produced hardware/software is highly optimized. MATLAB represents one example of such a high-level tool where a huge number of specialized functions have been implemented and optimized over time. 21/51 The MathWorks has been developing system design tools since 1984. MATLAB is probably the most popular system design tool among engineers. It is in principle a programming language that offers an interpreter and a modeling environment. It offers extensive libraries for math functions, signal processing, DSP, communications, and much more. Visualization: large array of functions to plot and visualize your data and system/design. Open architecture: software model based on base system and domain-specific plugins. More information on The MathWorks and MATLAB is available at http://www.mathworks.com. 22/51

Example on the use of MATLAB for some signal processing. Here the frequency content of an input sound file is illustrated. Very simple job and even simpler visualizations. This METLAB example takes 1min. to implement but the same in an FPGA would take days to implement if from scratch. 23/51 Simulink - Visual data flow environment for modeling and simulation of dynamical systems. Simulink is fully integrated with the MATLAB engine. MATLAB code may be invoked from within Simulink. It has a graphical block editor which corresponds nicely with the fact that most hardware design starts out as block diagrams. Event-driven simulator It models parallelism/concurrency which is fundamental for implementation of highperformance hardware. There is an extensive library of parameterizable functions available. o Simulink Blockset - math, sinks, sources. o o DSP Blockset - filters, transforms, etc. Communications Blockset - modulation, DPCM, etc. 24/51

An example of the use of SIMULINK for a signal processing application. Here a real time frequency response from a microphone is illustrated. This emphasizes the dynamic nature of Simulink. 25/51 Traditionally there has been a gab between the system designer working in MATLAB/SIMULINK and the hardware designer that would have to implement the actual design. System Architect System Verification GAP Simulink FPGA Designer HDL Synthesis Functional Verify Equivalence Implementation Timing Download In-Circuit Verification 26/51

This gab is where the SYSTEM Generator tool from Xilinx comes into the picture. Industry s system-level design environment (IDE) for FPGAs. o o Integrated design flow from Simulink to bit file. Leverages existing technologies. Matlab/Simulink R13.1 or R14 from The MathWorks HDL synthesis IP Core libraries FPGA implementation tools Simulink library of arithmetic, logic operators and DSP functions (Xilinx Blockset). o Currently more than 61 different blocks are available and around 30 logicores are targeted. o Nine categories; Basic elements, Communications, Control logic, Data types, DSP, Index, Math, Memory, Tools. o Bit and cycle true to FPGA implementation. o Each block is bit and cycle true. Arithmetic abstraction o Arbitrary precision fixed-point, including quantization and overflow o of double precision as well as fixed point 27/51 The SYSTEM Generator offers support for all Xilinx FPGA platforms. It specifically offers VHDL code generation for Virtex-4, Virtex-II Pro, Virtex -II, Virtex -E, Virtex, Spartan -3, Spartan -IIE and Spartan -II devices. o Hardware expansion and mapping o Synthesizable VHDL with model hierarchy preserved o Mixed language support for Verilog o Automatic invocation of CORE Generator to utilize IP cores o ISE project generation to simplify the design flow o HDL testbench and test vector generation o Constraint file (.xcf), simulation.do files generation o HDL Co- via HDL C- Verification acceleration using Hardware in the Loop. 28/51

The System Generator provides a convenient way to perform HDL co-simulation and Hardware in the loop simulation using Black Box block. The black box can be used to incorporate hardware description language (HDL) models into System Generator. 29/51 It is possible to use only Xilinx System Generator s blocks in the design and generate a synthesizable design which can be implemented using Xilinx ISE s Project Navigator. No user defined blocks are included. It is a quick way to design a system. MATLAB/Simulink HDL System Generator System Verification Synthesis Functional Implementation Timing Download In-Circuit Verification Option 1. 30/51

Another approach, typically used for HDL co-simulation, is to use black box and include user VHDL code or 3 rd party IP cores along with Xilinx System Generator blocks. The Xilinx simulator, ModelSim, may also be invoked and asked to parse results back to Simulink. MATLAB/Simulink HDL System Generator Synthesis System Verification Functional Files Used Configuration file VHDL IP Constraints File Implementation Timing HDL-Co Download In-Circuit Verification Option 2. 31/51 For Hardware in the Loop verification a 3rd option is possible. Here a synthesizable design is produced and used to generate a configuration bit file that is downloaded to the hardware. The HW response is then included in the Simulink simulation. MATLAB/Simulink HDL System Generator Synthesis System Verification Functional Files Used Configuration file VHDL IP Constraints File Implementation Timing Download In-Circuit Verification Option 3. 32/51

The use of the SYSTEM Generator is very simple. First the Simulink library browser needs to be invoked. To open the Simulink library browser, simply click the Simulink library browser button or type Simulink in MATLAB console. The library browser contains all the blocks that are available to designer. Start a new design by clicking the new sheet button. With the System Generator installed there will be some Xilinx folders available. These blocks contain all the required functionality to emulate the hardware performance finite resolution fx. Blocks capable of producing VHDL code based on the Simulink setup are also available. 33/51 Build the design by dragging and dropping blocks from the Xilinx blockset onto your new sheet. Design Entry is similar to a schematic editor. Connect up blocks by pulling the arrows on the sides of each block 34/51

Use the Find feature to search ALL Simulink libraries. Xilinx blockset has nine major sections. o Basic elements Counters, delays o Communication Error correction blocks o Control Logic MCode, Black Box o Data Types Convert, Slice o DSP FDATool, FFT, FIR o Index All Xilinx blocks quick way to view all blocks o Math Multiply, accumulate, inverter o Memory Dual Port RAM, Single Port RAM o Tools ModelSim, Resource Estimator 35/51 Double-click or go to Block Parameters to view a block s configurable parameters. o Arithmetic Type: Unsigned or twos complement o Implement with Xilinx Smart-IP Core (if possible)/ Generate Core o Latency: Specify the delay through the block o Overflow and Quantization: Users can saturate or wrap overflow. Truncate or Round Quantization o Override with Doubles: only o Precision: Full or the user can define the number of bits and where the decimal point is for the block o Sample Period: Can be inherent with a -1 or must be an integer value Note: While all parameters can be simulated, not all are realizable. 36/51

You can also enter equations in the block parameters, which can aid calculation and your own understanding of the model parameters The equations are calculated at the beginning of a simulation Useful MATLAB operators o + add o - subtract o * multiply o / divide o ^ power o π pi (3.1415926535897. ) o exp(x) exponential (ex) 37/51 THE NUMBERS GAME. Simulink uses a double to represent numbers in a simulation. A double is a 64-bit twos complement floating point number. Because the binary point can move, a double can represent any number between +/- 9.223 x 10 18 with a resolution of 1.08 x 10-19 a wide and very desirable range, but not efficient or realistic for FPGAs. Xilinx Blockset uses n-bit fixed point number (twos complement optional). -2 2 2 1 2 0 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 Value = -2.261108 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 Format = Fix_16_13 Integer Fraction (Sign: Fix = Signed Value Format = Sign_Width_Decimal point from the LSB UFix = Unsigned value) Design Hint: Always try to maximize the dynamic range of design by using only the required number of bits Thus, a conversion is required when communicating with Xilinx blocks with Simulink blocks (Xilinx blockset MATLAB I/O Gateway In/Out) 2-13 38/51

AND THE OTHER BITS? The Gateway In and Out blocks support parameters to control the conversion from double precision to N - bit fixed point precision..... 2 4 2 3-2 6 2 5 1 1 1 1 DOUBLE 2 2 2 1 2 0 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 2-13.... OVERFLOW -Wrap - Saturate - Flag Error -2 2 2 1 2 0 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 1 0 1 1 0 1 1 1 1 0 1 0 FIX_12_9 QUANTIZATION - Truncate - Round 39/51 The Xilinx Blockset also uses the type Boolean for control ports like CE and RESET. The Boolean type is a variant on the 1-bit unsigned number in that it will always be defined (High or Low). A 1-bit unsigned number can become invalid; a Boolean type cannot. 40/51

Fractional numbers. Using the technique shown, convert the following fractional values Define the format of the following twos complement binary fraction and calculate the value it represents Format = < > 1 1 0 0 0 1 1 0 1 0 1 1 Value = What format should be used to represent a signal that has: a) Max value: +1 Min value: -1 Quantized to 12 bit data b) Max value: 0.8 Min value: 0.2 Quantized to 10 bit data c) Max value: 278 Min value: -138 Quantized to 11 bit data Format = < > Format = < > Format = < > Fill in the table: Operation <Fix_12_9> + <Fix_8_3> <Fix_8_7> x <Ufix_8_6> Full Precision Output Type 41/51 A System Generator design consists of distinct sections. Some that are hardware realizable, some gateway functions and finally some sources and sinks. I/O blocks used as interface between the Xilinx Blockset and other Simulink blocks Blue: HW Yellow: fix point Green: support Simulink sources SysGen blocks realizable in Hardware Simulink sinks and library functions 42/51

The sample period specification is very important. Every SysGen signal must be sampled ; transitions occur at equidistant discrete points in time called sample times. Each block in a Simulink design has a Sample Period and it corresponds to how often that block s function is calculated and the results outputted. This sample period must be set explicitly for: Gateway in. Blocks w/o inputs (note: constants are idiosyncratic). Sample period can be derived from input sample times for other blocks. A sample period of 0 equates to an analog signal. This is not supported by Xilinx blocks. A sample period of -1 means that the block inherits the sampling frequency of the data input. An example of Blocks w/o inputs: counters. 43/51 The units of the sample period can be thought of as arbitrary, BUT a lot of Simulink source blocks do have an essence of time. o For example, a sample period of 1/44100 means the block s function will be executed every 1/44100 of a sec. Remember Nyquist Theorem (Fs 2f max ) when setting sample periods. The sample period of a block DIRECTLY relates to how that block will be clocked in the actual hardware. 44/51

The Simulink System Period MUST be set in the System Generator token. For single rate systems it will be the same as the Sample Periods set in the design. More on Multi Rate designs later Sample Period = 1 45/51 Master Controls Slave Controls Simulink System Period MUST be set correctly for simulation to work 46/51

Click Properties to change the number of axes displayed and the time range value (X-axis) Use the Data History tab to control how many values are stored and displayed on the scope o Also can direct output to workspace Click Autoscale to quickly let the tools configure the display to the correct axis values Right-click on the Y-axis to set its value 47/51 Push play to simulate the design. Go to Parameters under the menu to control the length of simulations 48/51

Full VHDL/Verilog (Instantiating Primitives) o o Advantages: Full access to all architecture features Carry on further with optimization Best optimization Disadvantages: Not as portable as RTL VHDL/Verilog Must be an FPGA expert and know the architecture Time-consuming 49/51 CORE Generator o Advantages o Can quickly access and generate existing functions No need to reinvent the wheel and re-design a block if it meets specifications IP is optimized for the specified architecture Disadvantages IP doesn t always do exactly what you are looking for Need to understand signals and parameters and match them to your specification Dealing with black box and have little information on how the function is implemented 50/51

System Generator for DSP o Advantages o Huge productivity gains through high-level modeling Ability to simulate the complete designs at a system level Very attractive for FPGA novices Excellent capabilities for designing complex testbenches HDL Testbench, test vector and golden data written automatically Hardware in the loop simulation improves productivity and provides quick verification of the system functioning correctly or not Disadvantages Minor cost of abstraction: doesn t always give the best result from an area usage point of view Customer may not be familiar with Simulink Not well suited to multiple clock designs No bi-directional bus supported 51/51