Lecture 3: Modeling in VHDL. EE 3610 Digital Systems
|
|
- Sheena Richards
- 6 years ago
- Views:
Transcription
1 EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL
2 VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware Other languages: Verilog, Verilog-AMS (Analog and Mixed Signal)
3 VHDL: Overview 3 Benefits Public Standard Technology and Process Independent Include technology via libraries Supports a variety of design methodologies Behavioral modeling Dataflow or RTL (Register Transfer Language) Modeling: We won t use it Structural or gate level modeling
4 VHDL: Overview 4 Model Mathematical Description of a physical device Simulation Analysis (automated) of a model given a set of inputs Digital Circuit Models Structural: defines sub-models and how they are interconnected (FFs, Gates, etc) Behavioral: defines the behavior of the circuit (no actual components)
5 HDL: Then 5 Originally designed for simulation only Start with behavioural models and slowly replace them with structural models Reduce these to FFs and Gates Try and Test
6 HDL: Now 6 Build behavioral models and Simulate Synthesize to net-list (generic) Fit to a device Simulate the new (wholly structural) model Try and test
7 Levels of Abstraction: Behavioral, Structural, Physical 7 S <=AB S Behavioral (Algorithms, Dataflow) Structural (Components, interconnections) Physical
8 Combinational Circuits 8 C<=A and B after 5 ns; E<=C or D after 5 ns; explicit declaration of delay to update the change 1) Suppose initial Values: A=1, B=C=D=E=0 2) At t=0 ns: B=1 3) At t=5 ns: C=1 4) At t=10 ns: E=1 5) If delay is not specified, then a minimum is assumed
9 Combinational Circuits 9 Concurrent Statements C<=A and B after 5 ns; E<=C or D after 5 ns; Order is not important E<=C or D after 5 ns; C<=A and B after 5 ns;
10 Combinational Circuits This statement causes a simulation error 10 CLK <= not CLK;
11 Combinational Circuits Repetition of Concurrent Statements CLK <= not CLK after 10 ns; 11 1) Implicit Loop 2) Toggles between 1 and 0 after updating the signal at every 10 ns 3) Will continue indefinitely
12 Combinational Circuits Concurrent Statements 12 1) Statements are executed simultaneously 2) D, E, F are updated at different times 3) Can specify different gate delays within cocurrent statements
13 VHDL: Elements Entity:-Description of interface consisting of the port list -The primary hardware abstraction in VHDL, -Analogous to a symbol in a block diagram. Architecture: Description of the function of the corresponding module. Process: Allows for a sequential execution of the assignments Configuration: Used for simulation purposes. Package: Hold the definition of commonly used data types, constants and subprograms. Library: -The logical name of a collection of compiled VHDL units (object code) -Mapped by the simulation or synthesis tools 13
14 VHDL: Example Code Write the code for the following circuit: 14
15 VHDL: Example Code 15 entity example is port (x1,x2,x3: in std_logic; f: out std_logic); end example; ARCHITECTURE logicfunc of example is begin -- Architecture statement region f <= (x1 AND x2) NOR (NOT x2 AND x3); end logicfunc; name defined by the user
16 Code Flow 16
17 Six Phases (1) Compilation: Code Flow Checks the code to see that the syntax and semantic rules are met, references to libraries are correct Outputs intermediate code to be used by Simulator (2) Elaboration: A driver is created for each signal Each driver holds the current value of signal and a queue of future signal values Ports are created for each component, memory storage is allocated, interconnection between port signals specified 17
18 Code Flow Six Phases (continued ) (3) Simulation: Simulator takes simulation commands Passage of time is simulated in discrete steps VHDL statements are executed and actions are scheduled Whenever a component input changes, the output is scheduled to change after specified delay or some delay After all inputs are processed, simulated time is advanced and counter is reset 18
19 Code Flow Six Phases (continued ) (4) Synthesis: Translate VHDL code to a circuit description Compilation and Elaboration: same as Simulation Usually Synthesis comes after Simulation List of required components and interconnections is produced (5) Implementation: Output of Synthesizer is used to implement the digital system using specific hardware, e.g. CPLD, FPGA, ASIC ASIC: masks may be generated CPLD/FPGA: generates bit-map 19
20 Code Flow (5) Implementation (continued ): TRANSLATE: converts the netlist generated from the synthesis process, into a form specific to the target device (e.g. Xilinx FPGA). MAP: translates the standard building blocks into the specific resources available in the target hardware PLACE & ROUTE: picks up where the MAP process leaves off by allocating specific resources (placing) and interconnecting (routing) the placed design, places and routes the design to the timing constraints Can perform a post-place and route simulation (6) Hardware: Binary programming file is generated (bitstream) and downloaded to the FPGA 20
21 Inside of a Bit File: Lab 0 Hexadecimal Format 21
22 SIDE NOTES: INSIDE THE FPGA 22
23 SIDE NOTES: INSIDE THE FPGA 23 CLB=Configurable Logic Block=4 Slices Slice=> two Look Up Table (LUT)s and two Flip Flops
24 SIDE NOTES: LUT Implementation [1/2] LUT is implemented with small RAM Four input bits act as an address bus: select output bit based on four input bits addressing one of 16 stored bits 24 Io I1 I2 I3 Out
25 16:1 MUX SIDE NOTES: LUT Implementation [2/2] 25 16:1 Addressable Shift Register
26 Example 1: Pin Assignments (Lab 0) NET "SW0" LOC = "L13"; NET "SW1" LOC = "L14"; 26 Set this signal (which is a port in the top level module) to pin L13 on the FPGA entity top is Port ( SW0 : in STD_LOGIC; SW1 : in STD_LOGIC; LED0 : out STD_LOGIC); end top; NET "LED0" LOC = "F12" IOSTANDARD = LVTTL SLEW = SLOW DRIVE = 8 ; Set input output standard to transistor-transistor logic, slew rate (rate of transition for each output), and current level to 8 ma
27 Example 2: 1-bit Full Adder Co = A B + A Ci + B Ci; S=A + B + Ci 27 entity FullAdder is port (A,B,Ci: in bit Co,S: out bit end FullAdder; architecture Eq of FullAdder is begin S <= A xor B xor Ci; Co <= (A and b) or (A and Ci) or (B and Ci); end Eq; Use ( )to specify order of precedence
28 Predefined Operators There are seven groups of predefined VHDL operators: Binary logical operators: and or nand nor xor xnor 2. Relational operators: = /= < <= > >= 3. Shifts operators: sll srl sla sra rol ror 4. Adding operators: + - &(concatenation) 5. Unary sign operators: Multiplying operators: * / mod rem 7. Miscellaneous operators: not abs **
29 Predefined Operators: Order of Precedence [1/2] Highest precedence first, left to right within same precedence group, use parenthesis to control order. Unary operators take an operand on the right. "result same" means the result is the same as the right operand. Binary operators take an operand on the left and right. "result same" means the result is the same as the left operand. 29 ** exponentiation, numeric ** integer, result numeric abs absolute value, abs numeric, result numeric not complement, not logic or boolean, result same * multiplication, numeric * numeric, result numeric / division, numeric / numeric, result numeric mod modulo, integer mod integer, result integer rem remainder, integer rem integer, result integer + unary plus, + numeric, result numeric - unary minus, - numeric, result numeric + addition, numeric + numeric, result numeric - subtraction, numeric - numeric, result numeric & concatenation, array or element & array or element, result array Reserved Words:
30 Predefined Operators: Order of Precedence [2/2] sll shift left logical, logical array sll integer, result same srl shift right logical, logical array srl integer, result same sla shift left arithmetic, logical array sla integer, result same sra shift right arithmetic, logical array sra integer, result same rol rotate left, logical array rol integer, result same ror rotate right, logical array ror integer, result same 30 = test for equality, result is boolean /= test for inequality, result is boolean < test for less than, result is boolean <= test for less than or equal, result is boolean > test for greater than, result is boolean >= test for greater than or equal, result is boolean and logical and, logical array or boolean, result is same or logical or, logical array or boolean, result is same nand logical complement of and, logical array or boolean, result is same nor logical complement of or, logical array or boolean, result is same xor logical exclusive or, logical array or boolean, result is same xnor logical complement of exclusive or,logical array or boolean, result is same Reserved Words:
31 Example 3: Priority of Operators Let A= 110, B= 111, C= , and D= (A & not B or C ror 2 and D)= Order: not, &, ror, or, and, = 1) not B = bit-by-bit complement 2) A & not B = concatenation 3) C ror 2 = rotate right 2 places 4) (A & not B) or (C ror 2) = bit-by-bit or 5) (A & not B or C ror 2) and D = bit-by-bit and 6) [(A & not B or C ror 2 and D) = ]=TRUE=1 --with parentheses the equality test is done last 31
32 Example 4: Concurrent Statement (4-bit mux) entity mux4 is port (I0, I1, I2, I3: in std_logic; Select: in std_logic_vector (1 downto 0); Y: out bit); end mux4; architecture dude of mux4 is begin Y <= I0 when select = 00 ; else I1 when select = 01 ; else I2 when select = 10 ; else I3; end dude; 32
33 4 bit Ripple Carry Adder
34 4 bit Ripple Carry Adder 4 bit Ripple Carry Adder with Hierarchical Design entity Adder4 is port (A,B: in bit_vector(3 downto 0); Ci: in bit --inputs S: out bit_vector(3 downto 0); Co: out bit--outputs end Adder4; architecture Structure of Adder4 is component FullAdder is port (X,Y,Cin: in bit --inputs Cout,Sum: out bit --outputs end component; Can create component declarations in a libary file signal C: bit_vector (3_downto 1); --C is internal signal begin ---create 4 copies of FullAdder FA0: FullAdder port map (A(0),B(0),Cin,C(1),S(0)); FA1: FullAdder port map (A(1),B(1),C(1),C(2),S(1)); FA2: FullAdder port map (A(2),B(2),C(2),C(3),S(2)); FA3: FullAdder port map (A(3),B(3),C(3),Co,S(3)); end Structure
35 4 bit Ripple Carry Adder entity Adder4 is port (A,B: in bit_vector(3 downto 0); Ci: in bit --inputs S: out bit_vector(3 downto 0); Co: out bit--outputs end Adder4; architecture Structure of Adder4 is component FullAdder is port (X,Y,Cin: in bit --inputs Cout,Sum: out bit --outputs end component; signal C: bit_vector (3_downto 1); --C is internal signal begin ---create 4 copies of FullAdder FA0: FullAdder port map (Y=>B(0), X=>A(0),Sum=>S(0), Cin=>Ci);. end Structure.. With named association order doesn't matter
36 VHDL: Common Mistakes Avoid Common Mistakes: [1] [2] VHDL Guides: [1] 36
IT T35 Digital system desigm y - ii /s - iii
UNIT - V Introduction to Verilog Hardware Description Language Introduction HDL for combinational circuits Sequential circuits Registers and counters HDL description for binary multiplier. 5.1 INTRODUCTION
More informationHardware Description Language VHDL (1) Introduction
Hardware Description Language VHDL (1) Introduction Digital Radiation Measurement and Spectroscopy NE/RHP 537 Introduction Hardware description language (HDL) Intended to describe circuits textually, for
More informationAbi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University
Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL Defined in 1980s by U.S.
More informationC-Based Hardware Design
LECTURE 6 In this lecture we will introduce: The VHDL Language and its benefits. The VHDL entity Concurrent and Sequential constructs Structural design. Hierarchy Packages Various architectures Examples
More informationELCT 501: Digital System Design
ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)
More informationEECE-4740/5740 Advanced VHDL and FPGA Design. Lecture 3 Concurrent and sequential statements
EECE-4740/5740 Advanced VHDL and FPGA Design Lecture 3 Concurrent and sequential statements Cristinel Ababei Marquette University Department of Electrical and Computer Engineering Overview Components hierarchy
More informationLogic and Computer Design Fundamentals VHDL. Part 1 Chapter 4 Basics and Constructs
Logic and Computer Design Fundamentals VHDL Part Chapter 4 Basics and Constructs Charles Kime & Thomas Kaminski 24 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Overview
More informationDigital Systems Design
Digital Systems Design Review of Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits Dr. D. J. Jackson Lecture 2-1 Introduction to VHDL Designer writes a logic circuit description in
More informationContents. Appendix D VHDL Summary Page 1 of 23
Appendix D VHDL Summary Page 1 of 23 Contents Appendix D VHDL Summary...2 D.1 Basic Language Elements...2 D.1.1 Comments...2 D.1.2 Identifiers...2 D.1.3 Data Objects...2 D.1.4 Data Types...2 D.1.5 Data
More information!"#$%&&"'(')"*+"%,%-".#"'/"'.001$$"
!"#$%&&"'(')"*+"%,%-".#"'/"'.001$$"!!"#$%&'#()#*+"+#,-."/0110#230#4."50",+"+#)6# 6+-+#(.6+-0#)4475.8)60#0/#.65-0#230#9+**+"+# 2.48).-0#(.6+-0#! 2+"*5."5*:#,."/0110#;)**0! *),".6*:#-.99-0*0"5."+#2+660,.40"5)#;)*)2)#
More informationCS211 Digital Systems/Lab. Introduction to VHDL. Hyotaek Shim, Computer Architecture Laboratory
CS211 Digital Systems/Lab Introduction to VHDL Hyotaek Shim, Computer Architecture Laboratory Programmable Logic Device (PLD) 2/32 An electronic component used to build reconfigurable digital circuits
More informationECEN 468 Advanced Logic Design
ECEN 468 Advanced Logic Design Lecture 26: Verilog Operators ECEN 468 Lecture 26 Operators Operator Number of Operands Result Arithmetic 2 Binary word Bitwise 2 Binary word Reduction 1 Bit Logical 2 Boolean
More information5. 0 VHDL OPERATORS. The above classes are arranged in increasing priority when parentheses are not used.
Filename= ch5.doc 5. 0 VHDL OPERATORS There are seven groups of predefined VHDL operators: 1. Binary logical operators: and or nand nor xor xnor 2. Relational operators: = /= < >= 3. Shifts operators:
More informationVHDL. Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit
VHDL VHDL Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit VHDL Alternative (Student Generated) Definition Very Hard Digital Logic language VHDL Design
More informationVHDL BASIC ELEMENTS INTRODUCTION
VHDL BASIC ELEMENTS INTRODUCTION VHDL Basic elements Identifiers Basic identifiers Extended identifiers Data Objects Constant Variable Signal File Data Types Scalar Composite Access File type Identifiers
More informationECOM4311 Digital Systems Design
ECOM 4311 Digital Systems Design Eng. Monther Abusultan Computer Engineering Dept. Islamic University of Gaza Page 1 Agenda 1. VHDL : Data Types Cont d 2. VHDL : Operators 3. VHDL : Signal Assignments
More informationCSCI Lab 3. VHDL Syntax. Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\
CSCI 250 - Lab 3 VHDL Syntax Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\ Objectives 1. Learn VHDL Valid Names 2. Learn the presentation of Assignment and Comments 3. Learn Modes, Types, Array,
More informationEmbedded Systems CS - ES
Embedded Systems - 1 - REVIEW Hardware/System description languages VDHL VHDL-AMS SystemC TLM - 2 - VHDL REVIEW Main goal was modeling of digital circuits Modelling at various levels of abstraction Technology-independent
More informationVHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning
VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Cengage Learning Design Flow 418_02 2 VHDL Modules 418_02 3 VHDL Libraries library IEEE; use IEEE.std_logic_1164.all; std_logic Single-bit
More informationECE4401 / CSE3350 ECE280 / CSE280 Digital Design Laboratory
ECE4401 / CSE3350 ECE280 / CSE280 Digital Design Laboratory Instructor John Chandy Office: ITEB 437 Office Hours: W10-12 Tel: (860) 486-5047 Email: john.chandy@uconn chandy@uconn.edu Class home page: HuskyCT
More informationEE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 4 Introduction to VHDL
EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 4 Introduction to VHDL Read before class: Chapter 2 from textbook (first part) Outline VHDL Overview VHDL Characteristics and Concepts
More informationBASIC VHDL LANGUAGE ELEMENTS AND SEMANTICS. Lecture 7 & 8 Dr. Tayab Din Memon
BASIC VHDL LANGUAGE ELEMENTS AND SEMANTICS Lecture 7 & 8 Dr. Tayab Din Memon Outline Data Objects Data Types Operators Attributes VHDL Data Types VHDL Data Objects Signal Constant Variable File VHDL Data
More informationReview of Digital Design with VHDL
Review of Digital Design with VHDL Digital World Digital world is a world of 0 and 1 Each binary digit is called a bit Eight consecutive bits are called a byte Hexadecimal (base 16) representation for
More informationCOE 405 Design Methodology Based on VHDL
COE 405 Design Methodology Based on VHDL Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Elements of VHDL Top-Down Design Top-Down Design with
More informationIntroduction to VHDL #1
ECE 3220 Digital Design with VHDL Introduction to VHDL #1 Lecture 3 Introduction to VHDL The two Hardware Description Languages that are most often used in industry are: n VHDL n Verilog you will learn
More informationA bird s eye view on VHDL!
Advanced Topics on Heterogeneous System Architectures A bird s eye view on VHDL Politecnico di Milano Conference Room, Bld 20 19 November, 2015 Antonio R. Miele Marco D. Santambrogio Politecnico di Milano
More informationECE U530 Digital Hardware Synthesis. Course Accounts and Tools
ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu Sept 13, 2006 Lecture 3: Basic VHDL constructs Signals, Variables, Constants VHDL Simulator and Test benches Types Reading: Ashenden
More informationHDL. Hardware Description Languages extensively used for:
HDL Hardware Description Languages extensively used for: Describing (digital) hardware (formal documentation) Simulating it Verifying it Synthesizing it (first step of modern design flow) 2 main options:
More informationFPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
More informationVHDL 3 BASIC OPERATORS AND ARCHITECTURE BODY. Design descriptions & design constructions examples are taken from foundation series examples
1 VHDL 3 BASIC OPERATORS AND ARCHITECTURE BODY Design descriptions & design constructions examples are taken from foundation series examples 2 What we have done in Lab 1 entity AND_Gate is port ( a : in
More informationLecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)
Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable
More informationVHDL Structural Modeling II
VHDL Structural Modeling II ECE-331, Digital Design Prof. Hintz Electrical and Computer Engineering 5/7/2001 331_13 1 Ports and Their Usage Port Modes in reads a signal out writes a signal inout reads
More informationECE 3401 Lecture 10. More on VHDL
ECE 3401 Lecture 10 More on VHDL Outline More on VHDL Some VHDL Basics Data Types Operators Delay Models VHDL for Simulation VHDL for Synthesis 1 Data Types Every signal has a type, type specifies possible
More information! Initially developed under DOD auspices, later standardized as IEEE standards , , & (standard logic data type)
VHDL Introduction, Part I Figures in this lecture are from: Rapid Prototyping of Digital Systems, Second Edition James O. Hamblen & Michael D. Furman, Kluwer cademic Publishers, 2001, ISN 0-7923-7439-8
More informationDesign units can NOT be split across different files
Skeleton of a Basic VHDL Program This slide set covers the components to a basic VHDL program, including lexical elements, program format, data types and operators A VHDL program consists of a collection
More informationVHDL Objects. Lecture 8: VHDL (2) Variables. VHDL Objects - Constant. Files. EE3109 Gopi K. Manne Fall 2007
Lecture 8: VHDL (2) VHDL Objects Four types of objects in VHDL Constants Variables Computer Aided Digital Design EE3109 Gopi K. Manne Fall 2007 Signals Files The scope of an object is as follows : Objects
More informationLecture 12 VHDL Synthesis
CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?
More informationPerformance Engineering of Real-Time and Embedded Systems. Introduction to VHDL
Performance Engineering of Real-Time and Embedded Systems Introduction to VHDL VHDL designs are decomposed into blocks. A block has an entity/architecture pair. Entity describes the interface Architecture
More informationECE 545 Lecture 5. Data Flow Modeling in VHDL. George Mason University
ECE 545 Lecture 5 Data Flow Modeling in VHDL George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 4, Concurrent Signal Assignment Statements of VHDL 2 Types of VHDL Description
More informationDigital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
More informationWhat Is VHDL? VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE 1076 standard (1987, 1993)
What Is VHDL? VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE 1076 standard (1987, 1993) Only possible to synthesize logic from a subset of VHDL Subset varies according to
More informationEEL 4783: Hardware/Software Co-design with FPGAs
EEL 4783: Hardware/Software Co-design with FPGAs Lecture 9: Short Introduction to VHDL* Prof. Mingjie Lin * Beased on notes of Turfts lecture 1 What does HDL stand for? HDL is short for Hardware Description
More informationPINE TRAINING ACADEMY
PINE TRAINING ACADEMY Course Module A d d r e s s D - 5 5 7, G o v i n d p u r a m, G h a z i a b a d, U. P., 2 0 1 0 1 3, I n d i a Digital Logic System Design using Gates/Verilog or VHDL and Implementation
More informationyamin/
http://cis.k.hosei.ac.jp/ yamin/ Verilog HDL p.1/76 HDL Verilog HDL IEEE Standard 1364-1995 (Verilog-1995) IEEE Standard 1364-2001 (Verilog-2001) VHDL VHSIC HDL IEEE Standard 1076-1987 AHDL Altera HDL
More informationVHDL simulation and synthesis
VHDL simulation and synthesis How we treat VHDL in this course You will not become an expert in VHDL after taking this course The goal is that you should learn how VHDL can be used for simulation and synthesis
More informationVHDL Part 2. What is on the agenda? Basic VHDL Constructs. Examples. Data types Objects Packages and libraries Attributes Predefined operators
VHDL Part 2 Some of the slides are taken from http://www.ece.uah.edu/~milenka/cpe428-02s/ What is on the agenda? Basic VHDL Constructs Data types Objects Packages and libraries Attributes Predefined operators
More informationVLSI DESIGN (ELECTIVE-I) Question Bank Unit I
VLSI DESIGN (ELECTIVE-I) Question Bank Unit I B.E (E&C) NOV-DEC 2008 1) If A & B are two unsigned variables, with A = 1100 and B = 1001, find the values of following expressions. i. (A and B) ii. (A ^
More informationOutline. CPE/EE 422/522 Advanced Logic Design L07. Review: JK Flip-Flop Model. Review: VHDL Program Structure. Review: VHDL Models for a MUX
Outline CPE/EE 422/522 Advanced Logic Design L07 Electrical and Computer Engineering University of Alabama in Huntsville What we know How to model Combinational Networks in VHDL Structural, Dataflow, Behavioral
More informationCPE/EE 422/522. Chapter 8 - Additional Topics in VHDL. Dr. Rhonda Kay Gaede UAH. 8.1 Attributes - Signal Attributes that return a value
CPE/EE 422/522 Chapter 8 - Additional Topics in VHDL Dr. Rhonda Kay Gaede UAH 1 8.1 Attributes - Signal Attributes that return a value A event true if a has just occurred A active true if A has, even if
More informationOutline. CPE/EE 422/522 Advanced Logic Design L05. Review: General Model of Moore Sequential Machine. Review: Mealy Sequential Networks.
Outline CPE/EE 422/522 Advanced Logic Design L05 Electrical and Computer Engineering University of Alabama in Huntsville What we know Combinational Networks Sequential Networks: Basic Building Blocks,
More informationHardware Modeling. VHDL Syntax. Vienna University of Technology Department of Computer Engineering ECS Group
Hardware Modeling VHDL Syntax Vienna University of Technology Department of Computer Engineering ECS Group Contents Identifiers Types & Attributes Operators Sequential Statements Subroutines 2 Identifiers
More informationTwo HDLs used today VHDL. Why VHDL? Introduction to Structured VLSI Design
Two HDLs used today Introduction to Structured VLSI Design VHDL I VHDL and Verilog Syntax and ``appearance'' of the two languages are very different Capabilities and scopes are quite similar Both are industrial
More informationLecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1
Lecture 1: VHDL Quick Start Digital Systems Design Fall 10, Dec 17 Lecture 1 1 Objective Quick introduction to VHDL basic language concepts basic design methodology Use The Student s Guide to VHDL or The
More informationComputer-Aided Digital System Design VHDL
بس م اهلل الر حم ن الر حی م Iran University of Science and Technology Department of Computer Engineering Computer-Aided Digital System Design VHDL Ramin Rajaei ramin_rajaei@ee.sharif.edu Modeling Styles
More informationENGIN 241 Digital Systems with Lab
ENGIN 241 Digital Systems with Lab (4) Dr. Honggang Zhang Engineering Department University of Massachusetts Boston 1 Introduction Hardware description language (HDL): Specifies logic function only Computer-aided
More informationOutline CPE 626. Advanced VLSI Design. Lecture 4: VHDL Recapitulation (Part 2) Signals. Variables. Constants. Variables vs.
CPE 626 Lecture 4: VHDL Recapitulation (Part 2) Aleksandar Milenkovic http://www.ece.uah.edu/~milenka http://www.ece.uah.edu/~milenka/cpe626-04f/ milenka@ece.uah.edu Assistant Professor Electrical and
More informationCSE140L: Components and Design Techniques for Digital Systems Lab. Verilog HDL. Instructor: Mohsen Imani UC San Diego. Source: Eric Crabill, Xilinx
CSE140L: Components and Design Techniques for Digital Systems Lab Verilog HDL Instructor: Mohsen Imani UC San Diego Source: Eric Crabill, Xilinx 1 Hardware description languages Used to describe & model
More informationHardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University
Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis
More informationVHDL. VHDL History. Why VHDL? Introduction to Structured VLSI Design. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language
VHDL Introduction to Structured VLSI Design VHDL I Very High Speed Integrated Circuit (VHSIC) Hardware Description Language Joachim Rodrigues A Technology Independent, Standard Hardware description Language
More informationThis Lecture. Some components (useful for the homework) Verilog HDL (will continue next lecture)
Last Lecture The basic component of a digital circuit is the MOS transistor Transistor have instrinsic resistance and capacitance, so voltage values in the circuit take some time to change ( delay ) There
More informationUNIT I Introduction to VHDL VHDL: - V -VHSIC, H - Hardware, D - Description, L Language Fundamental section of a basic VHDL code Library :
UNIT I Introduction to VHDL VHDL stands for very high-speed integrated circuit hardware description language. Which is one of the programming languages used to model a digital system by dataflow, behavioral
More informationECE 545 Lecture 12. FPGA Resources. George Mason University
ECE 545 Lecture 2 FPGA Resources George Mason University Recommended reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional Details 2 What is an FPGA? Configurable Logic Blocks
More informationElektrotechnik und Informationstechnik, Stiftungsprofessur hochparallele VLSI Systeme und Neuromikroelektronik. Oberseminar Informationstechnik
Elektrotechnik und Informationstechnik, Stiftungsprofessur hochparallele VLSI Systeme und Neuromikroelektronik Oberseminar Informationstechnik Reminder: Project Work Project Work ONE system ACCOUNT for
More informationJUNE, JULY 2013 Fundamentals of HDL (10EC45) PART A
JUNE, JULY 2013 Fundamentals of HDL (10EC45) Time: 3hrs Max Marks:100 Note: Answer FIVE full questions, selecting at least TWO questions from each part. PART A Q1.a. Describe VHDL scalar data types with
More informationVerilog Module 1 Introduction and Combinational Logic
Verilog Module 1 Introduction and Combinational Logic Jim Duckworth ECE Department, WPI 1 Module 1 Verilog background 1983: Gateway Design Automation released Verilog HDL Verilog and simulator 1985: Verilog
More informationChapter 6 Combinational-Circuit Building Blocks
Chapter 6 Combinational-Circuit Building Blocks Commonly used combinational building blocks in design of large circuits: Multiplexers Decoders Encoders Comparators Arithmetic circuits Multiplexers A multiplexer
More informationLecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26)
Lecture Topics Today: Integer Arithmetic (P&H 3.1-3.4) Next: continued 1 Announcements Consulting hours Introduction to Sim Milestone #1 (due 1/26) 2 1 Overview: Integer Operations Internal representation
More informationSRI SUKHMANI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DERA BASSI (MOHALI)
SRI SUKHMANI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DERA BASSI (MOHALI) VLSI LAB MANUAL ECE DEPARTMENT Introduction to VHDL It is a hardware description language that can be used to model a digital system
More informationECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7
More informationField Programmable Gate Array (FPGA)
Field Programmable Gate Array (FPGA) Lecturer: Krébesz, Tamas 1 FPGA in general Reprogrammable Si chip Invented in 1985 by Ross Freeman (Xilinx inc.) Combines the advantages of ASIC and uc-based systems
More informationField Programmable Gate Array
Field Programmable Gate Array System Arch 27 (Fire Tom Wada) What is FPGA? System Arch 27 (Fire Tom Wada) 2 FPGA Programmable (= reconfigurable) Digital System Component Basic components Combinational
More informationGetting Started with VHDL
Getting Started with VHDL VHDL code is composed of a number of entities Entities describe the interface of the component Entities can be primitive objects or complex objects Architectures are associated
More informationContents. Appendix D Verilog Summary Page 1 of 16
Appix D Verilog Summary Page 1 of 16 Contents Appix D Verilog Summary... 2 D.1 Basic Language Elements... 2 D.1.1 Keywords... 2 D.1.2 Comments... 2 D.1.3 Identifiers... 2 D.1.4 Numbers and Strings... 3
More informationSynthesis from VHDL. Krzysztof Kuchcinski Department of Computer Science Lund Institute of Technology Sweden
Synthesis from VHDL Krzysztof Kuchcinski Krzysztof.Kuchcinski@cs.lth.se Department of Computer Science Lund Institute of Technology Sweden March 23, 2006 Kris Kuchcinski (LTH) Synthesis from VHDL March
More informationLecture #2: Verilog HDL
Lecture #2: Verilog HDL Paul Hartke Phartke@stanford.edu Stanford EE183 April 8, 2002 EE183 Design Process Understand problem and generate block diagram of solution Code block diagram in verilog HDL Synthesize
More informationFPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language. Reference: [1]
FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language Reference: [] FIELD PROGRAMMABLE GATE ARRAY FPGA is a hardware logic device that is programmable Logic functions may be programmed
More informationVHDL for Synthesis. Course Description. Course Duration. Goals
VHDL for Synthesis Course Description This course provides all necessary theoretical and practical know how to write an efficient synthesizable HDL code through VHDL standard language. The course goes
More informationTopics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
More information5. VHDL - Introduction - 5. VHDL - Design flow - 5. VHDL - Entities and Architectures (1) - 5. VHDL - Entities and Architectures (2) -
Sistemas Digitais I LESI - 2º ano Lesson 5 - VHDL Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática - Introduction - VHDL was developed, in the mid-1980s, by DoD and IEEE. VHDL stands
More informationEECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis
EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis Jan 31, 2012 John Wawrzynek Spring 2012 EECS150 - Lec05-verilog_synth Page 1 Outline Quick review of essentials of state elements Finite State
More informationDesign Using Verilog
EGC220 Design Using Verilog Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Basic Verilog Lexical Convention Lexical convention are close to C++. Comment // to the of the line. /* to
More informationLab 3: Standard Combinational Components
Lab 3: Standard Combinational Components Purpose In this lab you will implement several combinational circuits on the DE1 development board to test and verify their operations. Introduction Using a high-level
More informationOutline CPE 626. Advanced VLSI Design. Lecture 3: VHDL Recapitulation. Intro to VHDL. Intro to VHDL. Entity-Architecture Pair
Outline CPE 626 Lecture 3: VHDL Recapitulation Aleksandar Milenkovic http://www.ece.uah.edu/~milenka http://www.ece.uah.edu/~milenka/cpe626-04f/ milenka@ece.uah.edu Assistant Professor Electrical and Computer
More informationVHDL kod yerleşimi. kütüphaneler. Dış görünüş (entity: varlık) İşleyişi, yapısı (architecture: mimari)
VHDL Basics VHDL kod yerleşimi library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; kütüphaneler entity and_gate_3_1 is port ( a:in std_logic; b:in
More informationCombinational Logic II
Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic
More informationECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level
More informationINTRODUCTION TO VHDL. Lecture 5 & 6 Dr. Tayab Din Memon Assistant Professor Department of Electronic Engineering, MUET
INTRODUCTION TO VHDL Lecture 5 & 6 Dr. Tayab Din Memon Assistant Professor Department of Electronic Engineering, MUET VHDL Resources Other Sources manufacturers web pages http://www.xilinx.com http://www.altera.com
More informationIE1204 Digital Design L7: Combinational circuits, Introduction to VHDL
IE24 Digital Design L7: Combinational circuits, Introduction to VHDL Elena Dubrova KTH / ICT / ES dubrova@kth.se This lecture BV 38-339, 6-65, 28-29,34-365 IE24 Digital Design, HT 24 2 The multiplexer
More informationArithmetic Circuits. Nurul Hazlina Adder 2. Multiplier 3. Arithmetic Logic Unit (ALU) 4. HDL for Arithmetic Circuit
Nurul Hazlina 1 1. Adder 2. Multiplier 3. Arithmetic Logic Unit (ALU) 4. HDL for Arithmetic Circuit Nurul Hazlina 2 Introduction 1. Digital circuits are frequently used for arithmetic operations 2. Fundamental
More informationECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level
More informationDesign Entry: Schematic Capture and VHDL ENG241: Digital Design Week #4
Design Entry: Schematic Capture and VHDL ENG241: Digital Design Week #4 1 References Kenneth Sort, VHDL For Engineers, Prentice Hall, 2009. Peter Ashenden, The designer s guide to VHDL, 2 nd edition, Morgan
More informationN-input EX-NOR gate. N-output inverter. N-input NOR gate
Hardware Description Language HDL Introduction HDL is a hardware description language used to design and document electronic systems. HDL allows designers to design at various levels of abstraction. It
More informationChapter 3: Dataflow Modeling
Chapter 3: Dataflow Modeling Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 3-1 Objectives After completing this chapter, you will be able to: Describe
More informationDigital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification
Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Ahmed Abu-Hajar, Ph.D. abuhajar@digitavid.net Digitavid, Inc San Jose, CA Session One Outline Introducing VHDL
More informationVerilog. Reminder: Lab #1 due tonight! Fall 2008 Lecture 3
Verilog Hardware Description Languages Verilog -- structural: modules, instances -- dataflow: continuous assignment -- sequential behavior: always blocks -- pitfalls -- other useful features Reminder:
More informationCCE 3202 Advanced Digital System Design
CCE 3202 Advanced Digital System Design Lab Exercise #2 This lab exercise will show you how to create, synthesize, and test a 3-bit ripple counter. A ripple counter is simply a circuit that outputs the
More informationChap 6 - Introduction to HDL (b)
Design with Verilog Chap 6 - Introduction to HDL (b) Credit to: MD Rizal Othman Faculty of Electrical & Electronics Engineering Universiti Malaysia Pahang Ext: 6036 Language Elements 1. Operators There
More informationWhy Should I Learn This Language? VLSI HDL. Verilog-2
Verilog Why Should I Learn This Language? VLSI HDL Verilog-2 Different Levels of Abstraction Algorithmic the function of the system RTL the data flow the control signals the storage element and clock Gate
More informationReview. LIBRARY list of library names; USE library.package.object; ENTITY entity_name IS generic declarations PORT ( signal_name(s): mode signal_type;
LIBRARY list of library names; USE library.package.object; Review ENTITY entity_name IS generic declarations PORT ( signal_name(s): mode signal_type; signal_name(s) : mode signal_type); END ENTITY entity_name;
More informationSynthesizable Verilog
Synthesizable Verilog Courtesy of Dr. Edwards@Columbia, and Dr. Franzon@NCSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Design Methodology Structure and Function (Behavior) of a Design HDL
More information