PINE TRAINING ACADEMY

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PINE TRAINING ACADEMY Course Module A d d r e s s D - 5 5 7, G o v i n d p u r a m, G h a z i a b a d, U. P., 2 0 1 0 1 3, I n d i a Digital Logic System Design using Gates/Verilog or VHDL and Implementation on FPGA. + 9 1 9 9 9 9 0 3 7 4 8 4 v a i b h a v. m i s h r a @ p i n e t r a i n i n g a c a d e m y. c o m 4 / 1 8 / 2 0 1 6

Digital Logic System Design using Gates/Verilog or VHDL and Implementation on FPGA Module Detailed Syllabus Duration Module 1 Week 1- Introduction. Month 1 Introduction to Pine Training Academy. Introduction of Semiconductor Industry. Introduction of VLSI- ASIC & FPGA FLOW. Study/Revision of Digital System Design. MINIMIZATION OF LOGIC GATES BOOLEAN ALGEBRA K-MAP LOGIC GATES NAND AND NOR AS A UNIVERSAL GATES COMBINATIONAL CIRCUITS HALF ADDER FULL ADDER HALF SUBRACTOR FULL SUBTRACTOR SERIAL ADDER PARALLEL ADDER LOOK AHEAD CARRY ADDER MUX, DEMUX DECODER, ENCODER, PRIORITY ENCODER COMPARATOR, CODE CONVERTOR NUMBER SYSTEM SEQUENTIAL CIRCUITS FLIP FLOPS REGISTORS COUNTERS MEMORIES INPUT OUTPUT BUFFERS TIMING FUNDAMENTAL CLOCK OSCILLATORS Project: Hardware Design using Digital Components on XILINX ISE Schematics. Schematics Entry Practical on ISE.

Module 2 FPGA/CPLD: - FPGA Device and FPGA Design Flow. Module 3 HDL- VHDL and Simulation Lab. XILINX FPGA and CPLD Introduction. Feature. Architecture. Packaging. CLB Overview. SLICE LOGIC Cell LUT Carry and Control Logic. IOB. RAM BLOCK. Multiplier. Memory. DCM. FPGA Nomenclature. Written test on Module 2. Project Assignment and Project Study: - Industrial Project uses VHDL Implementation on FPGA. Synthesisable VHDL:-XILINX ISE / VIVADO Introduction. VHDL Start-up. FPGA Design Flow. Design Entities. Data Types. Combinational Design Method. Sequential Design Method. FSM Synthesis. Memories. Sub-Programs. Parameterised Design. Hierarchical Designs. Test Benches. Industrial Project:-Discussion of project start from 1st week and daily 1 hr. discussion on project with student. Written Test on HDL-VHDL. Project Work Continue in every week. Week 2 Month 1 Week 2, 3 and 4 Month 1 Or

Synthesisable Verilog Introduction :- The scope and application of Verilog. Design and tool flow. Types of compilation, Simulation and Synthesis on FPGAs. Module:- Structure of basic Verilog program. Basic elements of Verilog:-Defining Modules: ports lists, port modes, parameters, Instance type. Language Elements:- Identifiers, Comments, Compiler Directives. Value Set: integers, real s, strings. Data Type: net, vectored, scalar and registers. Expressions:- Arithmetic operator. Logical operator. Relational operators. Miscellaneous operators. Modelling:- Gate Level Modelling. UDP. Data Flow Modelling. Behavioural Modelling:- Procedural Constructs, Timing Controls, Block Statement, Procedural assignment, conditional statement, loop, cases, procedural continuous assignment. Structural Modelling Example Designs:- Combinational Design. Sequential Design. FSM Synthesis :- Verilog coding styles for FSMs. State encoding, Unreachable states and input hazards. Memories:- Array types.

Module 4 FPGA Design Flow and Study of FPGA Development board. Module 5. Development Board- Xilinx. Modelling memories. Implementing ROMs & RAMs. Advanced Verilog:- System Task. Function. Test benches. verification Industrial Project:-Discussion of project start from 1st week and daily 1 hr. discussion on project with student. Written Test on HDL-VHDL. Project Work (Continue in every week). Synthesis. Pre- Synthesis Simulation. Post Synthesis Simulation. Synthesis Technique. Analysis of Report. PlanAhead- ISE. UCF. Implementation. Translation. o Post Translation Simulation. Mapping. o Post Mapping Simulation. Placement and Routing. o Post Placement and Routing Simulation. Implementation Technique and Analysis of Report at each stage. Programing. FPGA Programming. FLASH Programming. Project work Continue. Written test on Module 4. Study of Xilinx Spartan 6 SP605 /SP601 Development Board. Study of Interface. o LED. o Switch. o Button. o DIP. o FLASH. o UART. Completion of Project, Viva and Hanover of Certificate. Week 2 Month 1 Week 1,2,3,4- Month 2 Project based Internship

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