TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 8 GBIT (G 8 BIT) CMOS NAND E 2 PROM DESCRIPTION The TC58NVG3S0F is a single 3.3V 8 Gbit (9,076,473,856 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E 2 PROM) organized as (4096 + 232) bytes 64 pages 4096blocks. The device has two 4328-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 4328-byte increments. The Erase operation is implemented in a single block unit (256 Kbytes + 4.5 Kbytes: 4328 bytes 64 pages). The TC58NVG3S0F is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATURES Organization x8 Memory cell array 4328 256K 8 Register 4328 8 Page size 4328 bytes Block size (256K + 4.5K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read Mode control Serial input/output Command control Number of valid blocks Min 406 blocks Max 4096 blocks Power supply V CC = 2.7V to 3.6V Access time Cell array to register 30 μs max Serial Read Cycle 25 ns min (CL=00pF) Program/Erase time Auto Page Program Auto Block Erase Operating current Read (25 ns cycle) Program (avg.) Erase (avg.) Standby 300 μs/page typ. 3 ms/block typ. 30 ma max. 30 ma max 30 ma max 50 μa max Package TSOP I 48-P-220-0.50C (Weight: 0.53 g typ.) 4bit ECC for each 52Byte is required.
PIN ASSIGNMENT (TOP VIEW) TC58NVG3S0FTAI0 8 NC NC NC NC NC NC /BY RY RE NC NC V CC V SS NC NC ALE WP NC NC NC NC NC 48 2 47 3 46 4 45 5 44 6 43 7 42 8 4 9 40 0 39 38 2 37 3 36 4 35 5 34 6 33 7 32 8 3 9 30 20 29 2 28 22 27 23 26 24 25 8 NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC PSL NC V CC V SS NC NC NC I/O4 I/O3 I/O2 I/O NC NC NC NC PINNAMES I/O to I/O8 RE ALE PSL WP I/O port Chip enable Write enable Read enable Command latch enable latch enable Power on select Write protect Ready/Busy V CC V SS Power supply Ground 2
BLOCK DIAGRAM Status register V CC V SS I/O to I/O Control circuit register Column buffer Column decoder I/O8 Command register Data register Sense amp ALE RE WP Logic control Control circuit Row address buffer decoder Row address decoder Memory cell array PSL HV generator ABSOLUTE MAXIMUM RATINGS SYMBOL RATING VALUE UNIT V CC Power Supply Voltage 0.6 to 4.6 V V IN Input Voltage 0.6 to 4.6 V V I/O Input /Output Voltage 0.6 to V CC + 0.3 ( 4.6 V) V P D Power Dissipation 0.3 W T SOLDER Soldering Temperature (0 s) 260 C T STG Storage Temperature 55 to 50 C T OPR Operating Temperature -40 to 85 C CAPACITAN *(Ta = 25 C, f = MHz) SYMB0L PARAMETER CONDITION MIN MAX UNIT C IN Input V IN = 0 V 0 pf C OUT Output V OUT = 0 V 0 pf * This parameter is periodically sampled and is not tested for every device. 3
VALID BLOCKS SYMBOL PARAMETER MIN TYP. MAX UNIT N VB Number of Valid Blocks 406 4096 Blocks NOTE: The device occasionally contains unusable blocks. Refer to Application Note (3) toward the end of this document. The first block (Block 0) is guaranteed to be a valid block at the time of shipment. The specification for the minimum number of valid blocks is applicable over lifetime The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations. RECOMMENDED DC OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP. MAX UNIT V CC Power Supply Voltage 2.7 3.6 V V IH High Level input Voltage 2.7 V V CC 3.6 V Vcc x 0.8 V CC + 0.3 V V IL Low Level Input Voltage 2.7 V V CC 3.6 V 0.3* Vcc x 0.2 V * 2 V (pulse width lower than 20 ns) DC CHARACTERISTICS (Ta = -40 to 85, V CC = 2.7 to 3.6V) SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT I IL Input Leakage Current V IN = 0 V to V CC ±0 μa I LO Output Leakage Current V OUT = 0 V to V CC ±0 μa PSL = GND or NU 30 I CCO0 * Power On Reset Current PSL = V CC, FFh command input after Power On 30 ma I CCO Serial Read Current = V IL, I OUT = 0 ma, tcycle = 25 ns 30 ma I CCO2 Programming Current 30 ma I CCO3 Erasing Current 30 ma I CCS Standby Current = V CC 0.2 V, WP = 0 V/V CC, PSL = 0 V/V CC /NU 50 μa V OH High Level Output Voltage I OH = 0.4 ma 2.4 V V OL Low Level Output Voltage I OL = 2. ma 0.4 V I OL ( RY / BY ) Output current of pin RY / BY V OL = 0.4 V 8 ma * Refer to application note (2) for detail 4
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Ta = -40 to 85, V CC = 2.7 to 3.6V) TC58NVG3S0FTAI0 SYMBOL PARAMETER MIN MAX UNIT Setup Time 2 ns t CLH Hold Time 5 ns Setup Time 20 ns t CH Hold Time 5 ns t WP Write Pulse Width 2 ns t ALS ALE Setup Time 2 ns t ALH ALE Hold Time 5 ns t DS Data Setup Time 2 ns t DH Data Hold Time 5 ns t WC Write Cycle Time 25 ns t WH High Hold Time 0 ns t WW WP High to Low 00 ns t RR Ready to RE Falling Edge 20 ns t RW Ready to Falling Edge 20 ns t RP Read Pulse Width 2 ns t RC Read Cycle Time 25 ns t REA RE Access Time 20 ns ta Access Time 25 ns t CLR Low to RE Low 0 ns t AR ALE Low to RE Low 0 ns t RHOH RE High to Output Hold Time 25 ns t RLOH RE Low to Output Hold Time 5 ns t RHZ RE High to Output High Impedance 60 ns t CHZ High to Output High Impedance 20 ns D High to ALE or Don t Care 0 ns t REH RE High Hold Time 0 ns t IR Output-High-impedance-to- RE Falling Edge 0 ns t RHW RE High to Low 60 ns t WHC High to Low 30 ns t WHR High to RE Low 60 ns t R Memory Cell Array to Starting 30 μs t DCBSYR Data Cache Busy in Read Cache (following 3h and 3Fh) 30 μs t DCBSYR2 Data Cache Busy in Page Copy (following 3Ah) 35 μs t WB High to Busy 00 ns t RST Device Reset Time (Ready/Read/Program/Erase) 0/0/30/500 μs *: tcls and tals can not be shorter than twp *2: tcs should be longer than twp + 8ns. 5
AC TEST CONDITIONS PARAMETER CONDITION V CC : 2.7 to 3.6V Input level Input pulse rise and fall time 0V to Vcc 3 ns Input comparison level Vcc / 2 Output data comparison level Vcc / 2 Output load C L (00 pf) + TTL Note: Busy to ready time depends on the pull-up resistor tied to the RY / BY pin. (Refer to Application Note (9) toward the end of this document.) PROGRAMMING AND ERASING CHARACTERISTICS (Ta = -40 to 85, V CC = 2.7 to 3.6V) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES t PROG Average Programming Time 300 700 μs t DCBSYW Data Cache Busy Time in Write Cache (following h) 0.5 μs t DCBSYW2 Data Cache Busy Time in Write Cache (following 5h) 700 μs (2) N Number of Partial Program Cycles in the Same Page 4 () t BERASE Block Erasing Time 3 0 ms () Refer to Application Note (2) toward the end of this document. (2) t DCBSYW2 depends on the timing between internal programming time and data in time. Data Output When treh is long, output buffers are disabled by /RE=High, and the hold time of data output depend on trhoh (25ns MIN). On this condition, waveforms look like normal serial read mode. When treh is short, output buffers are not disabled by /RE=High, and the hold time of data output depend on trloh (5ns MIN). On this condition, output buffers are disabled by the rising edge of,ale,/ or falling edge of /, and waveforms look like Extended Data Output Mode. 6
TIMING DIAGRAMS TC58NVG3S0FTAI0 Latch Timing Diagram for Command//Data ALE RE Setup Time Hold Time t DS t DH I/O : V IH or V IL Command Input Cycle Timing Diagram t CLH t CH t WP t ALS t ALH ALE t DS t DH I/O : V IH or V IL 7
Input Cycle Timing Diagram t CLH t CH t WC t WC t CH t WP t WH t WP t WH t WP t WH t WP t WH t WP t ALS t ALH ALE t DS t DH t DS t DH t DS t DH t DS t DH t DS t DH I/O CA0 to 7 CA8 to 2 PA0 to 7 PA8 to 5 PA6 to 7 : V IH or V IL Data Input Cycle Timing Diagram t CLH t CH t CH t ALS t ALH ALE t WC t WP t WH t WP t WP t DS t DH t DS t DH t DS t DH I/O D IN 0 D IN D IN 4327* 8
Serial Read Cycle Timing Diagram t RC t RP t REH t RP t RP t CHZ RE t REA t RHZ t RHZ t RHZ t RHOH t REA t RHOH t REA t RHOH I/O t A ta t RR : V IH or V IL Status Read Cycle Timing Diagram t CLR t CLH t WP t CH t A t WHC t CHZ t WHR RE t DS t DH t IR trea t RHZ t RHOH I/O 70h* Status output *: 70h represents the hexadecimal number : V IH or V IL 9
Read Cycle Timing Diagram t CLR t CLH t CLH t CH t CH t WC t ALH t ALS t ALH t ALS ALE t R t RC RE t WB t RR t A I/O 00h CA0 to 7 CA8 to 2 PA0 to 7 PA8 to 5 PA6 to 7 30h t REA D OUT N D OUT N + Col. Add. N Data out from Col. Add. N Read Cycle Timing Diagram: When Interrupted by t CLR t CLH t CLH t CH t CH t WC D t ALH t ALS t ALH t ALS ALE t R t RC t CHZ RE t WB t RR t A t RHZ t RHOH I/O 00h CA0 to 7 CA8 to 2 PA0 to 7 PA8 to 5 PA6 to 7 30h t REA D OUT N D OUT N + Col. Add. N Col. Add. N 0
Read Cycle with Data Cache Timing Diagram (/2) t CLR t CLR t CLH t CH t CLH t CH t CLH t CH t CLH t CH t WC t ALH t ALS t ALH t ALS t RW ta ta ALE t R t DCBSYR t RC t DCBSYR RE t WB t WB t WB t RR t REA t RR t REA I/O 00h CA0 to 7 CA8 to 2 PA0 to 7 PA8 to 5 PA6 to 7 30h 3h D OUT 0 D OUT D OUT 3h D OUT 0 Column address N * Page address M Page address M Page address M + Col. Add. 0 Col. Add. 0 * The column address will be reset to 0 by the 3h command input. Continues to of next page
Read Cycle with Data Cache Timing Diagram (2/2) t CLR t CLR t CLR t CLH t CLH t CLH t CH t CH t CH ta ta ta ALE t DCBSYR t RC t DCBSYR t RC tdcbsyr t RC RE t WB t WB t WB t RR trea t RR trea t RR t REA I/O D OUT 3h D OUT 0 D OUT D OUT 3h D OUT 0 D OUT D OUT 3Fh D OUT 0 D OUT D OUT Page address M + Page address M + 2 Page address M + x Col. Add. 0 Col. Add. 0 Col. Add. 0 Make sure to terminate the operation with 3Fh command. Continues from of last page 2
Column Change in Read Cycle Timing Diagram (/2) t CLR t CLH t CLH t CH t CH t WC ta t ALH t ALS t ALH t ALS ALE t R t RC RE t WB t RR t REA I/O 00h CA0 to 7 CA8 to 2 PA0 to 7 PA8 to 5 Page address P PA6 to 7 30h D OUT A D OUT A + D OUT A + N Page address P Column address A Continues from of next page 3
Column Change in Read Cycle Timing Diagram (2/2) t CLR tclh t CLH t CH t CH t RHW t WC ta t ALH t ALS t ALH t ALS ALE t WHR t RC RE t REA t IR I/O D OUT A + N 05h CA0 to 7 CA8 to 2 E0h D OUT B D OUT B + D OUT B + N Column address B Page address P Column address B Continues from of last page 4
Data Output Timing Diagram t CLH t CH ALE t ALH t RC t CHZ t RP t REH t RP t RP t RHZ RE t A t REA t REA t DS t t REA RLOH t RLOH t DH I/O Dout Dout Command t RR t RHOH t RHOH 5
Auto-Program Operation Timing Diagram t CLH t CH t ALH t ALH t ALS t ALS t PROG t WB ALE RE t DS t DS tdh t DS tdh t DH I/O 80h CA0 to 7 CA8 to 2 PA0 to 7 PA8 to 5 PA6 to 7 D D IN N IN D IN M 0h 70h N+ Status output Column address N : Do not input data while data is being output. : V IH or V IL *) M: up to 4327 (byte input data for 8 device). 6
Auto-Program Operation with Data Cache Timing Diagram (/3) t CLH t CH t ALH t ALH t ALS t DCBSYW2 ALE t ALS t WB RE t DS t DS t DH t DS tdh t DH I/O 80h CA0 to 7 CA8 to 2 PA0 to 7 PA8 to 5 PA6 to 7 D IN N D IN N+ 5h 80h CA0 to 7 D IN 4327 : Do not input data while data is being output. : V IH or V IL CA0 to CA2 is 0 in this diagram. Continues to of next page 7
Auto-Program Operation with Data Cache Timing Diagram (2/3) t CLH t CH t ALH t ALH t ALS t ALS t DCBSYW2 t WB ALE RE t DS t DS t DH t DS tdh t DH I/O 80h CA0 to 7 CA8 to 2 PA0 to 7 PA8 to 5 PA6 to 7 D IN N D IN N+ 5h 80h CA0 to 7 D IN 4327 Repeat a max of 62 times (in order to program pages to 62 of a block). 2 Continued from of last page : Do not input data while data is being output. : V IH or V IL 8
Auto-Program Operation with Data Cache Timing Diagram (3/3) t CLH t CH t ALH t ALH t ALS t ALS t PROG (*) t WB ALE RE t DS t DS tdh t DH t DS t DH I/O 80h CA0 to 7 CA8 to 2 PA0 to 7 PA8 to 5 PA6 to 7 D IN N D IN N+ 0h 70h Status D IN 4327 : Do not input data while data is being output. : V IH or V IL 2 Continued from 2 of last page (*) t PROG : Since the last page programming by 0h command is initiated after the previous cache program, the t PROG during cache programming is given by the following equation. t PROG = t PROG of the last page + t PROG of the previous page A A = (command input cycle + address input cycle + data input cycle time of the last page) If A exceeds the t PROG of previous page, t PROG of the last page is t PROG max. (Note) Make sure to terminate the operation with 80h-0h- command sequence. If the operation is terminated by 80h-5h command sequence, monitor I/O 6 (Ready / Busy) by issuing Status Read command (70h) and make sure the previous page program operation is completed. If the page program operation is completed issue FFh reset before next operation. 9
Multi-Page Program Operation with Data Cache Timing Diagram (/4) t CLH t CH t ALH t ALH t ALS t ALS t DCBSYW t WB ALE RE t DS t DS t DH t DS tdh t DH I/O 80h CA0 to 7 CA8 to 2 PA0 to 7 PA8 to 5 Page M District-0 PA6 to 7 D IN N D IN N+ D IN 4327 h 8h CA0 to 7 : Do not input data while data is being output. : V IH or V IL Continues to of next page 20
Multi-Page Program Operation with Data Cache Timing Diagram (2/4) t CLH t CH t ALH t ALH t ALS t DCBSYW2 ALE t ALS t WB RE t DS t DS t DH t DS tdh t DH I/O 8h CA0 to 7 CA8 to 2 PA0 to 7 PA8 to 5 Page M District- PA6 to 7 D IN N D IN N+ D IN 4327 5h 80h CA0 to 7 Repeat a max of 63 times (in order to program pages 0 to 62 of a block). 2 Continued from of last page : Do not input data while data is being output. : V IH or V IL 2
Multi-Page Program Operation with Data Cache Timing Diagram (3/4) t CLH t CH t ALH t ALH tals t ALS t DCBSYW t WB ALE RE t DS t DS t DH t DS tdh t DH I/O 80h CA0 to 7 CA8 to 2 PA0 to 7 PA8 to 5 Page M+n District-0 PA6 to 7 D IN N D IN N+ D IN 4327 h 8h CA0 to 7 : Do not input data while data is being output. : V IH or V IL 2 3 Continues to 3 of next page 22
Multi-Page Program Operation with Data Cache Timing Diagram (4/4) t CLH t CH t ALH t ALH t ALS t ALS t PROG (*) t WB ALE RE t DS t DS tdh t DH t DS t DH I/O 8h CA0 to 7 CA8 to 2 PA0 to 7 PA8 to 5 Page M+n District- PA6 to 7 D IN N D IN N+ D IN 4327 0h 7h Status : Do not input data while data is being output. : V IH or V IL 3 Continued from 3 of last page (*) t PROG : Since the last page programming by 0h command is initiated after the previous cache program, the t PROG during cache programming is given by the following equation. t PROG = t PROG of the last page + t PROG of the previous page A A = (command input cycle + address input cycle + data input cycle time of the last page) If A exceeds the t PROG of previous page, t PROG of the last page is t PROG max. (Note) Make sure to terminate the operation with 80h-0h- command sequence. If the operation is terminated by 8h-5h command sequence, monitor I/O 6 (Ready / Busy) by issuing Status Read command (70h) and make sure the previous page program operation is completed. If the page program operation is completed issue FFh reset before next operation. 23
Auto Block Erase Timing Diagram t CLH t ALS t ALH t WB t BERASE ALE RE 60h PA0 PA8 PA6 I/O D0h 70h to 7 to 5 to 7 Status output Auto Block Erase Setup command Erase Start command Busy Status Read command : V IH or V IL : Do not input data while data is being output. 24
Multi Block Erase Timing Diagram t CLH t ALS t ALH t WB t BERASE ALE RE I/O to 60h PA0 to 7 PA8 to 5 PA6 to 7 D0h 7h Status output RY/BY Auto Block Erase Setup command Busy Status Read command Repeat 2 times (District-0,) : V IH or V IL : Do not input data while data is being output. 25
Copy Back Program with Random Data Input twc twb tprog twhr twb ALE tr RE I/Ox Col Add Col Add2 Row Add Row Add2 Row Add3 00h 35h 85h Col Add Col Add2 Row Add Row Add2 Row Add3 Data DataN 0h 70h I/O R/B Column Row Column Row Read Status command Busy Busy Copy Back Program Data Input Command I/O=0 Successful Program I/O= Error in Program 26
ID Read Operation Timing Diagram t CH t A t CH t ALH t ALH t ALS t AR ALE RE t DH t DS t REA t REA t REA t REA t REA I/O 90h 00h 98h D3h See Table 5 See Table 5 See Table 5 ID Read command 00 Maker code Device code : V IH or V IL 27
PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. Command Latch Enable: TC58NVG3S0FTAI0 The input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the signal while is High. Latch Enable: ALE The ALE signal is used to control loading address information into the internal address register. information is latched into the address register from the I/O port on the rising edge of while ALE is High. Chip Enable: The device goes into a low-power Standby mode when goes High during the device is in Ready state. The signal is ignored when device is in Busy state ( RY / BY = L), such as during a Program or Erase or Read operation, and will not enter Standby mode even if the input goes High. Write Enable: The signal is used to control the acquisition of data from the I/O port. Read Enable: RE The RE signal controls serial data output. Data is available t REA after the falling edge of RE. The internal column address counter is also incremented ( = + l) on this falling edge. I/O Port: I/O to 8 The I/O to 8 pins are used as a port for transferring address, command and input/output data to and from the device. Write Protect: WP The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. Ready/Busy: RY / BY The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state ( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be pulled-up to Vccq with an appropriate resister. Power on Select: PSL The PSL signal is used to select whether the device initialization should take place during the device power on or during the first Reset. Please refer to the application note (2) for details. 28
Schematic Cell Layout and Assignment The Program operation works on page units while the Erase operation works on block units. TC58NVG3S0FTAI0 I/O Data Cache Page Buffer 4096 4096 232 232 I/O8 A page consists of 4328 bytes in which 4096 bytes are used for main memory storage and 232 bytes are for redundancy or for other uses. page = 4328bytes block = 4328 bytes 64 pages = (256K + 4.5K) bytes Capacity = 4328 bytes 64pages 4096 blocks 26244 pages 4096 blocks 64 Pages= block An address is read in via the I/O port over five consecutive clock cycles, as shown in Table. 8I/O 4328 Table. ing I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O First cycle CA7 CA6 CA5 CA4 CA3 CA2 CA CA0 Second cycle L L L CA2 CA CA0 CA9 CA8 Third cycle PA7 PA6 PA5 PA4 PA3 PA2 PA PA0 CA0 to CA2: Column address PA0 to PA7: Page address PA6 to PA7: Block address PA0 to PA5: NAND address in block Fourth cycle PA5 PA4 PA3 PA2 PA PA0 PA9 PA8 Fifth cycle L L L L L L PA7 PA6 29
Operation Mode: Logic and Command Tables The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown in Table 3. input, command input and data input/output are controlled by the, ALE,,, RE, WP and PSL signals, as shown in Table 2. Table 2. Logic Table ALE RE WP * PSL *3 Command Input H L L H * 0V/V CC /NU Data Input L L L H H 0V/V CC /NU input L H L H * 0V/V CC /NU Serial Data Output L L L H * 0V/V CC /NU During Program (Busy) * * * * * H 0V/V CC /NU During Erase (Busy) * * * * * H 0V/V CC /NU During Read (Busy) * * H * * * 0V/V CC /NU * * L H (*2) H (*2) * 0V/V CC /NU Program, Erase Inhibit * * * * * L 0V/V CC /NU Standby * * H * * 0 V/V CC 0V/V CC /NU H: V IH, L: V IL, *: V IH or V IL *: Refer to Application Note (0) toward the end of this document regarding the WP signal when Program or Erase Inhibit *2: If is low during read busy, and RE must be held High to avoid unintended command/address input to the device or read to device. Reset or Status Read command can be input during Read Busy. *3: PSL must be tied to either 0V or V CC or left unconnected(nu). 30
Table 3. Command table (HEX) First Set Second Set Acceptable while Busy Serial Data Input 80 Read 00 30 Column Change in Serial Data Output 05 E0 Read with Data Cache 3 Read Start for Last Page in Read Cycle with Data Cache 3F Auto Page Program 80 0 Column Change in Serial Data Input 85 Auto Program with Data Cache 80 5 80 Multi Page Program 8 5 8 0 Read for Page Copy (2) with Data Out 00 3A Read for Copy-Back without Data Out 00 35 Copy-Back Program without Data Out 85 0 Auto Program with Data Cache during Page Copy (2) 8C 5 Auto Program for last page during Page Copy (2) 8C 0 Auto Block Erase 60 D0 Page Program with 2KB Data 80 80-0 Copy-Back Program with 2KB Data 85-85 - 0 ID Read 90 Status Read 70 Status Read2 F Status Read for Multi-Page Program or Multi Block Erase 7 Reset FF HEX data bit assignment (Example) Serial Data Input: 80h 0 0 0 0 0 0 0 8 7 6 5 4 3 2 I/O Table 4. Read mode operation states ALE RE I/O to I/O8 Power Output select L L L H L Data output Active Output Deselect L L L H H High impedance Active H: V IH, L: V IL 3
DEVI OPERATION Read Mode Read mode is set when the "00h" and 30h commands are issued to the Command register. Between the two commands, a start address for the Read mode needs to be issued. After initial power on sequence, 00h command is latched into the internal command register. Therefore read operation after power on sequence is excuted by the setting of only five address cycles and 30h command. Refer to the figures below for the sequence and the block diagram (Refer to the detailed timing chart.). ALE RE Column M Page N Busy t R I/O 00h 30h M M+ M+2 Data Cache Page Buffer Select page N M Start-address input I/O to 8: m = 4327 m Cell array Page N A data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising edge of in the 30h command input cycle (after the address information has been latched). The device will be in the Busy state during this transfer period. After the transfer period, the device returns to Ready state. Serial data can be output synchronously with the RE clock from the start address designated in the address input cycle. Random Column Change in Read Cycle ALE RE I/O 00h Busy t R Col. M 30h M M+ M+2 M+3 05h E0h M M + M +2 M +3 M +4 Select page N Col. M Page N Start-address input M M Col. M Page N Page N Start from Col. M Start from Col. M During the serial data output from the Data Cache, the column address can be changed by inputting a new column address using the 05h and E0h commands. The data is read out in serial starting at the new column address. Random Column Change operation can be done multiple times within the same page. 32
Read Operation with Read Cache TC58NVG3S0FTAI0 The device has a Read operation with Data Cache that enables the high speed read operation shown below. When the block address changes, this sequence has to be started from the beginning. ALE RE I/O 00h 30h t R t DCBSYR t DCBSYR t DCBSYR 3 5 2 4 6 3h 0 2 3 4327 3h 0 2 3 4327 3Fh 0 2 3 7 4327 Data Cache Page Buffer Col. M Page N 2 Column 0 Page N Page N Page N 3 Cell Array Page N Page N + 3 Page N + 2 5 30h 3h & RE clock 3h & RE clock 3Fh & RE clock If the 3h command is issued to the device, the data content of the next page is transferred to the Page Buffer during serial data out from the Data Cache, and therefore the tr (Data transfer from memory cell to data register) will be reduced. Normal read. Data is transferred from Page N to Data Cache through Page Buffer. During this time period, the device outputs Busy state for tr max. 2 After the Ready/Busy returns to Ready, 3h command is issued and data is transferred to Data Cache from Page Buffer again. This data transfer takes tdcbsyr max and the completion of this time period can be detected by Ready/Busy signal. 3 Data of Page N + is transferred to Page Buffer from cell while the data of Page N in Data cache can be read out by /RE clock simultaneously. 4 The 3h command makes data of Page N + transfer to Data Cache from Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for tdcbsyr max.. This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time. 5 Data of Page N + 2 is transferred to Page Buffer from cell while the data of Page N + in Data cache can be read out by /RE clock simultaneously 6 The 3Fh command makes the data of Page N + 2 transfer to the Data Cache from the Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for tdcbsyr max.. This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time. 7 Data of Page N + 2 in Data Cache can be read out, but since the 3Fh command does not transfer the data from the memory cell to Page Buffer, the device can accept new command input immediately after the completion of serial data out. 33 4 Page N + Page N + Page N + 5 6 Page N + 2 Page N + 2 7 Page N + 2
Multi Page Read Operation The device has a Multi Page Read operation and Multi Page Read with Data Cache operation.. () Multi Page Read without Data Cache The sequence of command and address input is shown below. Same page address (PA0 to PA5) within each district has to be selected. Command input 60 RY/BY (3 cycle) (3 cycle) input 30 A input 60 Page PA0 to PA7 (District 0) Page PA0 to PA7 (District ) tr A Command input (5 cycle) (2 cycle) A 00 input 05 input E0 Data output B RY/BY A Column + Page CA0 to CA2, PA0 to PA7 (District 0) Column CA0 to CA2 (District 0) (District 0) B Command input (5 cycle) B 00 input 05 input E0 Data output RY/BY B Column + Page CA0 to CA2, PA0 to PA7 (District ) Column CA0 to CA2 (District ) (District ) District 0 District Reading Selected page Selected page The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising edge of in the 30h command input cycle (after the 2 Districts address information has been latched). The device will be in the Busy state during this transfer period. After the transfer period, the device returns to Ready state. Serial data can be output synchronously with the RE clock from the start address designated in the address input cycle. 34
(2) Multi Page Read with Data Cache When the block address changes (increments) this sequenced has to be started from the beginning. The sequence of command and address input is shown below. Same page address (PA0 to PA5) within each district has to be selected. Command input 60 input 60 Page PA0 to PA7 (Page m0 ; District 0) RY/BY input 30 A Page PA0 to PA7 (Page n0 ; District ) tr A Command input A 3 00 input 05 input E0 Data output B RY/BY A tdcbsyr Column + Page CA0 to CA2, PA0 to PA7 (Page m0 ; District 0) Column CA0 to CA2 (District 0) (District 0) B Command input B 00 input 05 input E0 Data output C RY/BY B Column + Page CA0 to CA2, PA0 to PA7 (Page n0 ; District ) Column CA0 to CA2 (District ) (District ) C Command input Return to A Repeat a max of 63 times C 3F 00 input 05 input E0 Data output D RY/BY C tdcbsyr Column + Page CA0 to CA2, PA0 to PA7 (Page m63 ; District 0) Column CA0 to CA2 (District 0) (District 0) D Command input D 00 input 05 input E0 Data output RY/BY D Column + Page CA0 to CA2, PA0 to PA7 (Page n63 ; District ) Column CA0 to CA2 (District ) (District ) 35
(3) Notes (a) Internal addressing in relation with the Districts TC58NVG3S0FTAI0 To use Multi Page Read operation, the internal addressing should be considered in relation with the District. The device consists from 2 Districts. Each District consists from 2048 erase blocks. The allocation rule is follows. District 0: Block 0, Block 2, Block 4, Block 6,, Block 4094 District : Block, Block 3, Block 5, Block 7,, Block 4095 (b) input restriction for the Multi Page Read operation There are following restrictions in using Multi Page Read; (Restriction) Maximum one block should be selected from each District. Same page address (PA0 to PA5) within two districts has to be selected. For example; (60) [District 0, Page 0x00000] (60) [District, Page 0x00040] (30) (60) [District 0, Page 0x0000] (60) [District, Page 0x0004] (30) (Acceptance) There is no order limitation of the District for the address input. For example, following operation is accepted; (60) [District 0] (60) [District ] (30) (60) [District ] (60) [District 0] (30) It requires no mutual address relation between the selected blocks from each District. (c) WP signal Make sure WP is held to High level when Multi Page Read operation is performed 36
Auto Page Program Operation The device carries out an Automatic Page Program operation when it receives a "0h" Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.) ALE RE RY/BY I/O 80h Din Din Din Din 0h 70h Status Out Col. M Page P Data Data input Selected page Program Read& verification The data is transferred (programmed) from the Data Cache via the Page Buffer to the selected page on the rising edge of following input of the 0h command. After programming, the programmed data is transferred back to the Page Buffer to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. Random Column Change in Auto Page Program Operation The column address can be changed by the 85h command during the data input sequence of the Auto Page Program operation. Two address input cycles after the 85h command are recognized as a new column address for the data input. After the new data is input to the new column address, the 0h command initiates the actual data program into the selected page automatically. The Random Column Change operation can be repeated multiple times within the same page. 80h Din Din Din Din 85h Din Din Din Din 0h 70h Status Col. M Page N Col. M Busy Col. M Col. M Data input Selected page Program Reading & verification 37
Multi Page Program TC58NVG3S0FTAI0 The device has a Multi Page Program, which enables even higher speed program operation compared to Auto Page Program. The sequence of command, address and data input is shown bellow. (Refer to the detailed timing chart.) Although two planes are programmed simultaneously, pass/fail is not available for each page when the program operation completes. Status bit of I/O is set to when any of the pages fails. Limitation in addressing with Multi Page Program is shown below. Multi Page Program R/ B tdcbsyw tprog I/O0~7 80h & Data Input h CA0~CA2 : Valid PA0~PA5 : Valid PA6 : District0 PA7~PA7 : Valid Note 8h & Data Input 0h 70h CA0~CA2 : Valid PA0~PA5 : Valid PA6 : District PA7~PA7 : Valid 0 I/O Fail Pass NOTE: Any command between h and 8h is prohibited except 70h/Fh and FFh. Data Input 80h h 8h 0h Plane 0 (2048 Block) Plane (2048 Block) Block 0 Block Block 2 Block 3 Block 4092 Block 4093 Block 4094 Block 4095 38
Auto Page Program Operation with Data Cache TC58NVG3S0FTAI0 The device has an Auto Page Program with Data Cache operation enabling the high speed program operation shown below. When the block address changes this sequenced has to be started from the beginning. ALE RE t DCBSYW2 t DCBSYW2 t PROG (NOTE) I/O 80h Add Add Add Add Add Din Din Din 5h 70h 80h Add Add Add Add Add Din Din Din 5h 70h 80h Add Add Add Add Add Din Din Din 0h 70h Data Cache Page Buffer Cell Array Page N Page N Data for Page N 2 2 Status Output Data for Page N 3 Page N + Data for Page N + 3 3 4 4 Data for Page N + Status Output 5 5 Page N + P Data for Page N + P 5 6 Page N + Page N + P Page N + P Issuing the 5h command to the device after serial data input initiates the program operation with Data Cache Data for Page N is input to Data Cache. 2 Data is transferred to the Page Buffer by the 5h command. During the transfer the Ready/Busy outputs Busy State (t DCBSYW2 ). 3 Data is programmed to the selected page while the data for page N + is input to the Data Cache. 4 By the 5h command, the data in the Data Cache is transferred to the Page Buffer after the programming of page N is completed. The device output busy state from the 5h command until the Data Cache becomes empty. The duration of this period depends on timing between the internal programming of page N and serial data input for Page N + (t DCBSYW2 ). 5 Data for Page N + P is input to the Data Cache while the data of the Page N + P is being programmed. 6 The programming with Data Cache is terminated by the 0h command. When the device becomes Ready, it shows that the internal programming of the Page N + P is completed. NOTE: Since the last page programming by the 0h command is initiated after the previous cache program, the tprog during cache programming is given by the following; t PROG = t PROG for the last page + t PROG of the previous page ( command input cycle + address input cycle + data input cycle time of the previous page) 6 Status Output 39
Pass/fail status for each page programmed by the Auto Page Programming with Data Cache operation can be detected by the Status Read operation. I/O : Pass/fail of the current page program operation. I/O2 : Pass/fail of the previous page program operation. The Pass/Fail status on I/O and I/O2 are valid under the following conditions. Status on I/O: Page Buffer Ready/Busy is Ready State. The Page Buffer Ready/Busy is output on I/O6 by Status Read operation or RY / BY pin after the 0h command Status on I/O2: Data Cache Read/Busy is Ready State. The Data Cache Ready/Busy is output on I/O7 by Status Read operation or RY / BY pin after the 5h command. Example) I/O2 => I/O => Invalid Invalid Page Invalid Page Page 2 Page N 2 Invalid invalid invalid Page N Page N 80h 5h 70h Status Out 80h 5h 70h Status Out 70h Status Out 80h 5h 70h Status Out 80h 0h 70h Status Out 70h Status Out Page Page 2 Page N Page N RY/ BY pin Data Cache Busy Page Buffer Busy Page Page 2 Page N Page N If the Page Buffer Busy returns to Ready before the next 80h command input, and if Status Read is done during this Ready period, the Status Read provides pass/fail for Page 2 on I/O and pass/fail result for Page on I/O2 40
Multi Page Program with Data Cache TC58NVG3S0FTAI0 The device has a Multi Page Program with Data Cache operation, which enables even higher speed program operation compared to Auto Page Program with Data Cache as shown below. When the block address changes (increments) this sequenced has to be started from the beginning. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.) Data input command RY/BY Data input command for multi-page program 80 8 5 80 8 0 input (District 0) Dummy Program command Data input 0 to 4327 input (District ) Program with Data Cache command Data input 0 to 4327 Data input command input (District 0) Dummy Program command Data input 0 to 4327 Data input command for multi-page program input (District) Auto Page Program command Data input 0 to 4327 After 5h or 0h Program command is input to device, physical programing starts as follows. For details of Auto Program with Data Cache, refer to Auto Page Program with Data Cache. District 0 District Program Reading & verification Selected page The data is transferred (programmed) from the page buffer to the selected page on the rising edge of / following input of the 5h or 0h command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. 4
Starting the above operation from st page of the selected erase blocks, and then repeating the operation total 64 times with incrementing the page address in the blocks, and then input the last page data of the blocks, 0h command executes final programming. Make sure to terminate with 8h-0h- command sequence. In this full sequence, the command sequence is following. st 80 8 5 80 8 5 63th 80 8 5 64th 80 8 0 After the 5h or 0h command, the results of the above operation is shown through the 7h Status Read command. 0 or5 7 Status Read command I/O Fail Pass The 7h command Status description is as below. STATUS OUTPUT I/O Chip Status : Pass/Fail Pass: 0 Fail: I/O2 District 0 Chip Status : Pass/Fail Pass: 0 Fail: I/O3 District Chip Status : Pass/Fail Pass: 0 Fail: I/O4 District 0 Chip Status2 : Pass/Fail Pass: 0 Fail: I/O5 District Chip Status2 : Pass/Fail Pass: 0 Fail: I/O6 Ready/Busy Ready: Busy: 0 I/O7 Data Cache Ready/Busy Ready: Busy: 0 I/O describes Pass/Fail condition of district 0 and (OR data of I/O2 and I/O3). If one of the districts fails during multi page program operation, it shows Fail. I/O2 to 5 shows the Pass/Fail condition of each district. For details on Chip Status and Chip Status2, refer to section Status Read. I/O8 Write Protect Protect: 0 Not Protect: 42
Internal addressing in relation with the Districts TC58NVG3S0FTAI0 To use Multi Page Program operation, the internal addressing should be considered in relation with the District. The device consists from 2 Districts. Each District consists from 2048 erase blocks. The allocation rule is follows. District 0: Block 0, Block 2, Block 4, Block 6,, Block 4094 District : Block, Block 3, Block 5, Block 7,, Block 4095 input restriction for the Multi Page Program with Data Cache operation There are following restrictions in using Multi Page Program with Data Cache; (Restriction) Maximum one block should be selected from each District. Same page address (PA0 to PA5) within two districts has to be selected. For example; (80) [District 0, Page 0x00000] () (8) [District, Page 0x00040] (5 or 0) (80) [District 0, Page 0x0000] () (8) [District, Page 0x0004] (5 or 0) (Acceptance) There is no order limitation of the District for the address input. For example, following operation is accepted; (80) [District 0] () (8) [District ] (5 or 0) (80) [District ] () (8) [District 0] (5 or 0) It requires no mutual address relation between the selected blocks from each District. Operating restriction during the Multi Page Program with Data Cache operation (Restriction) The operation has to be terminated with 0h command. Once the operation is started, no commands other than the commands shown in the timing diagram is allowed to be input except for Status Read command and reset command. 43
Page Copy (2) By using Page Copy (2), data in a page can be copied to another page after the data has been read out. When the block address changes (increments) this sequenced has to be started from the beginning. RY/BY Command 2 3 input 00 input 30 Data output 8C input Data input 5 00 input 3A Data output Col = 0 start When changing data, Col = 0 start CA0 to CA2, PA0 to PA7 CA0 to CA2, PA0 to PA7 changed data is input. CA0 to CA2, PA0 to PA7 (Page N) (Page M) 4 (Page N+P) 5 t R t DCBSYW2 t DCBSYR2 A A Data Cache Page Buffer Data for Page N 2 Data for Page N 3 Data for Page M 4 5 Data for Page N + P Cell Array Page M Page N Page N + P Page Copy (2) operation is as following. Data for Page N is transferred to the Data Cache. 2 Data for Page N is read out. 3 Copy Page address M is input and if the data needs to be changed, changed data is input. 4 Data Cache for Page M is transferred to the Page Buffer. 5 After the Ready state, Data for Page N + P is output from the Data Cache while the data of Page M is being programmed. 44
A A Command 6 input 8C input Data input 5 00 input 3A Data output 00 input 3A Data output CA0 to CA2, PA0 to PA7 (Page M+R) When changing data, changed data is input. 7 CA0 to CA2, PA0 to PA7 (Page N+P2) Col = 0 start Col = 0 start CA0 to CA2, PA0 to PA7 8 (Page N+Pn) 9 t DCBSYW2 t DCBSYR2 t DCBSYR2 B B Data Cache Page Buffer 6 7 Data for Page M + R Data for Page M + R 8 9 Data for Page N + P2 Data for Page N + Pn Cell Array Page M Page N + P Page M + R Page N + P2 Page M + Rn Page N + Pn Page M + Rn 6 Copy Page address (M + R) is input and if the data needs to be changed, changed data is input. 7 After programming of page M is completed, Data Cache for Page M + R is transferred to the Page Buffer. 8 By the 5h command, the data in the Page Buffer is programmed to Page M + R. Data for Page N + P2 is transferred to the Data cache. 9 The data in the Page Buffer is programmed to Page M + Rn. Data for Page N + Pn is transferred to the Data Cache. 45
B B Command 0 input 8C input Data input 0 70 Status output CA0 to CA2, PA0 to PA7 (Page M+Rn) t PROG (*) Data Cache Page Buffer Page M + Rn Cell Array Data for Page M + Rn 0 Page N + Pn Data for Page M + Rn 0 Copy Page address (M + Rn) is input and if the data needs to be changed, changed data is input. By issuing the 0h command, the data in the Page Buffer is programmed to Page M + Rn. (*) Since the last page programming by the 0h command is initiated after the previous cache program, the t PROG here will be expected as the following, t PROG = t PROG of the last page + tprog of the previous page ( command input cycle + address input cycle + data output/input cycle time of the last page) NOTE) This operation needs to be executed within District-0 or District-. Data input is required only if previous data output needs to be altered. If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and change only the data that needs be changed. If the data does not have to be changed, data input cycles are not required. Make sure WP is held to High level when Page Copy (2) operation is performed. Also make sure the Page Copy operation is terminated with 8Ch-0h command sequence 46
Multi Page Copy (2) By using Multi Page Copy (2), data in two pages can be copied to another pages after the data has been read out. When the each block address changes (increments) this sequenced has to be started from the beginning. Same page address (PA0 to PA5) within two districts has to be selected. Command input 60 input 60 input 30 00 input 05 input E0 Data output A PA0 to PA7 (Page m0 ; District 0) PA0 to PA7 (Page n0 ; District ) CA0 to CA2, PA0 to PA7 (Page m0) CA0 to CA2 (Col = 0) RY/BY t R A RY/BY A A 00 input 05 input E0 Data output 8C input Data input B CA0 to CA2, PA0 to PA7 (Page n0) CA0 to CA2 (Col = 0) CA0 to CA2, PA0 to PA7 (Page M0 ; District 0) t DCBSYW B B 8C input Data input 5 60 input 60 input 3A C RY/BY B CA0 to CA2, PA0 to PA7 (Page N0 ; District ) t DCBSYW2 PA0 to PA7 (Page m ; District 0) PA0 to PA7 (Page n ; District ) t DCBSYR2 C C 00 input 05 input E0 Data output 00 input 05 input E0 Data output D RY/BY C CA0 to CA2, PA0 to PA7 (Page m) CA0 to CA2 (Col = 0) CA0 to CA2, PA0 to PA7 (Page n) CA0 to CA2 (Col = 0) D 47
D 8C input Data input 8C input Data input 5 E RY/BY D CA0 to CA2, PA0 to PA7 (Page M ; District 0) t DCBSYW CA0 to CA2, PA0 to PA7 (Page N ; District ) t DCBSYW2 E E 60 input 60 input 3A 00 input 05 input E0 Data output F PA0 to PA7 (Page m63 ; District 0) PA0 to PA7 (Page n63 ; District ) CA0 to CA2, PA0 to PA7 (Page m63) CA0 to CA2 (Col = 0) RY/BY E t DCBSYR2 F RY/BY F F 00 input 05 input E0 Data output 8C input Data input G CA0 to CA2, PA0 to PA7 (Page n63) CA0 to CA2 (Col = 0) CA0 to CA2, PA0 to PA7 (Page M63 ; District 0) t DCBSYW G RY/BY G G 8C input Data input 0 CA0 to CA2, PA0 to PA7 (Page N63 ; District ) tprog (*) (*) t PROG : Since the last page programming by 0h command is initiated after the previous cache program, the t PROG* during cache programming is given by the following equation. t PROG = t PROG of the last page + t PROG of the previous page-a A = (command input cycle + address input cycle + data output/input cycle time of the last page) If A exceeds the t PROG of previous page, t PROG of the last page is t PROG max. Note) This operation needs to be executed within each District. Data input is required only if previous data output needs to be altered. If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and change only the data that needs be changed. If the data does not have to be changed, data input cycles are not required. Make sure WP is held to High level when Multi Page Copy (2) operation is performed. Also make sure the Multi Page Copy operation is terminated with 8Ch-0h command sequence 48
Auto Block Erase TC58NVG3S0FTAI0 The Auto Block Erase operation starts on the rising edge of after the Erase Start command D0h which follows the Erase Setup command 60h. This two-cycle process for Erase operations acts as an extra layer of protection from accidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations. 60 D0 70 Block input: 3 cycles Erase Start command Status Read command Pass I/O Fail Busy Multi Block Erase The Multi Block Erase operation starts by selecting two block addresses before D0h command as in below diagram. The device automatically executes the Erase and Verify operations and the result can be monitored by checking the status by 7h status read command. For details on 7h status read command, refer to section Multi Page Program with Data Cache. 60 60 D0 7 Block input: 3 cycles District 0 Block input: 3 cycles District Erase Start command Status Read command Pass I/O Fail Busy Internal addressing in relation with the Districts To use Multi Block Erase operation, the internal addressing should be considered in relation with the District. The device consists from 2 Districts. Each District consists from 2048 erase blocks. The allocation rule is follows. District 0: Block 0, Block 2, Block 4, Block 6,, Block 4094 District : Block, Block 3, Block 5, Block 7,, Block 4095 input restriction for the Multi Block Erase There are following restrictions in using Multi Block Erase (Restriction) Maximum one block should be selected from each District. For example; (60) [District 0] (60) [District ] (D0) (Acceptance) There is no order limitation of the District for the address input. For example, following operation is accepted; (60) [District ] (60) [District 0] (D0) It requires no mutual address relation between the selected blocks from each District. Make sure to terminate the operation with D0h command. If the operation needs to be terminated before D0h command input, input the FFh reset command to terminate the operation. 49
READ FOR COPY-BACK WITH DATA OUTPUT TIMING GUIDE TC58NVG3S0FTAI0 Copy-Back operation is a sequence execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with 35h command and the address of source page moves the whole 4328byte data into the internal data buffer. Bit errors are checked by sequential reading the data. In the case where there is no bit error, the data don t need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command (85h) with destination page address. Acutual programming operation begins after Program Confirm command (0h) is issued. Once the program process starts, the Read Status Register command (70h) may be enterd to read the status register. The system contoller can detect the completion of a program cycle by monitoring the RY / BY output, or the Status Bit (I/O7) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit (I/O) may be checked. The command register remains in Read Status command mode until another valid command is written to the command register. During copy-back program, data modification is possible using randam data input command (85h) as shown below. Page Copy-Back Program Operation R/ B tr tprog I/Ox 00h 0 Add.(5Cycles) 35h Data Output 85h Add.(5Cycles) 0h 70h I/O Pass Col. Add.,2 & Page Add.,2,3 Source Col. Add.,2 & Page Add.,2,3 Destination Fail NOTE:. Copy-Back Program operation is allowed only within the same district. Page Copy-Back Program Operation with Random Data Input R/ B tr tprog I/Ox 00h Add.(5Cycles) Col. Add.,2 & Page Add.,2,3 Source 35h Data Output 85h Add.(5Cycles) Data 85h Add.(2Cycles) Data 0h 70h Col. Add.,2 & Page Add.,2,3 Destination Col. Add.,2 There is no limitation for the number of repetition 50
Two-Plane Copy-Back Program Operation TC58NVG3S0FTAI0 Multi Page Copy-Back Program is an extension of Copy-Back Program, for a single plane with 4328byte data registers. Since the device is equipped with two memory planes, activating the two sets of 4328 byte data registers enable a simultaneous programming of two pages. Same page address (PA0 to PA5) within two districts has to be selected. tr R/ B I/Ox 60h (3Cycle) 60h (3Cycle) 35h Row Add.,2,3 PA0~PA5 : Valid PA6 : Fixed Low PA7~PA7 : Valid Row Add.,2,3 PA0~PA5 : Valid PA6 : Fixed High PA7~PA7 : Valid R/ B I/Ox 00h (5Cycle) 05h (2Cycle) E0h Data Output Col. Add.,2 & Row Add.,2,3 CA0~CA2 : Valid PA0~PA5 : Valid PA6 : Fixed Low PA7~PA7 : Valid Col. Add.,2 CA0~CA2 : Valid 2 R/ B I/Ox 00h (5Cycle) 05h (2Cycle) E0h Data Output 2 Col. Add.,2 & Row Add.,2,3 CA0~CA2 : Valid PA0~PA5 : Valid PA6 : Fixed High PA7~PA7 : Valid Col. Add.,2 CA0~CA2 : Valid tdcbsyw tprog 3 R/ B I/Ox 3 85h Add.(5Cycles) Col. Add.,2 & Row Add.,2,3 Destination h Note *2 8h Add.(5Cycles) 0h 70h Col. Add.,2 & Row Add.,2,3 Destination CA0~CA2 PA0~PA5 PA6 PA7~PA7 : Valid : Valid : Fixed Low : Valid CA0~CA2 PA0~PA5 PA6 PA7~PA7 : Valid : Valid : Fixed High : Valid Plane0 Plane Source page Source page Target page () (3) Target page () (3) () : Multi Page Read for Copy Back (2) : Multi Page Random Data Out (3) : Multi Page Copy-Back Program (2) Data field Spare field (2) Data field Spare field NOTE:. Copy-Back Program operation is allowed only within the same district. 2. Any command between h and 8h is prohibited except 70h/Fh and FFh. 5