CAT25C02/04/08/16/32 2K/4K/8K/16K/32K SPI Serial CMOS E 2 PROM FEATURES

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Josephine Reed
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1 K/K/8K/6K/K SPI Serial CMOS E PROM FEATURES 0 MHz SPI Compatible.8 to 6.0 Volt Operation Hardware and Software Protection Zero Standby Current Low Power CMOS Technology SPI Modes (0,0 &,) Commercial, Industrial and Automotive Temperature Ranges DESCRIPTION,000,000 Program/Erase Cycles 00 Year Data Retention Self-Timed Write Cycle 8-Pin DIP/IC, 6-Pin IC, 8-Pin TSP and -Pin TSP Page Write Buffer Block Write Protection Protect /, / or all of E PROM Array The is a K/K/8K/6K/K-Bit input (), data in () and data out () are required SPI Serial CMOS E PROM internally organized as to access the device. The pin may be used to 56x8/5x8/0x8/08x8/096x8 bits. Catalyst s suspend any serial communication without resetting the advanced CMOS Technology substantially reduces device serial sequence. The is de- power requirements. The CAT5C0/0 features a signed with software and hardware write protection 6-byte page write buffer. The 5C08/6/ features a features including Block Lock protection. The device is -byte page write buffer.the device operates via the available in 8-pin DIP, 8-pin IC, 6-pin IC, 8-pin SPI bus serial interface and is enabled though a Chip TSP and -pin TSP packages. Select (). In addition to the Chip Select, the clock PIN CONFIGURATION TSP Package (U) IC Package (S6) IC Package (S) DIP Package (P) TSP Package (U) WP V SS VCC WP 7 0 V SS 8 9 VCC WP V SS V CC WP VSS BLOCK DIAGRAM VCC WP VSS SENSE AMPS SHIFT REGISTERS VCC PIN FUTIONS Pin Name Function WORD ADDRESS BUFFERS COLUMN DECODERS WP V CC V SS Serial Data Output Serial Clock Write Protect +.8V to +6.0V Power Supply Ground Chip Select WP I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC CONTROL LOGIC XDEC E PROM ARRAY Serial Data Input Suspends Serial Input DATA IN STORAGE No Connect STATUS REGISTER HIGH VOLTAGE/ TIMING CONTROL 5C8 F0 998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No /98

2 ABLUTE MAXIMUM RATINGS* Temperature Under Bias C to +5 C Storage Temperature C to +50 C Voltage on any Pin with Respect to Ground ()....0V to +V CC +.0V V CC with Respect to Ground....0V to +7.0V Package Power Dissipation Capability (Ta = 5 C)....0W Lead Soldering Temperature (0 secs) C Output Short Circuit Current () ma *COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTI Symbol Parameter Min. Max. Units Reference Test Method N () END Endurance,000,000 Cycles/Byte MIL-STD-88, Test Method 0 T () DR Data Retention 00 Years MIL-STD-88, Test Method 008 V () ZAP ESD Susceptibility 000 Volts MIL-STD-88, Test Method 05 I ()() LTH Latch-Up 00 ma JEDEC Standard 7 D.C. OPERATING CHARACTERISTI V CC = +.8V to +6.0V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions I CC Power Supply Current 5 ma V CC = 5MHz (Operating Write) =open; =Vss I CC Power Supply Current 0. ma V CC = 5.5V (Operating Read) F CLK = 5MHz I SB Power Supply Current 0 µa = V CC (Standby) V IN = V SS or V CC I LI Input Leakage Current µa I LO Output Leakage Current µa V OUT = 0V to V CC, = 0V V IL () Input Low Voltage - V CC x 0. V V IH () Input High Voltage V CC x 0.7 V CC V V OL Output Low Voltage 0. V V OH Output High Voltage V CC V.5V V CC <5.5V I OL =.0mA I OH = -.6mA V OL Output Low Voltage 0. V.8V V CC <.7V V OH Output High Voltage V CC-0. V I OL = 50µA I OH = -00µA Note: () The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to.0v for periods of less than 0 ns. Maximum DC voltage on output pins is V CC +0.5V, which may overshoot to V CC +.0V for periods of less than 0 ns. () Output shorted for no more than one second. No more than one output shorted at a time. () This parameter is tested initially and after a design or process change that affects the parameter. () Latch-up protection is provided for stresses up to 00 ma on address and data pins from V to V CC +V. Doc. No /98

3 Figure. Sychronous Data Timing V IH t V IL t S t H V IH V IL t SU t WH t H t WL V IH VIL VALID IN t V t HO tdis V OH HI-Z HI-Z V OL A.C. CHARACTERISTI Limits.8,.5.5V-5.5V Test SYMBOL PARAMETER Min. Max. Min. Max. UNITS Conditions t SU Data Setup Time 50 0 ns V IH =.V t H Data Hold Time 50 0 ns C L = 00pF t WH High Time 00 0 ns V OL = 0.8V t WL Low Time 00 0 ns V OH =.0v f Clock Frequency DC DC 0 MHz t LZ to Output Low Z ns t RI () Input Rise Time µs t FI () Input Fall Time µs t HD Setup Time 00 0 ns t CD Time 00 0 ns C L = 00pF t WC Write Cycle Time 0 5 ms t V Output Valid from Clock Low ns t HO Output Time 0 0 ns t DIS Output Disable Time ns t HZ to Output High Z ns t High Time ns t S Setup Time ns t H Time ns NOTE: () This parameter is tested initially and after a design or process change that affects the parameter. C L = 50pF Doc. No /98

4 FUTIONAL DESCRIPTION The supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the to interface directly with many of today s popular microcontrollers. The contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) After the device is selected with going low, the first byte will be received. The part is accessed via the pin, with data being clocked in on the rising edge of. The first byte contains one of the six op-codes that define the operation to be performed. PIN DESCRIPTION : Serial Input is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 5C0/0/08/6/. Input data is latched on the rising edge of the serial clock. : Serial Output is the serial data output pin. This pin is used to transfer data out of the 5C0/0/08/6/. During a read cycle, data is shifted out on the falling edge of the serial clock. INSTRUCTION SET : Serial Clock is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the 5C0/0/08/6/. Opcodes, byte addresses, or data present on the pin are latched on the rising edge of the. Data on the pin is updated on the falling edge of the. : Chip Select Instruction Opcode Operation is the Chip select pin. low enables the CAT5C0/ 0/08/6/ and high disables the CAT5C0/0/ 08/6/. high takes the output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway) The draws ZERO current in the Standby mode. A high to low transition on is required prior to any sequence being initiated. A low to high transition on after a valid write sequence is what initiates an internal write cycle. WP: Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low and the WPEN bit in the status register is set to, all write operations to the status register are inhibited. WP going low while is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0. WREN Enable Write Operations WRDI Disable Write Operations RDSR Read Status Register WRSR Write Status Register READ 0000 X0 () Read Data from Memory WRITE 0000 X00 () Write Data to Memory Power-Up Timing ()() Symbol Parameter Max. Units t PUR Power-up to Read Operation ms t PUW Power-up to Write Operation ms Note: () X=O for 5C0, 5C08, 5C6 and 5C. X=A8 for 5C0 () This parameter is tested initially and after a design or process change that affects the parameter. () t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated. Doc. No /98

5 : Hold is the pin. The pin is used to pause transmission to the while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, must be brought low while is low. The pin is in a high impedance state during the time the part is paused, and transitions on the pins will be ignored. To resume communication, is brought high, while is low. ( should be held high any time this function is not being used.) may be tied high directly to V CC or tied to V CC through a resistor. Figure 9 illustrates hold timing sequence. STATUS REGISTER The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT5C0/ 0/08/6/ is busy with a write operation. When set to a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read onlythe WEL (Write Enable) bit indicates the status of the write enable latch. When set to, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. The BPO and BP (Block Protect) bits indicate which STATUS REGISTER WPEN X X X BP BP0 WEL RDY BLOCK PROTECTION BITS Status Register Bits Array Address Protection BP BPO Protected 0 0 None No Protection 0 5C0: C0-FF Quarter Array Protection 5C0: 80-FF 5C08: 000-0FF 5C6: FF 5C: 0C00-0FFF 0 5C0: 80-FF Half Array Protection 5C0: 00-FF 5C08: 000-0FF 5C6: FF 5C: FFF 5C0: 00-FF Full Array Protection 5C0: 000-FF 5C08: FF 5C6: FF 5C: FFF WRITE PROTECT ENABLE OPERATION WPEN Protected Unprotected Status WP WEL Blocks Blocks Register 0 X 0 Protected Protected Protected 0 X Protected Writable Writable Low 0 Protected Protected Protected Low Protected Writable Protected X High 0 Protected Protected Protected X High Protected Writable Writable 5 Doc. No /98

6 blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed to protect quarter of the memory, half of the memory or the entire memory by setting these bits. Once protected the user may only read from the protected portion of the array. These bits are non-volatile. The WPEN (Write Protect Enable) is an enable bit for the WP pin. The WP pin and WPEN bit in the status register control the programmable hardware write protect feature. Hardware write protection is enabled when WP is low and WPEN bit is set to high. The user cannot write to the status register, (including the block protect bits and the WPEN bit) and the block protected sections in the memory array when the chip is hardware write protected. Only the sections of the memory array that are not block protected can be written. Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero. DEVICE OPERATION Write Enable and Disable The contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when V cc is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes(reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. READ Sequence The part is selected by pulling low. The 8-bit read instruction is transmitted to the, followed by the 6-bit address for 5C08/6/. (only 0-bit addresses are used for 5C08, -bit addresses are used for 5C6, and -bit addresses are used for 5C. The rest of the bits are don't care bits) and 8-bit address for 5C0/0 (for the 5C0, bit of the read data instruction contains address A8). After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the high. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the line. The status register may be read at any time even during a write cycle. Read sequece is illustrated in Figure. Reading status register is illustrated in Figure 5. Figure. WREN Instruction Timing SK HIGH-Z Figure. WRDI Instruction Timing SK HIGH-Z 5C8 F05 Doc. No /98 6

7 WRITE Sequence The powers up in a Write Disable state. Prior to any write instructions, the WREN instruction must be sent to. The device goes into Write enable state by pulling the low and then clocking the WREN instruction into. The must be brought high after the WREN instruction to enable writes to the device. If the write operation is initiated immediately after the WREN instruction without being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block protection level. Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the low, issuing a write instruction via the line, followed by the 6-bit address for 5C08/6/. (only 0-bit addresses are used for 5C08, -bit addresses are used for 5C6, and -bit addresses are used for 5C. The rest of the bits are don't care bits) and 8-bit address for 5C0/0 (for the 5C0, bit of the read data instruction contains address A8). Programming will start after the is brought high. The low to high transition of the pin must occur during the low time, immediately after clocking the least significant bit of the data. Figure 6 illustrates byte write sequence. Figure. Read Instruction Timing RESET SK BYTE ADDRESS* *Please check the instruction set table for address Figure 5. RDSR Timing HIGH IMPEDAE DATA OUT MSB 5C8 F09 7 Doc. No /98

8 During an internal write cycle, all commands will be ignored except the RDSR (Read Status Register) instruction. The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the Status Register is set at, write cycle is in progress. If Bit 0 is set at 0, the device is ready for the next instruction Page Write The features page write capability. After the initial byte, the host may continue to write up to 6 bytes of data to the CAT5C0/0 and bytes of data for 5C08/6/. After each byte of data received, lower order address bits are internally incremented by one; the high order bits of address will remain constant.the only restriction is that the X (X=6 for 5C0/0 and X= for 5C08/6/) bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will roll over to the first address of the page and overwrite any data that may have been written. The is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. To write to the status register, the WRSR instruction should be sent. Only Bit, Bit and Bit 7 of the status register can be written using the WRSR instruction. Figure 7 illustrates the sequence of writing to status register. Figure 6. Write Instruction Timing SK ADDRESS D7 D6 D5 D D D D D0 Figure 7. WRSR Timing INSTRUCTION DATA IN C8 F08 Doc. No /98 8

9 DEGN CONDERATIONS The powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write the goes into a write disable mode. must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and programming is continued. On power up, is in a high impedance. If an invalid op code is received, no data will be shifted into the CAT5C0/0/ 08/6/, and the serial output pin () will remain in a high impedance state until the falling edge of is detected again. Figure 8. Page Write Instruction Timing SK ADDRESS Data Byte Data Byte Data Byte Data Byte N Figure 9. Timing tcd tcd thd thd thz HIGH IMPEDAE tlz 9 Doc. No /98

10 ORDERING INFORMATION Prefix Device # Suffix CAT 5C56 K I -.8 TE Optional Company ID Product Number 5C56: 56K Temperature Range Blank = Commercial (0 C to +70 C) I = Industrial (-0 C to +85 C) A = Automotive (-0 to +05 C)* Tape & Reel TE: 000/Reel Package P = PDIP K= 8-Pin IC (EIAJ) U0 = 0-Pin TSP Operating Voltage Blank (V cc =.5 to 6.0V).8 (V cc =.8 to 6.0V) * -0 C to +5 C is available upon request Notes: () The device used in the above example is a 5C6-.8TE (IC, Industrial Temperature,.8 Volt to 6 Volt Operating Voltage, Tape & Reel) Doc. No /98 0

128K/256K-Bit SPI Serial CMOS EEPROM

128K/256K-Bit SPI Serial CMOS EEPROM CAT25C128/256 CAT25C128/256 FEATURES 5 MHz SPI Compatible 1.8 to 5.5 Volt Operation Hardware and Software Protection Low Power CMOS Technology SPI Modes (0,0 &1,1)