Exam 3 Review COMP375 Topics I/O controllers chapter 7 Disk performance section 6.3-6.4 RAID section 6.2 Pipelining section 12.4 Superscalar chapter 14 RISC chapter 13 Parallel Processors chapter 18 Security Topics not covered in class will not be on the exam. RAID Types RAID 0 - Striping RAID 1 - Mirroring RAID 2 - Hamming code error recovery RAID 3 - Bit-interleaved parity RAID 4 - Block-level parity RAID 5 - Block-level distributed parity RAID 6 - Dual redundancy RAID 0 (non-redundant) Sequential blocks of a file are written across multiple disks Improved transfer rate Decreased reliability 1
RAID 1 (mirrored) RAID 5 (distributed block parity) Improved Reliability Slightly slower writes. Possibly faster reads Twice the disk space required Striping improves read performance Parity improves reliability N+1 disks are required RAID 6 (dual redundancy) Like RAID 5 but with two parity blocks for each data block Slow writes N+2 disks required RAID Comparison RAID Disks Reads Writes Survives failures 0 N faster faster 0 1 2N slightly faster 5 N+1 faster 6 N+2 faster slightly slower slightly slower slightly slower 1 1 2 2
RAID Planning First calculate how many drives does it take to hold your data If high performance is the only goal, then use RAID 0, striping, with N disks No fault recovery RAID Planning If the data will fit on one physical hard drive, use RAID 1 with two drives If the data fits on N > 1 physical hard drives, use RAID 5 with N+1 hard drives If you need to survive the failure of two physical drives, use RAID 6 with N+2 drives Hazards A hazard is a situation that reduces the processors ability to pipeline instructions. Resource When different instructions want to use the same CPU resource. Data When the data used in an instruction is modified by the previous instruction. Control When a jump is taken or anything changes the sequential flow. Resource Hazards In the example below, both the operand fetch and instruction fetch stages are using the memory system. Hazards can cause pipeline stalls. 3
Data Hazards The data used by one instruction may be modified by a previous instruction. If the previous instruction has not completed and stored the results, the next instruction will use an incorrect value. Data Hazard Resolution Register Forwarding The data from a previous instruction ti can be used by the next instruction before or while it is being written back. Register locking When a register is in use by an instruction, that register is locked to following instructions until the first instruction completes. This avoids incorrect results but introduces delays. Control Hazards A jump or function call changes the sequential execution of instructions. The pipelined instruction fetch stage continually fetches sequential instructions. When a jump occurs, the previously fetched instructions should not be executed. Instructions in the pipe may have to be discarded before the write back stage. Using A Pipeline Pipeline is transparent to programmer Disadvantage: programmer who does not understand pipeline can produce inefficient code Reason: hardware automatically stalls pipeline if items are not available 4
Pipelining Guide Pipeline Optimization Assume 3 stage pipeline Compilers can rearrange the machine language instructions ti so that t adjacent instructions avoid data hazards Same compiler optimization improves superscalar execution Hardware improvements, such as delayed branches, multi-access memory and multiple ALUs Un-optimized code again: mov eax, dog add eax, pig mov cow, eax mov eax, cat add eax, 47 mov goat, eax mov eax, rat sub eax, pig mov bird, eax cmp bird, 100 jl again Optimized code again: mov eax, rat mov ebx, dog mov ecx, cat sub eax, pig add ebx, pig add ecx, 47 mov bird, eax cmp eax, 100 mov cow, ebx mov goat, ecx jl again RISC Design Principles Simple operations Simple instructions that can execute in one cycle Register-to-register operations Only load and store operations access memory Rest of the operations on a register-to-register basis Simple addressing modes A few addressing modes (1 or 2) RISC Design Principles Large number of registers Needed to support register-to-register operations Minimize the procedure call and return overhead Fixed-length instructions Facilitates efficient instruction execution Simple instruction format Fixed boundaries for various fields 5
RISC Design Principle Start an instruction every cycle Simple, fixed length instructions are easy to pipeline. Only two instruction have memory operands all other operands are in registers. Delayed branches RISC Traits Pipelined Simple uniform instructions Few instructions ti No microcode Few addressing modes Load/Store architecture Many identical general purpose registers Sliding register stack Delayed branches Fast How Visible is Parallelism? Superscalar Programmer never notices Multiple Threads Programmer must create multiple threads in the program Multiple processes Different programs Programmer never notices Parts of the same program Programmer must divide the work among different processes Flynn s Parallel Classification SISD Single Instruction Single Data standard uniprocessors SIMD Single Instruction Multiple Data vector and array processors MISD - Multiple Instruction Single Data t li systolic processors MIMD Multiple Instruction Multiple Data 6
Instruction at the Same Time Usually most program execute on line of a program at a time. If this is all the computer can do, then it is Single Instruction If the computer has two or more CPUs and can execute two or more programs at the same time, it is Multiple p Instruction Data per Instruction The assembly programs you wrote operate on one pair of fdata values at a time add eax, dog If more than one of these instructions is executed at the same time, it is Multiple Data If an instruction can operate on multiple data values at a time, it is Multiple Data SISD Flynn Examples Microcode computer model Old computers SIMD Vector processors Intel instructions that operate on multiple integer or floating point numbers MISD Flynn Examples Systolic processors (not generally available) MIMD SMP Popular dual core processors Computers with multiple CPU chips MIMD separate memory Supercomputers with many CPUs 7
Amdahl s Law P = fraction of the program that can be executed din parallel l N = number of processors Single = single CPU execution time multicpu time = (1-P)*single + P*(single/N) multicpu time = single * (1 P + P/N) Highly Probable Questions How long to read X bytes from a drive What RAID type to use Types of pipelining hazards Flynn s classification Amdahl s law Attributes of RISC processors Encryption types Use of digital signatures 8