Computer Architecture

Transcription

1 Computer Architecture Slide Sets WS 2013/2014 Prof. Dr. Uwe Brinkschulte M.Sc. Benjamin Betting Part 3 Fundamentals in Computer Architecture Computer Architecture Part 3 page 1 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

2 Basic definitions Computer Architecture defines the behavior and the attributes of a computer as seen by the programmer and user, no internal structural or organization details Computer Organization the internal organization (datapaths, memory structures, input/output structures, e.g.) of a computer Computer Architecture Part 3 page 2 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

3 Basic definitions Processor Architecture Microarchitecture Operation Principle part of Computer Architecture, defines the view of the processor visible to the programmer or compiler developer, interface between hard- and software, no implementation details defines the concrete implementation of a processor architecture, several implementations of the same processor architecture might exist (e.g. Intel IA32) defines the way the processor processes instructions and data Computer Architecture Part 3 page 3 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

4 Basic definitions Software Hardware Memory Computer Architecture Processor Architecture Processor Microarchitecture Input/ Output Computer Organization Operation Principle Computer Architecture Part 3 page 4 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

5 Basic definitions Instruction Set defines the set of instructions executable by the given processor architecture Instruction Set Architecture often used as a synonym to processor (ISA) architecture Instruction Format defines the way operands are accessed by instructions, instructions usually are divided into an opcode (tells what to do) and one ore more operands (tells on what to apply the opcode) Computer Architecture Part 3 page 5 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

6 Basic instruction formats 3-Address-Format 2-Address-Format 1-Address-Format 0-Address-Format Opcode, Dest, Src1, Src2 e.g. add C, B, A (C = A + B) Opcode, Dest/Src1, Src2 e.g. add B, A (B = A + B) Opcode, Src e.g. add B (Accu = Accu + B) a special accumulator register (Accu) is used Opcode e.g. push A (C = A + B) push B add pop C Stack based architecture Computer Architecture Part 3 page 6 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

7 More basic definitions Central Processing Unit (CPU, Processor) central unit of a computer, controls all computer operations consists of a control unit and a functional unit Instructions (command) operands (data) control unit functional unit (datapath) The operation principle of a processor can be a sequential or a parallel processing of instructions (the program) The processing in one or more functional units is controlled by the control unit. results Computer Architecture Part 3 page 7 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

8 More basic definitions Microprocessor a CPU on a single chip Microprocessor-System a technical system containing at least one microprocessor (may not be a computer, e.g. a phone) Microcomputer a computer build from one or more micropressors, contains also memory, input/output (IO) and a connection system (bus) Microcomputer-System a microcomputer with attached peripherals (e.g. keyboard, screen, mouse, printer, etc.) Computer Architecture Part 3 page 8 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

9 More basic definitions Microcomputer Microprocessor, CPU control unit functional unit (datapath) connection (bus) memory (program, data) input/output peripherals Microcomputer-System Computer Architecture Part 3 page 9 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

10 More basic definitions Memory consists of a linear set of memory cells memory cells mostly have uniform size (e.g. a byte) memory cells are identified by an address Input/Output interface to the peripherals like memory, IO units are identified by an address address data address data memory Computer Architecture Part 3 page 10 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting IO

11 More basic definitions Bus Data Bus Address Bus Control Bus connection system between CPU, memory and IO unit part of the bus where data (instructions or operands) is transfered (usually bidirectional) part of the bus where address information (memory or IO addresses) is transfered (usual unidirectional) part of the bus where control and status signals are transferred (partly unidirectional, partly bidirectional) Data Bus Bus Address Bus Control Bus CPU side Computer Architecture Part 3 page 11 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting memory/io side

12 The Von-Neumann-Architecture The operation principle of a Von-Neumann-architecture defines that instructions are processed sequentially. Instructions and data are stored in the same main memory The opcode is to be applied to the operands. Depending on the opcode, the operands are interpreted as data or memory addresses of data. In the latter case, the instruction is applied to the content of the addressed memory cell. Computer Architecture Part 3 page 12 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

13 The Von-Neumann-Architecture An operand may also be interpreted as a jump pointer to an instruction. Since instructions and data reside in the same memory, a memory address may contain a data value or an instruction. Interpretation of a memory cell s content depends on the opcode of the instruction only. CPU address data code main memory Computer Architecture Part 3 page 13 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

14 The Von-Neumann-Architecture program and data memory processor addresses of data or commands control signals control unit micro commands condition codes datapath Shared memory for program and data, sequential access. Von-Neumann- Architecture: simple structure (only one memory) program and data must access the memory one after another data and instructions Computer Architecture Part 3 page 14 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

15 Operation Principle of Von-Neumann-Architecture Demonstration data address instruction operand main memory instruction operand result address control unit decode result functional unit (datapath) execute control Von-Neumann bottleneck! Computer Architecture Part 3 page 15 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

16 The Von-Neumann-Architecture - necessary sequential steps to execute an instruction 1. Send instruction i address 2. Fetch instruction i 3. Decode instruction i 4. Send operand address i 5. Fetch operand i 6. Execute instruction i 7. Send result address & result i 8. Send instruction address i step cycle Computer Architecture Part 3 page 16 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

17 The Harvard-Architecture program memory data memory processor instructions control signals instruction address control unit (program counter, instruction register, control register) condition codes micro instructions function unit (data path) (data register, ALU, shifter, MUX, DEMUX) results operands control signals The processor is augmented by a program memory which stores the program to be executed. Data is stored in a second memory, the data memory. Harvard-Architecture: complex structure (two memories) program and data can access their memories at the same time Computer Architecture Part 3 page 17 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

18 Operation Principle of Havard-Architecture Demonstration data address instruction program memory instruction operand result address address control unit decode result functional unit (datapath) execute operand data memory control Computer Architecture Part 3 page 18 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

19 The Havard-Architecture - necessary sequential steps to execute an instruction 1. Send instruction i address 2. Fetch instruction i 3. Decode instruction i 4. Send operand address i 5. Fetch operand i send instruction i+1 address 6. Execute instruction i fetch instruction i+1 7. Send result address & result i decode instruction i+1 8. Send operand address i+1 9. Fetch operand i+1 send instruction i+2 address 10. Execute instruction i+1 fetch instruction i Send result address & result i+1 decode instruction i i overlap 4 step cycle i+1 Computer Architecture Part 3 page 19 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

20 The microprocessor receives the instructions in sequential order from the main memory. Therefore, the control unit contains a program counter (PC) to address the instructions It decodes each instruction and executes an operation on the content of the memory cell addressed by the instruction. In Von-Neumann-Architecture, the interpretation of the memory cell s content (data or instruction) depends only on the information in the instruction. Data and instructions are stored in the main memory in the same way and are indistinguishable from memory side therefore. The memory cells themselves don t keep track of the type of their content. The only structuring is the size of the smallest addressable unit given by the bit width (8, 16, 32, or 64). Computer Architecture Part 3 page 20 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

21 The computer executes three phases which may overlap: In the instruction retrieval phase the content of a memory cell which is addressed by the program counter is fetched. In the decode phase the content of the retrieved memory cell is interpreted as an instruction. In the execution phase the contents of one or two memory cells are fetched and processed depending on the command given by the opcode. It is thereby assumed that the memory cells contain data which are conform to the given preconditions. Computer Architecture Part 3 page 21 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

22 Sequential execution of a program program control unit instruction instr. 1 instr. 2 instr. 3 instr. 4 Interpretation of the instruction control commands Computer Architecture Part 3 page 22 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

23 Computer: CPU + Memory Model: Bus complexity: b Bits (word length) bus lines = #b + ld(w) + #control Timing: CPU address control W Words memory clock address address valid data read/write control data bus data valid memory access Computer Architecture Part 3 page 23 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

24 CPU as FSMD model (Finite State Machine with Datapath) control flow data flow instruction (program) data in state register data register next state output function data path control functional units control unit data path control commands data out Computer Architecture Part 3 page 24 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

25 Data path (bus oriented) e.g. 2 functional units operand registers Register 1 Register 2 Register 3 control lines switches (tri state) FU1 FU2 bus lines functional units Computer Architecture Part 3 page 25 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

26 Instruction cycle based on FSMD model Fetch: IR <= databus; PC <= PC + 1; nextstate <= decode;... Execute_sub1... Execute_add1: accu<=accu + d0; -- prepare fetch nextstate <= fetch; addressbus <= PC; Decode: case IR is when add: nextstate <= Execute_add1; when sub: nextstate <= Execute_sub1; when load: nextstate<= Execute_load1; when store: nextstate <= Execute_store1: end case; Computer Architecture Part 3 page 26 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

27 To execute an instruction, it is loaded into the instruction register IR and decoded. The decoding is done by the FSM control unit (CU). Decoding the instruction yields the control signals for the arithmetic logic units (ALU) in the datapath. It furthermore selects up to three register two for reading and one for writing (three-ported register file). It also provides the write enable signals for the write operations The ALU combines two operands, which are taken from the register file or from the instruction itself. Computer Architecture Part 3 page 27 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

28 In case of a LOAD instruction, the ALU calculates the effective address. Then, the contents of the addressed memory cell is loaded into the register file. On a STORE-Instruction the calculation of the effective address is also necessary. The operand to store must be made available at the same time. Furthermore, the ALU generates flags (CC: condition codes), which can be evaluated by the control unit. The program counter (PC) holds the address of the instruction to be executed next. It is normally incremented automatically (+). Computer Architecture Part 3 page 28 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

29 Instruction cycle of an existing sequential processor in pseudocode 1: forever { 2: npc = pc + 1 3: instr = prog [pc] 4: opcode 5: a = data [source addr1] 6: b = data [source addr2] 7: d = dest addr +1 8: case (opcode) { PC instruc -tion memory data memory ALU 9: ADD: data [d] = a + b 10: SUB: data [d] = a - b 11: : 12: BEQ: if (a == b) npc = d instruction decoder 13: : 14: } 15: pc = npc 16: } Computer Architecture Part 3 page 29 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

30 Instruction cycle of an existing sequential processor Executing a sample instruction: Add content of data memory at address 10 to content of data memory at address F0, store the result at address 10 (2-address format) Instruction in fictive assembler mnemonics: ADD (F0),(10) Instruction in fictive machine code: 7A F0 10 Instruction address in instruction memory: 50 Content of data memory at address 10: 05 Content of data memory at address F0: 02 Computer Architecture Part 3 page 30 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

31 Instruction cycle of an existing sequential processor Fetching the Instruction +1 PC 50 instruc -tion memory data memory ALU instruction decoder Computer Architecture Part 3 page 31 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

32 Instruction cycle of an existing sequential processor Decoding the Instruction +1 PC 50 instruc -tion memory 7A F0 10 data memory ALU instruction decoder Computer Architecture Part 3 page 32 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

33 Instruction cycle of an existing sequential processor Fetching the Operands +1 PC 50 instruc -tion memory 7A F0 10 F0 10 data memory ALU instruction decoder Computer Architecture Part 3 page 33 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

34 Instruction cycle of an existing sequential processor Executing the Instruction +1 PC 50 instruc -tion memory 7A F0 10 F0 10 data memory instruction decoder ALU 7A Computer Architecture Part 3 page 34 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

35 Instruction cycle of an existing sequential processor Storing the Result +1 PC 50 instruc -tion memory 7A F0 10 F0 10 data memory instruction decoder ALU 07 7A Computer Architecture Part 3 page 35 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

36 Instruction cycle of an existing sequential processor Incrementing the PC PC 50 instruc -tion memory data memory ALU instruction decoder Computer Architecture Part 3 page 36 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

37 Multiplexer based 3 address Load-Store architecture for a CPU Computer Architecture Part 3 page 37 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

38 The hardware cost of the Von-Neumann-principle is minimal. It had its value in times when the hardware components were the biggest cost factor of a computer and optimal memory utilization was the most important design goal. However, in the last three decades the cost situation has changed fundamentally due to the development of semiconductor technology. As shown, particularly the connection between main memory and processor proves to be a bottleneck, as all data and instructions have to be transported by it. Computer Architecture Part 3 page 38 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

39 Today, the processor s instruction execution is significantly faster than the memory access, which even worsens the situation. Processor techniques like instruction pipelining, superscalar principle, multithreading and multicores increased the data requirements considerably. Therefore, the pure Von-Neumann-Architecture principle is dropped in modern microprocessors. Cache-based Harvard-Architectures in combination with time and spatial parallelism can be found Computer Architecture Part 3 page 39 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

40 Classifications As seen, an instruction cycle consists of the part cycles: 1. instruction fetch 2. decode 3. instruction execute. In each instruction cycle at most one instruction is fetched from the main memory and then executed. This results in a sequential control flow. This computer class is called SISD: Single Instruction Single Data Computer Architecture Part 3 page 40 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

41 Flynn Classification SISD Single Instruction Single Data Von-Neumann SIMD Single Instruction Multiple Data Array- or Vectorprocessors, Multimedia Extensions MISD Multiple Instruction Single Data Fault-Tolerance (controversial) MIMD Multiple Instruction Multiple Data GRID, Cloud, Multicore, Supercomputers Computer Architecture Part 3 page 41 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

42 Classification by Control Unit There are basically two possible structures for the control unit: direct (hardwired) control micro programmed control The hardwired solution is mainly used in RISC designs whereas microprogramming is more common among CISC. The hardwired solution uses a FSM consisting of a hardwired combinatorial circuit to decode the instructions. This requires simple and regular instructions such as it is given by a RISC-ISA. Complex instructions, which are common in CISC, are interpreted using a micro programmed control. Computer Architecture Part 3 page 42 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

43 Hardwired control data hardwired control opcode; addr. etc. instruction register (IR) ALU complex combinatorial network state register control signals Computer Architecture Part 3 page 43 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

44 Processor (CPU) with hardwired control unit program complex comb. network state register control status Functionalunit multiplexer data register Computer Architecture Part 3 page 44 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

45 Implementation of a microprogrammed FSM next state vector control vector word lines x t Decoder bit lines z t+1 y t+1 z t register clock y t Computer Architecture Part 3 page 45 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

46 Adding the datapath to the microprogrammed FSM Instruction (program) decoder microprogram memory control path C next address state register C ALU control register operands ALU result data path Computer Architecture Part 3 page 46 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

47 Adding a sequencer to allow more comfortable microprogram operations Instruction (program) decoder microprogram memory control path Sequencer, µp counter C sequencer control operands C ALU control register ALU result data path Computer Architecture Part 3 page 47 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

48 Microprogrammed control (micro) status information from ALU (FLAG) instruction data bus µbz µps sequencer opcode addr. etc. mapping ROM D start address micro instruction counter instruction register microprogram micro program memory µir address part micro instruction register control part Computer Architecture Part 3 page 48 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting control signals

49 Processor (CPU) with micro programmed control unit program Sequencer Micro program state register control status Functionalunit multiplexer data register Computer Architecture Part 3 page 49 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

50 The most important parts of micro programmed instruction decoding are: micro program memory (µpm) mapping -ROM micro instruction counter µbz micro instruction register µir sequencer IR is the instruction register that holds the current instruction to be executed. A decoder or mapping -ROM(D) maps opcodes to micro program address. The control unit interprets each instruction using a microprogram subroutine, which is stored in the micro program memory. Computer Architecture Part 3 page 50 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

51 A microprogram consists of a series of discrete microprogram instructions (micro instructions). When an instruction is executed, the sequence of micro instructions, whose start address is determined from the opcode, is processed. The start address is loaded into the µbz. The addressed micro instruction is loaded into the micro instruction register. The micro program sequencer determines the address of the next micro instruction according to the control and address codes of the current one as well as the status flags of the ALU. This micro instruction is loaded into the micro instruction register. Selecting the next micro instruction and controlling the data path is done in parallel. Computer Architecture Part 3 page 51 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

52 Horizontal microprogramming is characterized by a direct mapping of the bits of the micro instruction onto the control signals (micro order). microprogram memory register... sequencer control ALU control bus control fully parallel Computer Architecture Part 3 page 52 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

53 Quasi-horizontal microprogramming differs therein that each micro instruction is grouped in bit fields, which have to be decoded. microprogram memory register field select decoder... partly parallel sequencer control ALU control bus control These fields may hold the address of the next micro instruction, the micro order for the ALU, numbers of registers or control signals for multiplexers. The associated decoders are usually part of the data path. The width of a microprogram word is shrinked while parallelism is reduced Computer Architecture Part 3 page 53 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

54 If the micro instructions are being decoded using firmware, this is called nanoprogramming. microprogram memory register field select nanoprogram memory partly sequential register... sequencer control ALU control bus control Computer Architecture Part 3 page 54 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

55 SISD computers are usually classified based on: The number of separate paths for instructions and operands (Von- Neumann and Harvard architecture respectively) The instruction set architecture (CISC/RISC) The location, where operands are placed for processing: - memory-memory machine: The operands are loaded directly from the main memory. Fast registers as buffers for operands are abandoned. - virtual-register machine: A part of the main memory is used like a register file. - register-register or load/store machine: The operands have to be placed in registers before processing. This kind of architecture is going to be described in detail in the following. Computer Architecture Part 3 page 55 of 55 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting