OSIAC 5362 Read OSIAC 5362 posted on the course website
The Basic Structure of Control Unit m CLK Run/Inhibit Control Step Counter m Preset (to any new state) Reset IR Decoder/Encoder (combinational logic) Status Flag Condition Codes Control Signals mostly data transfers between registers
OSIAC 5362 In the following lectures, we will cover a new processor OSIAC 5362 developed by The Ohio State University We will develop the control unit for the OSIAC 5362 Write the microinstructions to implement the instruction set with associated addressing modes We will compare the instructions and addressing modes with the example computer because many are similar
Register Structure of OSIAC 5362 There are four registers R0 15 0 AC: Accumulator R1 X: Index register R2 SP: System stack pointer R3 PC: Program counter Also 4 condition code bits C V Z N Carry out, Overflow, Zero, Negative
Organized as 16-bit words Not byte addressable No long words One or more words long Operands and Addresses Instruction Types - Opcode word + others needed by addressing mode Four types Double operand Single operand Branch instruction Special instruction
Addressing Modes Seven basic addressing modes similar to the example machines Mode Name Assembler Syntax Operand* 0 Register Rk [Rk] 1 Register Indirect (Rk) [[Rk]] 2 Autoincrement (Rk)+ [[Rk]] then [Rk] + 1 Rk 3 Autodecrement -(Rk) [Rk] 1 Rk then [[Rk]] 4 Index n(rk) [n+[rk]] 5 Absolute n [n] 6 Immediate #n n * Operand is for arithmetic instructions. JUMP type instruction use is for effective address (EA).
Instructions Double operand instructions - 4 bit opcode - Instruction defines src and dst (2 operands) - There are addressing fields for each operand: 4 bits (mode) + 2 bits (register number) OP2 SAD DAD S D 15 12 11 8 7 4 3 2 1 0 OP2: op code SAD: source addressing mode DAD: destination addressing mode S: source register number D: destination register number ADD (op code = 1), SUB (=2), MOVE (=3), EXG (=4), OR (=5), AND (=6) Condition codes set accordingly
Use of Condition Code C for Borrow in Subtract Operations Example No borrow 1 1 0 1-3 1 1 0 1-3 - 1 0 0 1 -(-7) 0 1 1 1 7 0 0 1 0 0 4 1 0 1 0 0 4 Computer does (2 s complement addition) Carry out is not set in subtraction C = 0 Needs borrow 0 0 1 1 3 0 0 1 1 3-0 1 1 1-7 1 0 0 1 +(-7) 1 1 0 0 12 0 1 1 0 0 Carry out is set in subtraction C = 1
Single operand instructions Instructions (continued) - 4 bit opcode in bits 11-8. - Instruction defines dst only (1 operand) - There is one addressing field for the operand: 4 bits (mode) + 2 bits (register number) OP1: op code 0000 OP1 DAD XX D 15 12 11 8 7 4 3 2 1 0 DAD: destination addressing mode D: destination register number CLR (op code = 1), INC (=2), DEC (=3), NEG (=4), COM (=5), JMP (=6), JSR (=7), TST (=8) Condition codes set There are 8 instructions accordingly - NEG gets 2 s complement - JMP and JSR both EA(dst) PC, JSR also stores the returning address in STACK
Instructions (continued) Branch Instructions e.g. BEQ (2 words) Uses relative address (branch relative to where you are) Offset = 2 nd word First Word A branch occurs if the following expression is true Second Word IR5 [IR3 (IR4 C) + IR2 (IR4 V) + IR1 (IR4 Z) + IR0 (IR4 N)] PCUPD = PCoriginal + 2, [PCUPD] + Offset PC Special Instructions 0000 0000 10 I S/C CVZN Offset 15 12 11 8 7 6 5 4 3 2 1 0 Return from subroutine RTS, opcode = $0080 [[SP]] PC, [SP]+1 SP Set/Clear Condition Codes, opcode = 0000 0000 001 S/C CVZN HALT halt, opcode = $0000 15 12 11 8 7 4 3 2 1 0
Condition Codes Make sense of the condition codes can an operation cause a condition change? AND, OR, MOVE cannot get a carry or overflow ADD, SUB all CC s can change INC, DEC like ADD and SUB #1, all can change TST cannot cause carry or overflow, N, Z, possible CLR only Z=1; N=0, V=0, C=0 JMP, JSR not moving/operating on data, none of CC s is affected
Condition Branch Bits 3 2 1 0 marked C, V, Z, N set to 1 if that is the condition to test (most often just one at a time) Bit 4 S/C 1 test if condition is set 0 test if condition is clear Bit 5 Invert inverts the sense of everything tested to decide whether or not to branch generally 0
Opcodes for Branch Instructions IR5 IR4 IR3 IR2 IR1 IR0 Opcode (I) (S/C) (C) (V) (Z) (N) BEQ (equal) 0 1 0 0 1 0 $0092 IR1 (IR4 Z)=Z BNE (not equal) 0 0 0 0 1 0 $0082 = Z BPL (plus) 0 0 0 0 0 1 $0081 IR0 (IR4 N) =N BMI (minus) 0 1 0 0 0 1 $0091 = N BLS(low/same) 0 1 1 0 1 0 $009A IR3 (IR4 C) +IR1 (IR4 Z) = C+Z BHI (high) 1 1 1 0 1 0 $00BA = C+Z
Addressing Modes Allowed Each instruction is allowed different addressing modes ADD: s source from anywhere d immediate would not make sense AND: something you do to data, not to address Bcc: relative addressing which is just n(pc) JMP: operand is EA (where jump to)