Grundlagen Microcontroller Processor Core. Günther Gridling Bettina Weiss

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1 Grundlagen Microcontroller Processor Core Günther Gridling Bettina Weiss 1

2 Processor Core Architecture Instruction Set Lecture Overview 2

3 Processor Core Architecture Computes things > ALU (Arithmetic Logic Unit) arithmetic and logic operations shifting and rotation ADD SUB AND OR NOT... 2 data inputs, 1 data output 3

4 Architecture Interesting information about ALU result: Status Register (Condition Code Register) zero (Z) negative (N) overflow (V) carry (C) 4

5 Architecture Status Register Flags: Z, N, V, C whenever the result of an operation is zero, the Z flag is set, otherwise it is cleared if the result of an operation is negative (msb = 1), the N flag is set, otherwise it is cleared the V flag alerts that in a 2's complement operation, the sign bit has changed irregularly The carry bit is used for multi word operations 5

6 Architecture Where do operands come from? > Register File many general purpose registers some dedicated registers (accumulator) 6

7 Architecture Where do operands come from? > Data Memory the data memory is not part of the CPU! memory access is slower than register access 7

8 Architecture Who controls ALU? > Control Unit interprets instructions controls datapath 8

9 Architecture Which instruction should be executed? > Program Counter (PC) contains address of next instruction instruction is loaded into instruction register (IR), PC is incremented 9

10 Architecture What is the next instruction? mostly sequential (PC = PC + 1) sometimes a jump (PC = address, PC = PC + offset) sometimes a subroutine call > want to jump back after subroutine is finished have to store the return address 10

11 Architecture Where is return address stored? > Stack Stack: consecutive area in data memory used by CPU: store return addresses, sometimes registers User: store data, save register contents Stack Pointer (SP): points to first free (or last used) location in stack 11

12 Stack Initialization Architecture stack grows down, from higher address to lower address initial SP value is often the end of the data memory (0xFF here) SP is initialized by the user! 12

13 Architecture Stack Example PUSH #1 PUSH #2 POP R0 13

14 Architecture Subroutine Call: 0x0A: JSR MyFunc 0x0C: NOP... start: PC = 0x0A SP = 0xFF MyFunc: 0x50: NOP 0x52: RET 14

15 Architecture Subroutine Call: 0x0A: JSR MyFunc 0x0C: NOP... MyFunc: 0x50: NOP 0x52: RET start: PC = 0x0A SP = 0xFF JSR is loaded PC = 0x0C JSR is interpreted PUSH PC ( > SP = 0xFE) PC = 0x50 15

16 Architecture Subroutine Call: 0x0A: JSR MyFunc 0x0C: NOP... MyFunc: 0x50: NOP 0x52: RET start: PC = 0x50 SP = 0xFE NOP is loaded PC = 0x52 NOP is interpreted 16

17 Architecture Subroutine Call: 0x0A: JSR MyFunc 0x0C: NOP... MyFunc: 0x50: NOP 0x52: RET start: PC = 0x52 SP = 0xFE RET is loaded PC = 0x54 RET is interpreted POP PC ( > PC = 0x0C) ( > SP = 0xFF) 17

18 Architecture Subroutine Call: 0x0A: JSR MyFunc 0x0C: NOP... MyFunc: 0x50: NOP 0x52: RET start: PC = 0x0C SP = 0xFF NOP is loaded PC = 0x0E NOP is interpreted...and so on... 18

19 Finally: our CPU is complete Datapath: ALU SR/CCR Register File PC contains next instr. SP for storing ret. addr. Control Architecture 19

20 Processor Core Architecture Instruction Set Lecture Overview 20

21 What can we do with the CPU? Instruction Format: Opcode [Operand]* Interesting information: types of instructions instruction size number of operands types of operands Instruction Set 21

22 Instruction Set Types of instructions: arithmetic and logic instructions branch instructions data transfer instructions bit instructions control instructions 22

23 Instruction Set Arithmetic and logic instructions ADD, SUB, MUL, INC, DEC,... AND, OR, NOT,... possibly special instructions for BCD arithmetic 23

24 Branch instructions Instruction Set everything that influences the program flow unconditional branches: JUMP (relative or absolute) conditional branches: BEQ, BNEQ subroutine calls: JSR, RET 24

25 Instruction Set Data transfer instructions instructions that move data, access memory load to/from registers: LD, ST copy data in memory: MOV tend to take many cycles (memory access) 25

26 Bit instructions Instruction Set an important feature of microcontrollers set/clear bits: BSET, BCLR test bits: BTST bit instructions are extremely important, they ensure that you can access a single output line without influencing other lines never access a bit you don't have to! 26

27 Control instructions are used to control the microcontroller simplest instruction: NOP (no operation, do nothing) control sleep mode: SLEEP, IDLE control watchdog Instruction Set cause a reset, enter debug mode,... 27

28 Interesting things: types of instructions instruction size number of operands types of operands Instruction Set 28

29 Instruction Size: 8 32 bits, fixed or variable long size has advantages and drawbacks: + many different instructions + many explicit operands, many different operand types large code size complex hardware CISC vs. RISC Instruction Set 29

30 Instruction Set CISC: Complex Instruction Set Computer complex (microcoded) instructions take many clock cycles to execute larger and often variable code size many addressing modes many instructions very powerful instructions 30

31 Instruction Set But: Study: 20% of instructions are responsible for 80% of code (80/20 rule) it is possible to simulate complex instructions with several simple ones 31

32 Instruction Set RISC: Reduced Instruction Set Computer simple (hardwired) instructions often take only one or few clock cycles to execute small fixed code size few addressing modes few instructions very fast execution of instructions 32

33 Instruction Set Which is better: RISC or CISC? depends on what you need! frequently need a powerful instruction/complex addressing mode > use CISC mostly need simple instructions and addressing modes > use RISC You must know which instructions/addr. modes you need to select the appropriate controller! 33

34 Interesting things: types of instructions instruction size number of operands types of operands Instruction Set 34

35 Instructions may require 0 3 operands, depending on their type: 0 operands: e.g. RET Instruction Set 1 operand: e.g. JUMP <addr> 2 operands: e.g. LOAD <dest>, <source> 3 operands: e.g. ADD <dest>, <source1>, <source2> 35

36 Instruction Set How many explicit operands does an instruction with 3 operands need? depends on the architecture, may be from 0 to 3! few operands imply short instructions, but it is not very flexible many operands allow for powerful instructions 36

37 0 Operands: 0 Address Format, Stack Architecture source operands are on the stack result is put on the stack Example: z = x + y PUSH x PUSH y ADD POP z Instruction Set ; push 1 st operand on stack ; push 2 nd operand on stack ; pop operands, add them, push result ; pop result 37

38 Instruction Set 1 Operand: 1 Address Format, Accumulator one source operand is implicit (accumulator register) result is saved in accumulator Example: z = x + y LDA x ADD y STA z ; load x into accumulator A ; add y to accu, store result in accu ; store value of accu A back to z 38

39 Instruction Set 2 Operands: 2 Address Format destination register is one of the source registers we assume that it is the first source Example: z = x + y LD R0, x ADD R0, y ST R0, z ; load x into register R0 ; add y to R0, store result in R0 ; store value of register R0 in z 39

40 Instruction Set 3 Operands: 3 Address Format sources and destination are explicit very powerful, but large instruction size Example: z = x + y ADD z, x, y ; add x and y, store result in z 40

41 Instruction Set Important Term: Load/Store Architecture memory access is slow > only do it with data transfer instructions arithmetic and logic instructions use registers register file contains many general purpose registers (i.e., all registers have the same functions) RISC architectures are load/store (register access is fast and easy compared to memory access) 41

42 Interesting things: types of instructions instruction size number of operands types of operands Instruction Set 42

43 Operand Types: constants registers memory locations Instruction Set 43

44 How do we specify the location of the operand? > Addressing Mode implicit immediate (constant) register direct/absolute... Instruction Set 44

45 Instruction Set Implicit Addressing Mode do not specify anything e.g. Stack Architecture: operands on stack 45

46 Instruction Set Immediate Addressing Mode for constants no data location, just a value how to distinguish from addresses? prefix, e.g. LD R0, #5 dedicated instructions, e.g. LDI R0, 5 (load immediate) 46

47 Register Addressing Mode operand is a register Instruction Set LD R0, R1 47

48 Instruction Set Direct/Absolute Addressing Mode operand is a memory address LD R0, 0x0FF M [0x0FF] 48

49 Register Indirect Instruction Set register contains memory address LD R0, (R1) M [R1] 49

50 Instruction Set Register Indirect with Autoincrement register contains memory address post increment, pre decrement (good for arrays) LD R0, (R1)+ M [R1], R1 < R1 + 1 LD R0, (R1) R1 < R1 1, M [R1] 50

51 Instruction Set Displacement/Based Register + Constant are address nice for arrays, data records LD R0, C(R1) M [C + R1] 51

52 Instruction Set Indexed Register + Register are address nice for arrays: one is base, one is index especially nice with autoincrement LD R0, (R1 + RX) M [R1+RX] 52

53 Memory Indirect Instruction Set memory contains address nice for jump tables LD M [M [R1]] 53

54 Instruction Set there are many more addressing modes for special accesses a given controller implements a subset of the addressing modes CISC controllers have more and more powerful addressing modes than RISC controllers 54

55 Instruction Set Summary types of instructions arithm./logic, branch, data transfer, bit, control instruction size CISC vs. RISC number of operands stack, accumulator, 2 address, 3 address types of operands constants/registers/memory, addressing modes 55

56 Processor Core Lecture Summary Architecture: datapath + control; ALU, reg. file, SR, PC, SP Instruction Set: different types of instructions (datasheet), CISC vs. RISC, addressing modes 56

Instruction-set Design Issues: what is the ML instruction format(s) ML instruction Opcode Dest. Operand Source Operand 1...

Instruction-set Design Issues: what is the format(s) Opcode Dest. Operand Source Operand 1... 1) Which instructions to include: How many? Complexity - simple ADD R1, R2, R3 complex e.g., VAX MATCHC substrlength,