Chapter 16 Control Unit Operation
Contents Micro-Operation Control of the Processor Hardwired Implementation 16-2
Micro-Operations Micro-Operations Micro refers to the fact that each step is very simple and accomplishes very little The execution of a program consists of the sequential execution of instructions Each instruction is executed during an instruction cycle made up of shorter subcycles The performance of each subcycle involves one or more shorter operations, that is, micro-operations 16-3
Constituent Element Micro-Operations 16-4
The Fetch Cycle Micro-Operations Four involved registers. Memory address register (MAR) : Is connected to the address lines of the system bus It specifies the address in memory for a read or write operation Memory buffer register (MBR) : Is connected to the data lines of the system bus It contains the value to be stored in memory or the last value read from memory Program counter (PC) : Holds the address of the next instruction to be fetched Instruction register (IR) : Holds the last instruction fetched 16-5
Sequence of Events, Fetch Cycle Micro-Operations (a) Beginning 16-6
Sequence of Events, Fetch Cycle Micro-Operations (b) First Step 16-7
Sequence of Events, Fetch Cycle (c) Second Step Micro-Operations 16-8
Sequence of Events, Fetch Cycle Micro-Operations (d) Third Step 16-9
The Fetch Cycle Sequence Micro-Operations (a) Beginning : the address of the next instruction to be executed is in the PC (b) First step : move that address to the MAR (c) Second step : bring in the instruction The desired address is placed on the address bus, the control unit issues a READ command on the control bus, and the result appears on the data bus and is copied into the MBR (d) Third step : move the contents of the MBR to the IR This free up the MBR for use during a possible indirect cycle 16-10
The Fetch Cycle Sequence Micro-Operations Symbolic presentation t 1 : MAR (PC) t 2 : MBR Memory PC (PC) + I t 3 : IR (MBR) Micro-operation grouping rules 1. The proper sequence of events must be followed 2. Conflicts must be avoided Micro-operation involve an addition - This addition could be performed by the ALU - The use of the ALU may involve additional micro-operations 16-11
The Indirect Cycle Micro-Operations Indirect addressing t 1 : MAR (IR(Address)) t 2 : MBR Memory t 3 : IR(Address) (MBR(Address)) 16-12
The Interrupt Cycle Micro-Operations t 1 : MBR (PC) t 2 : MAR Save_Address PC Routine_Address t 3 : Memory (MBR) 16-13
The Execute Cycle Micro-Operations ADD R1, X t 1 : MAR (IR(address)) t 2 : MBR Memory t 3 : R1 (R1) + (MBR) ISZ X (increment and skip if zero) t 1 : MAR (IR(address)) t 2 : MBR Memory t 3 : MBR (MBR) + 1 t 4 : Memory (MBR) If((MBR) = 0) then (PC (PC) +I) 16-14
The Execute Cycle Micro-Operations BSA X (branch and save address) t 1 : MAR (IR(address)) MBR (PC) t 2 : PC (IR(address)) Memory MBR t 3 : PC (PC) + I 16-15
The Instruction Cycle Micro-Operations There is one sequence each for the fetch, indirect, and interrupt cycle, and, for the execute cycle, there is one sequence of micro-operation for each opcode Instruction cycle code(icc) 00: Fetch 01: Indirect 10: Execute 11: Interrupt 16-16
Flowchart for Instruction Cycle Micro-Operations 16-17
Functional Requirements Control of the Processor The following three-step process leads to a characterization of the control unit: Define the basic elements of the processor Describe the micro-operations that the processor performs Determine the functions that the control unit must perform to cause the micro operations to be performed Basic functional elements ALU Register Internal data paths External data paths Control unit Control Of The Processor 16-18
Functional Requirements Control of the Processor The reader should see that all microoperations fall into the following categories Transfer data from one register to another Transfer data from a register to an external interface Transfer data from an external interface to a register Perform an arithmetic or logic operation, using registers for input and output The control unit perform two basic tasks Sequencing Execution 16-19
Control Signals Control of the Processor Inputs Clock Instruction register Flags Outputs Control signals within the processor Control signals to control bus 16-20
Model of Control Unit Control of the Processor 16-21
Control Signals Control of the Processor A control signal that opens gates, allowing the contents of the MAR onto the address bus A memory read control signal on the control bus A control signal that opens the gates, allowing the contents of the data bus to be stored in the MBR Control signals to logic that add 1 to the contents of the PC and store the result back to the PC 16-22
A Control Signals Example Control of the Processor Control signals go to three separate destinations Data paths ALU System bus 16-23
Data Paths and Control Signals Control of the Processor 16-24
Micro-operation operation and Control Signals Control of the Processor 16-25
Internal Processor Organization Control of the Processor The ALU and all processor registers are connected by a single internal bus Gates and control signals are provided for movement of data onto and off the bus from each register Two new registers,labeled Y and Z, have been added to the organization 16-26
CPU with Internal Bus Control of the Processor 16-27
Internal Processor Organization An operation to add a value from memory to the AC would have the following steps: Control of the Processor t 1 : MAR<-(IR(address)) t 2 : MBR<-Memory t 3 : Y<-(MBR) t 4 : Z<-(AC) + (Y) t 5 :AC<-(Z) Register Y provide temporary storage for the other input Register Z provide temporary output storage 16-28
The Intel 8085 Control of the Processor Incrementer/decrementer address latch Logic that can add 1 to or subtract 1 from the contents of the stack pointer or program counter Interrupt control This module handles multiple levels of interrupt signals Serial I/O control This module interfaces to devices that communicate 1 bit at a time 16-29
Intel 8085 CPU Block Diagram Control of the Processor 16-30
Intel8085 External Signals Control of the Processor 16-31
Intel8085 External Signals Control of the Processor 16-32
Intel 8085 Pin Configuration Control of the Processor 16-33
Timing and control Control of the Processor The control unit is identified as having two components labeled (1) instruction decoder and machine cycle encoding (2) Timing and control Timing and control accepts as inputs clock, current instruction and some external control signal Each instruction cycle is divided into from one to five machine cycles The number of machine cycles is fixed for a given instruction but varies from one instruction to another 16-34
Timing Diagram Control of the Processor 16-35
Hardwired Implementation Hardwired Implementation Control unit implementation Hardwired implementation Microprogrammed implementation 16-36
Control Unit Inputs Hardwired Implementation The key inputs are the instruction register, the clock, flags, and control bus signals To simplify the control unit logic, there should be a unique logic input for each opcode Decoder Takes an encoded input and produces a single output The clock portion of the control unit issues a repetitive sequence of pulses 16-37
Decoder Hardwired Implementation 16-38
Control Unit with Decoded Inputs Hardwired Implementation 16-39
Control Unit Logic Hardwired Implementation Derive a Boolean expression of that signal as a function of the inputs Define two new control signal, P and Q PQ = 00 PQ = 01 PQ = 10 PQ = 11 Fetch Cycle Indirect Cycle Execute Cycle Interrupt Cycle C 5 = P Q T 2 + P Q T 2 C 5 = P Q T2+ P Q T2+ P Q LDA+ ADD+ AND) ( T 2 16-40
Control Unit Logic Hardwired Implementation The task of implementing a combinatorial circuit that satisfies all of these equations becomes extremely difficult The results is that a far simpler approach Microprogramming 16-41