Chapter 12. CPU Structure and Function. Yonsei University

Transcription

1 Chapter 12 CPU Structure and Function

2 Contents Processor organization Register organization Instruction cycle Instruction pipelining The Pentium processor The PowerPC processor 12-2

3 CPU Structures Processor organization Fetch instructions CPU reads an instruction from memory Interpret instructions The instruction is decoded to determine what action is required Fetch data The execution may require reading data from memory or an I/O module Process data The execution may require performing arithmetic or logical operation on data Write data The result of an execution may require writing data to memory or I/O module 12-3

4 CPU With The System Bus Processor organization 12-4

5 Internal Structure of the CPU Processor organization 12-5

6 Registers Register organization CPU must have some working space (temporary storage) Called registers Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy 12-6

7 Registers Register organization User-visible registers Enable to minimize main memory references Control and status registers Enable the control unit to control the operation of the CPU Enable OS programs to control the execution of programs 12-7

8 User Visible Registers Register organization General Purpose Data Address Condition Codes 12-8

9 General Purpose Registers Can be assigned to a variety of functions May be true general purpose May be restricted May be used for data or addressing Register organization Make them general purpose Increase flexibility and programmer options Increase instruction size & complexity Make them specialized Smaller (faster) instructions Less flexibility 12-9

10 Data Registers Register organization Accumulator Only to hold data Cannot be employed in the calculation of an operand address 12-10

11 Address Registers Register organization Segment May be somewhat general purpose May be devoted to a particular addressing mode 12-11

12 Examples of Address Registers Register organization Segment pointers In a machine with segmented addressing, it holds the address of the base of the segment There may be multiple registers Index registers Used for indexed addressing May be autoindexed Stack pointer If there is user-visible stack addressing, then typically the stack is in memory and there is a dedicated register that points to the top of the stack This allows implicit addressing

13 How Many GP Registers? Register organization Between 8-32 Fewer = more memory references More does not reduce memory references and takes up processor real estate See also RISC 12-13

14 How big? Register organization Large enough to hold full address Large enough to hold full word Often possible to combine two data registers C programming double int a; long int a; 12-14

15 Design Issues Whether to use completely general purpose registers or to specialize their use The number of registers, either general purpose or data plus address, to be provided Register length Register that must hold addresses obviously must be at least long enough to hold the largest address Register organization 12-15

16 Condition Code Registers Register organization Sets of individual bits that set by the CPU hardware as the result of operations e.g. result of last operation was zero Condition code bits are collected into one or more registers Usually form part of a control register Can be read (implicitly) by programs e.g. Jump if zero Cannot be altered by programmers 12-16

17 Control & Status Registers Register organization CPU registers that are employed to control the operation of the CPU Program Counter Contains the address of an instruction to be fetched Instruction Register Contains the instruction most recently fetched Memory Address Register Contains the address of a location in memory Memory Buffer Register Contains a word of data to be written to memory or the word most recently read

18 Program Status Word Register organization Status Information Conditional code plus other status information 12-18

19 Flag of PSW Register organization Sign : Contains the sign bit of the result of the last arithmetic operation Zero : Set when the result is 0 Carry : Set if an operation resulted in a carry into or borrow out of a high-order bit Equal : Set if a logical compare result is equality Overflow : Used to indicate arithmetic overflow Interrupt enable/disable : Used to enable or disable interrupts Supervisor : Indicate whether the CPU is executing in supervisor or user mode 12-19

20 Other Registers Register organization Pointers to a block of memory containing additional status information (Process control blocks) Interrupt Vectors register System stack pointer If a stack is used, a system stack pointer is needed Page table pointer In virtual memory system Registers for the control of I/O operations 12-20

21 Design Issues Register organization Operating system support Certain types of control information are of specific utility to the operating system Allocation of control information between registers and memory Common to dedicate thousands words of memory for control purposes How much control information should be in registers and how much in memory 12-21

22 Example Register Organizations Register organization 12-22

23 Instruction Cycle Instruction cycle 12-23

24 Indirect Cycle Instruction cycle May require memory access to fetch operands Indirect addressing requires more memory accesses Can be thought of as additional instruction subcycle 12-24

25 Instruction Cycle Instruction cycle 12-25

26 Instruction Cycle with Indirect Alternating instruction fetch and instruction execution activities After an instruction is fetched, examine if any indirect addressing is involved If so, the required operands are fetched Following execution, an interrupt may be processed before the next instruction fetch Instruction cycle 12-26

27 Instruction Cycle State Diagram Instruction cycle 12-27

28 Data Flow - Instruction Fetch Instruction cycle Depends on CPU design In general: Fetch PC contains address of next instruction Address moved to MAR Address placed on address bus Control unit requests memory read Result placed on data bus, copied to MBR, then to IR Meanwhile PC incremented by

29 Data Flow - Fetch Cycle Instruction cycle 12-29

30 Data Flow - Data Fetch Instruction cycle IR is examined If indirect addressing, indirect cycle is performed Right most N bits of MBR transferred to MAR Control unit requests memory read Result (address of operand) moved to MBR 12-30

31 Data Flow - Indirect Cycle Instruction cycle 12-31

32 Data Flow - Execute Instruction cycle May take many forms Depends on instruction being executed May include Memory read/write Input/Output Register transfers ALU operations 12-32

33 Data Flow - Interrupt Instruction cycle Simple and Predictable Current PC saved to allow resumption after interrupt Contents of PC copied to MBR Special memory location (e.g. stack pointer) loaded to MAR MBR written to memory PC loaded with address of interrupt handling routine Next instruction (first of interrupt handler) can be fetched 12-33

34 Data Flow - Interrupt Cycle Instruction cycle 12-34

35 Two-stage Instruction Pipeline Instruction pipelining 12-35

36 Instruction Pipelining - Prefetch Instruction pipelining Fetch accessing main memory Execution usually does not access main memory Can fetch next instruction during execution of current instruction Called instruction prefetch or fetch overlap 12-36

37 Improved Performance Instruction pipelining Doubling of execution ratio is unlikely : Fetch usually shorter than execution Prefetch more than one instruction? Any jump or branch means that prefetched instructions are not the required instructions To reduce the time loss, when a conditional branch instruction is passed, fetch stage fetches the next instruction in memory after branch instruction If the branch is not taken, no loss Else, the fetched instruction must be discarded and a new instruction fetched Add more stages to improve performance 12-37

38 Pipelining Instruction pipelining Fetch instruction (FI) Read the next expected instruction into a buffer Decode instruction (DI) Determine the opcode and the operand specifiers Calculate operands (CO) Calculate effective address of each source operand Fetch operands (FO) Fetch each operand from memory Execute instruction (EI) Perform the operation and store the result Write operand (WR) 12-38

39 Timing of Pipeline Instruction pipelining 12-39

40 Timing of Pipeline Instruction pipelining Six stages of the pipeline This will not always be the case All stages can be performed in parallel Particularly assumed that there is no memory conflict The desired value may be in cache : Memory conflict won t slow down the pipeline 12-40

41 Limiting Factors Instruction pipelining Memory conflict if the cache is not used Unequal duration of stages There will be some waiting involved at stages The conditional branch instruction can invalidate several instruction fetches A similar unpredictable event is an interrupt 12-41

42 Conditional Branch in a Pipeline Instruction pipelining 12-42

43 Limiting Factors Instruction pipelining The CO stage depends on the contents of a register that could be altered by a previous instruction that is still in the pipeline Other such register and memory conflicts could occur 12-43

44 6-stage CPU Instruction Pipeline Instruction pipelining 12-44

45 Alternative Pipeline Depiction Instruction pipelining 12-45

46 Speed & The Number of Stages Instruction pipelining At each stage, overhead is involved in moving data from buffer to buffer and in performing various preparation and delivery functions This overhead can lengthen the total execution time of a single instruction This is significant when sequential instructions are logically dependent, either through heavy use of branching or through memory access dependencies The amount of control logic increases enormously with the number of stages The logic controlling the gating between stages is more complex than the stages being controlled 12-46

47 Pipeline Performance Instruction pipelining Cycle time Time needed to advance a set of instructions one stage through the pipeline [ ] i + d = m + d τ = max τ τ 1 i k τm k d = maximum stage delay = number of stages in the instruction pipeline = time delay of a latch 12-47

48 Pipeline Performance Instruction pipelining In general, the time delay d is equivalent to a clock pulse and Suppose that n instructions are processed Total time required Tk Speedup factor τm >> d Tk = [ k + ( n 1) ]τ S k = T T 1 k = nkτ = nk [ k + ( n 1) ] τ k + ( n 1) 12-48

49 Speedup Factors Number of instructions Instruction pipelining 12-49

50 Speedup Factors Number of stages Instruction pipelining 12-50

51 Dealing with Branches Instruction pipelining Until the instruction is actually executed, it is impossible to determine whether the branch will be taken or not Multiple Streams Prefetch Branch Target Loop buffer Branch prediction Delayed branching 12-51

52 Multiple Streams Instruction pipelining Replicate the initial portions of the pipeline and allow the pipeline to fetch both instructions, making use of two streams Two problems with this approach Contention delays for access to the registers and to memory Additional branch instructions may enter the pipeline before original branch decision is resolved Each such instruction needs an additional stream Despite these drawbacks, this strategy can improve performance 12-52

53 Prefetch Branch Target Instruction pipelining The target of the branch is prefetched in addition to the instruction following the branch Keep the target until the branch is executed If the branch is taken, the target has already been prefetched Used by IBM 360/

54 Loop Buffer Instruction pipelining A small, very-high-speed memory maintained by fetch stage of the pipeline and containing the n most recently fetched instructions, in sequence If a branch is to be taken, the hardware first checks whether the branch target is within the buffer If so, the next instruction is fetched from the buffer Very good for small loops or jumps 12-54

55 Benefits of Loop Buffer Instruction pipelining With the use of prefetching, the loop buffer will contain some instruction sequentially ahead of the current instruction fetch address If a branch occurs to a target a few locations ahead of the address of the branch instruction, the target will already be in the buffer Useful for the rather common occurrence of IF- THEN and IF-THEN-ELSE sequences Well suited to dealing with loops, or iterations 12-55

56 Loop Buffer Instruction pipelining 12-56

57 Branch Prediction Instruction pipelining Static approaches Do not depend on the execution history up to the time of the conditional branch instruction Predict never taken Predict always taken Predict by opcode Dynamic approaches Do depend on the execution history Improve the accuracy of prediction by recording the history of conditional branch instructions Taken/not taken switch Branch history table 12-57

58 Static Approaches Predict never taken Assume that jump will not happen Always fetch next instruction & VAX 11/780 VAX will not prefetch after branch if a page fault would result (O/S v CPU design) Predict always taken Conditional branches are taken more than 50% Assume that jump will happen Always fetch target instruction Predict by Opcode Some instructions are more likely to result in a jump than others Success rate > 75% Instruction pipelining

59 Dynamic Approaches Instruction pipelining Taken/Not taken switch History bits : One or more bits can be associated with each conditional branch instruction that reflects the recent history of the instruction History bits are kept in temporary high-speed storage Associate some history bits with any conditional branch instruction that is in a cache When the instruction is replaced in the cache, its history is lost Maintain a small table for recently executed branch instruction with one or more bits in each entry Good for loops 12-59

60 Dynamic Approaches Instruction pipelining Taken/Not taken switch (with a single bit) With a single bit, it s only recorded whether the last execution of this instruction resulted in a branch or not Disadvantages Used in the case of a conditional branch instruction that is almost always taken, such as a loop instruction Error in prediction will occur twice : once on entering the loop and once on exiting 12-60

61 Dynamic Approaches Instruction pipelining Taken/Not taken switch (with two bits) With two bits, it can be recorded the result of the last two instances of the execution of the associated instruction and a state in some other fashion If the last two branches of the given instruction have taken the same path, the prediction is to take that path again If the prediction is wrong, it remains the same the next time the instruction is encountered If the prediction is wrong again, the next prediction will be to select the opposite path 12-61

62 Branch Prediction Flowchart Instruction pipelining 12-62

63 Branch Prediction State Diagram Instruction pipelining 12-63

64 Dynamic Approaches Instruction pipelining Drawback of the use of history bits If the decision is made to take the branch, the target instruction cannot be fetched until the target address is decoded Greater efficiency could be achieved if the instruction fetch could be initiated as soon as the branch is made 12-64

65 Dynamic Approaches Instruction pipelining Branch history table A small cache memory associated with the instruction fetch stage of the pipeline Each entry in the table consists The address of a branch instruction Some number of history bits that record the state of use of that information Information about the target instruction This yields a shorter instruction fetch time, but a greater table compared with storing the target address 12-65

66 Predict Never Taken Strategy Instruction pipelining 12-66

67 Branch History Table Instruction pipelining 12-67

68 Delayed Branch Instruction pipelining Possible to improve pipeline performance by automatically rearranging instructions so that branch instructions occur later than actually desired Do not take jump until you have to Rearrange instructions 12-68

69 Intel Pipelining Instruction pipelining Fetch : instructions are fetched from the cache or from the external memory and placed into one of the two 16-byte prefetch buffers Decode stage1 : All opcode and addressingmode information is decoded Decode stage2 : This stage expands each opcode into control signals for ALU Execute : This stage includes ALU operations, cache access and register update Write back : If needed, this stage updates registers and status flags modified during the preceding execution stage

70 Intel Pipelining Fetch From cache or external memory Put in one of two 16-byte prefetch buffers Fill buffer with new data as soon as old data consumed Average 5 instructions fetched per load Independent of other stages to keep buffers full Decode stage 1 Opcode & address-mode info At most first 3 bytes of instruction Can direct D2 stage to get rest of instruction Decode stage 2 Expand opcode into control signals Computation of complex address modes Execute ALU operations, cache access, register update Writeback Update registers & flags Results sent to cache & bus interface write buffers Instruction pipelining

71 No Data Delay of Instruction pipelining No delay introduced into the pipeline when a memory access is required 12-71

72 Pointer Load Delay of Instruction pipelining A delay for values used to compute memory address 12-72

73 Pointer Load Delay of The processor accesses the cache in the EX stage of the first instruction and stores the value retrieved in the register during the WB stage The next instruction needs that register in the D2 stage When the D2 stage lines up with the WB stage of the previous instruction, bypass signal paths allow the D2 stage to have access to the same data being used by the WB stage for writing, saving one pipeline stage Instruction pipelining 12-73

74 Branch Instruction Timing Instruction pipelining Assume that the branch is taken 12-74

75 Branch Instruction Timing Instruction pipelining The compare instruction updates condition codes in the WB stage and bypass paths make this available to the EX stage of the jump instruction at the same time In parallel, the processor runs a speculative fetch cycle to the target of the jump during the EX stage of the jump instruction If the processor determines a false branch condition, it discards this prefetch and continues execution with the next sequential instruction 12-75

76 Pentium Processor Registers Pentium processor 12-76

77 EFLAGS Register Pentium processor 12-77

78 EFLAGS Register Pentium processor 6 condition codes 7 flags that may be referred to as control bits Trap flag (TF) Interrupt enable flag (IF) Direction flag (DF) I/O privilege flag (IOPL) Resume flag (RF) Alignment check (AC) Identification flag (ID) 12-78

79 Control Registers Pentium processor 12-79

80 Control Registers Pentium processor Flags Protection enable (PE) Monitor coprocessor (MP) Emulation (EM) Task switched (TS) Extension type (ET) Numeric error (NE) Write protect (WP) Alignment mask (AM) Not write through (NW) Cache disable (CD) Paging (PG) 12-80

81 Control Register 4 (CR4) Pentium processor Nine additional control bits Virtual-8086 mode extension Protected-mode virtual interrupts Time stamp disable Debugging extensions Page size extensions Physical address extension Machine check enable Page global enable Performance counter enable 12-81

82 MMX Register Mapping Pentium processor MMX uses several 64 bit data types Use 3 bit register address fields 8 registers No MMX specific registers Aliasing to lower 64 bits of existing floating point re gisters 12-82

83 MMX Registers Pentium processor 12-83

84 Features of MMX Registers Pentium processor For MMX operations, the floating-point registers are accessed directly The first time that an MMX instruction is executed after any floating-point operations, the FP tag word is marked valid The EMMS(Empty MMX state) instruction sets bits of the FP tag word to indicate that all registers are empty The programmer insert this instruction at the end of an MMX code block so that subsequent FP operations function properly When a value is written to an MMX register, bits[79:64] of the corresponding register are set to all ones 12-84

85 Interrupt Processing Interrupts and exceptions Pentium processor Interrupt vector table Interrupt handling 12-85

86 Interrupts Generated by a signal from hardware May occur at random times during the execution of a program Pentium processor Two sources of interrupts Maskable interrupts Processor doesn t recognize a maskable interrupt unless the interrupt enable flag(if) is set Nonmaskable interrupts Recognition of such interrupts cannot be prevented 12-86

87 Exceptions Pentium processor Generated from software Provoked by the execution of an instruction Two sources of exceptions Processor-detected exceptions Results when the processor encounters an error while attempting to execute an instruction Programmed exceptions These are instructions that generate an exception 12-87

88 Exception and Interrupt Vector Pentium processor 12-88

89 Interrupt Vector Table Pentium processor Every type of interrupt is assigned a number This number is used to index into the interrupt vector table If more than one exception or interrupt is pending, the processor services them in a predictable order The order of priority Class1 : Traps on the previous instruction Class2 : External interrupts Class3 : Faults from fetching next instruction Class4 : Faults from decoding the next instruction Class5 : Faults on executing an instruction 12-89

90 Interrupt Handling Pentium processor When an interrupt occurs and is recognized by the processor If the transfer involves a change of privilege level, the current stack segment register and the current extended stack pointer register are pushed onto the stack The current value of the EFLAGS register is pushed onto the stack Both the interrupt and trap flags are cleared The current code segment pointer and the current instruction pointer are pushed onto the stack If the interrupt is accomplished by an error code, the error code is pushed onto the stack The interrupt vector contents are fetched and loaded into the CS and IP or EIP registers 12-90

91 PowerPC G3 Block Diagram PowerPC processor 12-91

92 User-Visible Registers PowerPC processor 12-92

93 Register Organization PowerPC processor Fixed-point unit General bit general-purpose registers These may be used to load, store and manipulate data operands and also be used for register indirect addressing Exception register Includes 3 bits that report exceptions in integer arithmetic operations 12-93

94 PowerPC Register Formats PowerPC processor 12-94

95 Register Organization PowerPC processor Floating-point unit contains additional uservisible registers General bit general-purpose registers These may be used for all floating-point operations Floating-point status and control register Includes bits that control the operation of the floating-point unit and bits that record the status resulting from floating-point operations 12-95

96 FP Status and Control Register PowerPC processor 12-96

97 Register Organization PowerPC processor Branch processing unit Conditional register 8 4-bit condition code fields Link register Can be used in a conditional branch instruction for indirect addressing of the target address Also used for call/return behavior Count The count register can be used to control an iteration loop 12-97

98 Condition Register Interpretation of Bits in Condition Register PowerPC processor 12-98

99 PowerPC Interrupt Table PowerPC processor 12-99

100 Interrupt Processing PowerPC processor Machine state register Fundamental to the interruption of a program is the ability to recover the state of the processor at the time of the interrupt

101 Machine State Register PowerPC processor

102 Interrupt Handling PowerPC processor When interrupts occurs, the following sequence takes place The processor places the address of the instruction to be executed next in the Save/Restore Register 0 (SRR0) The processor copies machine state information from the MSR to the SRR1 The MSR is set to a hardware-defined value specific to the interrupt type The processor transfers control to the appropriate interrupt handler