ARTIST-Relevant Research from Linköping Department of Computer and Information Science (IDA) Linköping University http://www.ida.liu.se/~eslab/ 1
Outline Communication-Intensive Real-Time Systems Timing Analysis and Optimisation with FlexRay Time -and Buffer Space Analysis for NoCs A Simulator for Distributed Embedded Applications Predictability (even in the presence of faults) Timing Predictability for Multiprocessors Predictability in the Presence of Faults 2
Heterogeneous Distributed Embedded Systems Time triggered cluster: TT tasks Static communication Event triggered cluster: ET tasks Dynamic communication 3
Heterogeneous Distributed Embedded Systems N 0 N 1 N n TT TT TT ET f.p. ET f.p. ET f.p. edf edf edf Hierarchical Scheduler 4
Heterogeneous Distributed Embedded Systems N 0 N 1 N n TT TT TT ET f.p. ET f.p. ET f.p. edf edf edf Hierarchical Scheduler Bus cycle - UCM (TTP&CAN) - FlexRay static phase dynamic phase static phase dynamic phase static phase 5
FlexRey-Based System N 0 N 1 N n TT TT TT ET f.p. ET f.p. ET f.p. edf edf edf Hierarchical Scheduler Bus cycle FlexRay Static phase: TDMA Dynamic phase: Flexible TDMA static phase dynamic phase static phase dynamic phase static phase 6
FlexRey-Based System N 1 N 2 N 3 Host (CPU) Controller-Host Interface (CHI) m b 2/2 Schedule table 2 3 1 3 2 4 1 5 Communication controller m a 1/1 m c 1/3 m e m g m f low high Priority queues m d m h T bus T bus Static segment Dynamic segment Static segment Dynamic segment m a m c m d m e m f m b m g m h MS MS MS MS MS 1 2 3 1 2 3 4 5 1 2 3 123 4 5 MS Static slot counter Dynamic slot counter 1 2 3 4 5 6 7 8 9 101112 Minislot counter 1 2 3 4 5 6 7 8 9 101112 7
Strange Priority Inversions! m 3 FlexRey-Based System m 2 m 1 N 1 N 2 1 3 2 ST = 8 m 1 m 3 ST m 2 MS...... MS 0 DYN slot counter: 1 2 3 1 2 minislot counter: 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9...... 8
FlexRey-Based System Response-time analysis cannot be solved by just extending response time analysis for priority-based scheduling, like for CAN. Determining the number of bus cycles a message has to wait, is - in a simplified formulation - a bin covering problem. 9
FlexRey-Based System Response-time analysis cannot be solved by just extending response time analysis for priority-based scheduling, like for CAN. Determining the number of bus cycles a message has to wait, is - in a simplified formulation - a bin covering problem. Bus access optimisation assign FrameID to nodes and messages determine size of dynamic/static segment ECRTS 06 determine number of static slots 10
Outline Communication-Intensive Real-Time Systems Timing Analysis and Optimisation with FlexRay Time -and Buffer Space Analysis for NoCs A Simulator for Distributed Embedded Applications Predictability (even in the presence of faults) Timing Predictability for Multiprocessors Predictability in the Presence of Faults 11
Time -and Buffer Space Analysis for NoCs S 0,1 S 1,1 S 2,1 S 3,1 P 0,1 P 1,1 P 2,1 P 3,1 τ 1 τ 2 τ 7 S 0,0 S 1,0 S 2,0 S 3,0 P 0,0 P 1,0 τ 9 τ 10 τ 11 P 2,0 τ 8 P 3,0 τ 5 τ 6 τ 3 τ 4 12
Time -and Buffer Space Analysis for NoCs S 0,1 S 1,1 S 2,1 S 3,1 P 0,1 P 1,1 P 2,1 P 3,1 τ 1 τ 2 τ 7 S 0,0 S 1,0 S 2,0 S 3,0 P 0,0 P 1,0 τ 9 τ 10 τ 11 P 2,0 τ 8 P 3,0 τ 5 τ 6 τ 3 τ 4 13
Time -and Buffer Space Analysis for NoCs Scenario in which an application-specific NoC is built Find a communication mapping and the packet release times of all packets and determine the amount of buffer memory at each switch such that No deadline is missed and no buffer overflow occurs The total amount of buffer memory is minimised Message arrival probability is above a specified threshold given a link failure model. 14
Time -and Buffer Space Analysis for NoCs Scenario in which the application is implemented on an existing NoC with given buffer memory at each switch Find a communication mapping and the packet release times of all packets such that No deadline is missed and no buffer overflow occurs Message arrival probability is above a specified threshold given a link failure model. DATE 06 15
Outline Communication-Intensive Real-Time Systems Timing Analysis and Optimisation with FlexRay Time -and Buffer Space Analysis for NoCs A Simulator for Distributed Embedded Applications Predictability (even in the presence of faults) Timing Predictability for Multiprocessors Predictability in the Presence of Faults 16
A Simulator for Distributed Embedded Applications N 1 N 2 τ 1 τ 2 τ 3 τ 4 τ 1 τ 2 τ 3 τ 4 Synchronizer Scheduler1 Scheduler3 Scheduler2 N 1 bus N 2 17
A Simulator for Distributed Embedded Applications N 1 N 2 τ 1 τ 2 τ 3 τ 4 τ 1 τ 2 τ 3 τ 4 Synchronizer TT ET Static Dynamic TT ET N 1 bus N 2 18
A Simulator for Distributed Embedded Applications CAN, TTP, UCM, FlexRay τ 1 τ 2 τ 3 τ 4 Synchronizer TT ET Static Dynamic TT ET N 1 bus N 2 Scheduler specification Protocol specification Scheduler specification 19
A Simulator for Distributed Embedded Applications Compare Scheduling approaches Communication protocols 20
A Simulator for Distributed Embedded Applications Compare Scheduling approaches Communication protocols Interesting issues to look at: Pessimism of analysis Jitter, delay Quality of Control Syntetic applications and actual code 21
Outline Communication-Intensive Real-Time Systems Timing Analysis and Optimisation with FlexRay Time -and Buffer Space Analysis for NoCs A Simulator for Distributed Embedded Applications Predictability (even in the presence of faults) Timing Predictability for Multiprocessors Predictability in the Presence of Faults 22
Predictability τ 1 τ 2 τ 3 WCET τ 1 WCET τ 2 WCET τ 3 τ 1 τ 2 τ 3 23
Predictability τ 1 τ 2 τ 3 τ 1 τ 2 τ 3 cache cache cache private memory private memory private memory shared memory 24
Predictability τ 1 τ 2 Explicit communication τ 3 τ 1 τ 2 τ 3 cache cache cache private memory private memory private memory shared memory 25
Predictability τ 1 τ 2 Implicit communication τ 3 τ 1 τ 2 τ 3 cache cache cache private memory private memory private memory shared memory 26
Predictability τ 1 τ 2 WCET τ? 1 WCET τ 2? WCET τ? 3 τ 3 τ 1 τ 2 τ 3 cache cache cache private memory private memory private memory shared memory 27
Predictability WCET cannot be determined by taking tasks in isolation. WCET analysis has to be brought into the context of system analysis and optimisation. 28
Predictability WCET cannot be determined by taking tasks in isolation. WCET analysis has to be brought into the context of system analysis and optimisation. Trade-offs: Local WCET vs. global schedulability What is the cost of predictability? 29
Another Issue: Faults Transient faults Their number can be much larger than that of permanent faults. Find cost-effective implementations that are fault tolerant and satisfy time constraints. Some Interesting trade-offs! 30
Fault Tolerance Decide which fault tolerance technique to apply: re-execution re-exution&checkpointing replication different techniques can be applied to different tasks 31
Fault Tolerance Decide which fault tolerance technique to apply: re-execution re-exution&checkpointing replication Map the tasks (including eventual replicas) 32
Fault Tolerance Decide which fault tolerance technique to apply: re-execution re-exution&checkpointing replication Map the tasks (including eventual replicas) Decide on transparency Transparent: The schedule of outgoing messages does not depend on occurrence of faults (faults are not visible to the outside). 33
Fault Tolerance Decide which fault tolerance technique to apply: re-execution re-exution&checkpointing replication Map the tasks (including eventual replicas) Decide on transparency Do the analysis/scheduling, considering worst case number of faults (re-executions). Are time constraints satisfied? If not, go back! 34
Fault Tolerance Decide which fault tolerance technique to apply: re-execution re-exution&checkpointing replication Map the tasks (including eventual replicas) Decide on transparency Do the analysis/scheduling, considering worst case number of faults (re-executions). Are time constraints satisfied? If not, go back! Which is the optimal number of check-points? DATE 05 DATE 06 35