CSc 256 Midterm 2 Fall 2011 NAME: 1a) You are given a MIPS branch instruction: x: beq $12, $0, y The address of the label "y" is 0x400468. The memory location at "x" contains: address contents 0x40049c 000100 01100 00000????????????????... which represents the beq instruction. Find the 16- bit constant indicated by the????. (12 points) ANS: BTA = &beq + 4 + offset 0x400468 = 0x4004a0 + 4 + offset offset = 0x400468 0x4004a4 = 0x400468 + 0xffbf fb60 = 0xffff ffc8 = 1111 1111 1111 1111 1111 1111 1100 1000 16- bit constant = 1111 1111 1111 0010 1b) You are given this MIPS assembly language instruction (i.e., pseudo- instruction): lb $23, 0x10010014($11) Translate this MIPS instruction to an efficient sequence of machine language instructions. You only have to show the text form of the machine language instructions; don't translate into binary. ANS: Lui $1, 0x1001 Add $1, $1, $11 Lb $23, 0x14($1)
1c) This is a memory location that contains a MIPS instruction: address [0x00400024] contents 0x0067a820 Translate it into the MIPS assembly language instruction (show the operation, operands, etc): (13 points) ANS: add $21, $3, $7 0x0067a820 = 0000 0000 0110 0111 1010 1000 0010 0000 opcode = 0 (R- format) rs = 00011 rt = 00111 rd = 10101 FUNC code: add
Problem 2: Consider this digital logic circuit:
a) Fill out an equivalent truth table for the circuit. (14 points) X2 X1 X0 Y 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0 b) Write an equivalent logic expression for output y, in sum of products form. (6 points) y = ~x2~x1x0 + ~x2x1x0 + x2~x1~x0 + x2~x1x0
Problem 3: Refer to the MIPS single-cycle datapath in the sheets provided. Show the control signals for the MIPS instructions, in the table below. Note that some of the control signals have new names. (30 points) Hint: ALUOp control bits are 00 (force ALU to add), 01 (force ALU to subtract), 10 (follow operation specified by bits 5-0 of instruction word) [SelE: branch, SelF: RegDst, SelG: AlUSrc, SelH: MemToReg] a) sw SelE SelF SelG SelH MemRead MemWrite RegWrite ALUOp1 ALUOp0 0 x 1 x 0 1 0 0 0 b) R-format SelE SelF SelG SelH MemRead MemWrite RegWrite ALUOp1 ALUOp0 0 1 0 0 x 0 1 1 0
Problem 4: For the MIPS single-cycle datapath given, suppose we build a new implementation using different technology. These are the latencies through the main components: Register Read Register Write ALU operation Memory Read Memory Write 250 ps 250 ps T A ps 400 ps 400 ps a) We are given that the time taken for a sw to complete (i.e., the latency of the sw) is 1250 ps. Solve for T A. (8 points) 1250 = 400 (IF) + 250 (ID) + T A (EX) + 400 (MEM) = 1050 + T A T A = 1250 = 1050 = 200 ps b) How much time does a lw take to complete? (6 points) latency for lw = 400 (IF) + 250 (ID) + 200 (EX) + 400 (MEM) + 250 (WB) = 1500 ps
c) What is the clock rate in MHz for this new MIPS implementation? You don t have to give the actual number as the answer; just show an equation that can be solved to get the clock rate in MHz. (Hint: 1 ps = 10^-12 seconds, 1 ns = 10^-9 seconds, 1 MHz = 10^6 Hz.) (6 points) ANS: Clock rate in Hz = 1 / 1500 ps = 10^12 / 1500 Hz Clock rate in MHz = 10^-6 * 10^12 / 1500 = 10^6/1500 MHz
MIPS instructions op1, op2 are registers, op3 is register or constant cont[op1] means contents of op1 move op1, op2 cont[op1] = cont[op2] add op1, op2, op3 cont[op1] = cont[op2] + cont[op3] sub op1, op2, op3 cont[op1] = cont[op2] - cont[op3] mul op1, op2, op3 cont[op1] = cont[op2] * cont[op3] div op1, op2, op3 cont[op1] = cont[op2] / cont[op3] rem op1, op2, op3 cont[op1] = cont[op2] % cont[op3] not op1, op2 cont[op1] = not cont[op2] (bitwise) and op1, op2, op3 cont[op1] = cont[op2] and cont[op3] (bitwise) or op1, op2, op3 cont[op1] = cont[op2] or cont[op3] (bitwise) nand op1, op2, op3 cont[op1] = cont[op2] nand cont[op3] (bitwise) nor op1, op2, op3 cont[op1] = cont[op2] nor cont[op3] (bitwise) xor op1, op2, op3 cont[op1] = cont[op2] xor cont[op3] (bitwise) sll op1, op2, AMT cont[op1] = cont[op2] shift left logical by AMT bits srl op1, op2, AMT cont[op1] = cont[op2] shift right logical by AMT bits sra op1, op2, AMT cont[op1] = cont[op2] shift right arithmetic by AMT bits rol op1, op2, AMT cont[op1] = cont[op2] rotate left by AMT bits ror op1, op2, AMT cont[op1] = cont[op2] rotate right by AMT bits b label j label beq op1, op2, label bne op1, op2, label bgt op1, op2, label bge op1, op2, label blt op1, op2, label ble op1, op2, label beqz op1, label bnez op1, label bgtz op1, label bgez op1, label bltz op1, label blez op1, label la R, label li R, constant lw R,?? goto label goto label if (cont[op1]==cont[op2]) goto label if (cont[op1]!=cont[op2]) goto label if (cont[op1]>cont[op2]) goto label if (cont[op1]>=cont[op2]) goto label if (cont[op1]<cont[op2]) goto label if (cont[op1]<=cont[op2]) goto label if (cont[op1]==0) goto label if (cont[op1]!=0) goto label if (cont[op1]>0) goto label if (cont[op1]>=0) goto label if (cont[op1]<0) goto label if (cont[op1]<=0) goto label cont[r] = address of label cont[r] = constant cont[r] = M[ADDR]
lb R,?? lbu R,?? sw R,?? sb R,?? cont[r] = m[addr], sign- extended cont[r] = m[addr], zero- extended M[ADDR] = cont[r] m[addr] = low 8- bits of cont[r] if?? is a label, ADDR = address of label if?? is (R), ADDR = cont[r] if?? is constant(r), ADDR = cont[r] + constant if?? is label(r), ADDR = cont[r] + address of label mtc0 op1, op2 contents of coprocessor 0 register op1 = contents of MIPS register op2 mfc0 op1, op2 contents of MIPS register op1 = contents of coprocessor 0 register op2 Syscall usage: print an int $v0=1, $a0=int to be printed print a string $v0=4, $a0=address of string to be printed read an int $v0=5, input int appears in $v0 exit $v0=10 MIPS register names: $0 $1 $2,$3 $v0,$v1 $4 - $7 $a0 - $a3 $8 - $15 $t0 - $t7 $16 - $23 $s0 - $s7 $24 - $25 $t8 - $t9 $26 - $27 $k0 - $k1 $28 $gp $29 $sp $30 $s8 $31 $ra
0000 00ss ssst tttt dddd d000 0010 0000 add rd,rs,rt 0000 00ss ssst tttt dddd d000 0010 0010 sub rd,rs,rt 0000 00ss ssst tttt 0000 0000 0001 1000 mult rs,rt 0000 00ss ssst tttt 0000 0000 0001 1010 div rs,rt 0000 00ss ssst tttt dddd d000 0010 0001 addu rd,rs,rt 0000 00ss ssst tttt dddd d000 0010 0011 subu rd,rs,rt 0000 00ss ssst tttt 0000 0000 0001 1001 multu rs,rt 0000 00ss ssst tttt 0000 0000 0001 1011 divu rs,rt 0000 0000 0000 0000 dddd d000 0001 0000 mfhi rd 0000 00ss sss0 0000 0000 0000 0001 0001 mthi rs 0000 0000 0000 0000 dddd d000 0001 0010 mflo rd 0000 00ss sss0 0000 0000 0000 0001 0011 mtlo rs 0000 00ss ssst tttt dddd d000 0010 0100 and rd,rs,rt 0000 00ss ssst tttt dddd d000 0010 0111 nor rd,rs,rt 0000 00ss ssst tttt dddd d000 0010 0101 or rd,rs,rt 0000 00ss ssst tttt dddd d000 0010 0110 xor rd,rs,rt 0000 00ss ssst tttt dddd d000 0000 0100 sllv rd,rt,rs 0000 00ss ssst tttt dddd d000 0000 0110 srlv rd,rt,rs 0000 00ss ssst tttt dddd d000 0000 0111 srav rd,rt,rs 0010 00ss ssst tttt iiii iiii iiii iiii addi rt,rs,i 0010 01ss ssst tttt iiii iiii iiii iiii addiu rt,rs,i 0011 00ss ssst tttt iiii iiii iiii iiii andi rt,rs,i 0011 1100 000t tttt iiii iiii iiii iiii lui rt,i 0011 01ss ssst tttt iiii iiii iiii iii ori rt,rs,i 0011 10ss ssst tttt iiii iiii iiii iiii xori rt,rs,i 0000 0000 000t tttt dddd diii ii00 0000 sll rd,rt,i 0000 0000 000t tttt dddd diii ii00 0010 srl rd,rt,i 0000 0000 000t tttt dddd diii ii00 0011 sra rd,rt,i 1000 11bb bbbt tttt iiii iiii iiii iiii lw rt,i(rb) 1000 00bb bbbt tttt iiii iiii iiii iiii lb rt,i(rb) 1001 00bb bbbt tttt iiii iiii iiii iiii lbu rt,i(rb) 1010 11bb bbbt tttt iiii iiii iiii iiii sw rt,i(rb) 1010 00bb bbbt tttt iiii iiii iiii iiii sb rt,i(rb) 0000 01ss sss0 0000 iiii iiii iiii iiii bltz rs,i 0000 01ss sss0 0001 iiii iiii iiii iiii bgez rs,i 0001 10ss sss0 0000 iiii iiii iiii iiii blez rs,i 0001 11ss sss0 0000 iiii iiii iiii iiii bgtz rs,i 0001 00ss ssst tttt iiii iiii iiii iiii beq rs,rt,i
0001 01ss ssst tttt iiii iiii iiii iiii bne rs,rt,i 0000 00ss ssst tttt dddd d000 0010 1010 slt rd,rs,rt 0010 10ss ssst tttt iiii iiii iiii iiii slti rt,rs,i 0000 10ii iiii iiii iiii iiii iiii iiii j I 0000 00ss sss0 0000 0000 0000 0000 1000 jr rs 0000 11ii iiii iiii iiii iiii iiii iiii jal I 0000 00ss sss0 0000 dddd d000 0000 1001 jalr rd,rs 0000 0000 0000 0000 0000 0000 0000 1100 syscall