Quartus II Prime Foundation

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Quartus II Prime Foundation Course Description This course provides all theoretical and practical know-how to design programmable devices of ALTERA with Quartus Prime design software. The course combines 50% theory with 50% practical work in every meeting. The practical labs cover all the theory. The course starts with an overview of the Quartus Prime design software features, Quartus Prime projects types and management, design methodology, and using IP cores from the IP catalog. Qsys system integration tool, state machine editor, memory editor, Altera SD for OpenCL, and DSP Builder are also introduced in high level. The course continues with Quartus Prime compilation flow, incremental compilation concept, working with messages, viewing compilation reports, RTL and technology views, state machine viewer, and how to use the chip planner tool. The course also touches upon synthesis and Place & Route settings and assignment editor, optimizations, design assistant and various advisors. The course ends with I/O planning with the pin planner, with the BluePrint Platform Designer, and programming and configuration of FPGA/CPLD. Course Duration 2 days

Goals 1. Create a new Quartus Prime project 2. Choose supported design entry methods 3. Compile a design into a programmable logic device 4. Locate resulting compilation information 5. Create design constraints (assignments & settings) 6. Manage I/O assignments 7. Prepare for programming/configuring a programmable logic device Intended Users Hardware engineers who program with VHDL/Verilog languages and would like to be specialized with ALTERA FPGAs and Quartus II software Previous Knowledge VHDL/Verilog beginners and advanced users who are new to ALTERA FPGAs. Course Material 1. Synthesizer and Place & Route: Quartus Prime 2. Demonstration on ALTERA Evaluation board 3. Course book (including labs)

Table of Contents Day #1 Introduction to Programmable Logic Devices o CPLD architecture and design consideration o FPGA architecture (LUT, FF, PLL, DSP Block, Embedded RAM, Embedded Processor, Programming) Introduction to ALTERA FPGAs o CPLD : MAX V, MAX II o FPGA : Max 10 Cyclone, ARIA, STRATIX, SoC ARM based o FPGA: Gen 10 devices and SoC Introduction to Quartus Prime Software o Lite Edition, Standard Edition and Pro Edition o Quartus Prime design software features o Quartus Prime default operating environment o Tips and tricks advisor o Built in help system o Custom task flow o TCL and command line help Quartus Prime Projects o Project creation and project types o Altera design store o EDA tool settings o Quartus Prime project files and folders o Constraint files & assignment priority o Project management (archive, restore, copy, revisions, clean) o IP management tools Lab #1: Create a Project in Quartus Prime

Design Methodology o Typical PLD design flow o Design entry methods (schematic, HDL, EDIF) o Altera IP cores o IP catalog o System design entry with Qsys o State machine editor o Memory editor o DSP Builder standard/advanced blocksets o Open Computing Language (OpenCL) o Synthesis and P&R o Programmer Lab #2: Use IPs from the IP Catalog and the Memory Editor RTL Coding Guidelines for QUARTUS II Integrated Synthesis o Synthesis directives and attributes o Fixed output registers o RAM inference o Latch inference o Combinational loops o Finite state machine coding styles Lab #3: Use Synthesis Attributes to Affect Quartus Prime Synthesis Results

Day #2 Quartus Prime Compilation o Quartus Prime full compilation flow o Processing options o Notification center o Compilation design flows o Incremental compilation concept o Reducing compile times o Message windows o Viewing compilation results o Dynamic synthesis report o Netlist viewers o State machine viewer o Chip planner o Resource property editor Lab #4: Compile a Project in Quartus Prime and Locate Information in the Compilation Report Settings & Assignments o Synthesis and fitting control o Device settings o Version compatible database o Consolidated compiler optimization settings (synthesis & fitter) o Assignment editor features o Assignment groups o Updating.qsf file o Assignment Tcl command o Export assignment o Design assistant o Advisors Lab #5: Create a New Revision and Make Design Constraints using the Assignment Editor

I/O Planning o I/O planning need o Creating I/O related assignments o Pin planner tool o Assigning pin locations using pin planner o Pin planner tasks & report windows o Pin migration view o Reserved and unused I/O pins o Back annotation o Verifying I/O assignments o I/O rules checked o I/O assignment analysis output o Validating I/O pin-put o I/O planning with the BluePrint Platform Designer tool o Import/export via CSV o.qsf editing and scripting o Global pin settings o Using synthesis attributes in HDL Lab #6: Assign I/O Pins and Perform I/O Assignment Analysis, Back Annotate Pin Assignments, and Use Pin Migration View Programming & Configuration o Programming files (sof, pof, jam/jbc, jic) o Programming file conversion o Quartus Prime programmer

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