DE2 Board & Quartus II Software

Transcription

1 January 23, 2015

2 Contact and Office Hours Teaching Assistant (TA) Sergio Contreras Office Office Hours SEB 3259 Tuesday & Thursday 12:30-2:00 PM Wednesday 1:30-3:30 PM

3 Syllabus Session 1 Session 2 Session 3 Session 4 Session 5 Session 6 Review of DE2-board and Quartus II Software Quartus II Simulation and Debugging of Hardware Design Design of a Simple Processor Introduction to Altera s Qsys System Integration Tool Making Qsys Components Debugging of application programs

4 Syllabus Continued Session 7 Session 8 Session 9 Session 10 Session 11 Session 12 Introduction to the Altera Monitor Program Altera s Nios II Processor and its Assembly Language Subroutines and Stacks, Use of Logic Instructions Input/Output Organization, Implementation of a Computer System Use of UART and Timer Circuits, Implementation of UART and Timer Circuits Implementation of Any Application Using Assembly Language Code on NIOS II

5 DE2 Board

6 DE2 Board Purpose DE2 includes Digital logic Computer Organization FPGA Cyclone II 2C35 FPGA robust switches LEDs 7-segment displays SRAM SDRAM Flash memory chips 16x2 character display

7 FPGA Field Programmable Gate Array. Contains logic blocks that can be connected together in different ways. Can perform simple logic gates to complex combinational functions.

8 Cyclone II FPGA 33,216 logic elements (LEs) 35 embedded multipliers 4 phase lock loops (PLLs) 475 user I/O pins FineLine BGA 672-pin package

9 Typical FPGA Computer Aided Design (CAD) Flow

10 Typical FPGA CAD Flow Steps Design Entry - the desired circuit is specified either by means of a schematic diagram, or by using a hardware description language, such as Verilog or VHDL. Synthesis - the entered design is synthesized into a circuit that consists of the logic elements (LEs) in the FPGA chip Functional Simulation - the synthesized circuit is tested to verify its functional correctness; this simulation does not take into account any timing issues

11 Typical FPGA CAD Flow Steps Continued Fitting - the CAD Fitter tool determines the placement of the LEs defined in the netlist into the LEs in an actual FPGA chip; it also chooses routing wires in the chip to make the required connections between specific LEs Timing Analysis - propagation delays along the various paths in the fitted circuit are analyzed to provide an indication of the expected performance of the circuit Timing Simulation - the fitted circuit is tested to verify both its functional correctness and timing

12 Typical FPGA CAD Flow Steps Continued Programming and Configuration - the designed circuit is implemented in a physical FPGA chip by programming the configuration switches that configure the LEs and establish the required wiring connections

13 Programming and Configuring the FPGA Device The required configuration file is generated by the Quartus II Compiler s Assembler module. Altera s DE2 board allows the configuration in two different ways, JTAG or AS modes. The configuration data is transferred from the host computer (which runs Quartus II software) to the board by a cable that connects a USB port on the host computer to the leftmost USB connector on the board.

14 JTAG Joint Test Action Group (JTAG) Configuration data is loaded directly into FPGA device This group defined a simple way for testing digital circuits and loading data into them, which became an IEEE standard If FPGA is configured in this manner, it will retain its configuration as long as the power remains turned on. The configuration information is lost when the power is turned off.

15 AS Active Serial (AS) A configuration device that includes some flash memory is used to store the configuration data. Quartus II software places the configuration data onto the configuration device on the DE2 board. This data is loaded into the FPGA upon power-up or reconfiguration. The FPGA does not need to be configured by the Quartus II software if the power is turned off and on.

16 TimeQuest Timing Analyzer Timing analysis - a process of analyzing delays in a logic circuit to determine the conditions under which the circuit operates reliably. These conditions include, but are not limited to, maximum clock frequency (f max ) for which the circuit will produce a correct output. A simple example of the maximum clock frequency computation is shown below.

17 TimeQuest Timing Analyzer To operate correctly, clock frequency is limited by the delay on the longest path in the circuit. If the clock-to-q and setup times for each flip-flop are 1ns, and the delay in each gate is 1 ns, then the maximum clock frequency is f max = 1 = 1 t cq + 3 t and + t su 5ns = 200Mhz Computing f max is a basic function of a timing analyzer. Timing analyzer can be used to guide CAD tools in the implementation of logic circuits.

18 TimeQuest Timing Analyzer If a user requires the circuit to operate at a clock frequency of 250 MHz (>200MHz), the previous solution is inadequate. A functionally equivalent circuit with a different logic structure.

19 TimeQuest Timing Analyzer By placing timing constraints on the maximum clock frequency, it is possible to direct CAD tools to seek an implementation that meets those constraints. The CAD tools may arrive at this functionally equivalent circuit which has f max =250 MHz and meets the required timing constraints.

20 TimeQuest Graphical User Interface (GUI) Main menu is used to interact with the TimeQuest tool and issue commands. View pane hosts any windows that are opened, and initially contains a brief description of each part of the TimeQuest GUI. Console window provides access to a command line for TimeQuest.

21 TimeQuest Graphical User Interface (GUI) Tasks pane contains a sequence of actions that can be performed to obtain timing reports. Creating a timing netlist Reading a timing constraints file Performing timing analysis Generating reports Saving a timing constraints file Report pane contains reports with detailed timing information about the design. These reports are generated using commands in the Tasks pane.

22 References digital logic/tutorials/unv-tutorials.html comp org/tutorials/unv-tutorials.html