64K x 16 1Mb Asynchronous SRAM

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TSOP, FP-BGA Commercial Temp Industrial Temp 64K x 16 1Mb Asynchronous SRAM GS71116AGP/U 7, 8, 10, 12 ns 3.3 V V DD Center V DD and V SS Features Fast access time: 7, 8, 10, 12 ns CMOS low power operation: 145/125/100/85 ma at minimum cycle time Single 3.3 V power supply All inputs and outputs are TTL-compatible Byte control Fully static operation Industrial Temperature Option: 40 to 85 C Package line up GP: RoHS-compliant 400 mil, 44-pin TSOP Type II package U: 6 mm x 8 mm Fine Pitch Ball Grid Array package GU: RoHS-compliant 6 mm x 8 mm Fine Pitch Ball Grid Array package Description The GS71116A is a high speed CMOS static RAM organized as 65,536-words by 16-bits. Static design eliminates the need for external clocks or timing strobes. Operating on a single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS71116A is available in the 6 mm x 8 mm Fine Pitch BGA and 400 mil TSOP Type-II packages. Pin Descriptions Symbol A0 A15 DQ1 DQ16 LB UB WE OE V DD V SS NC Description Address input Data input/output Chip enable input Lower byte enable input (DQ1 to DQ8) Upper byte enable input (DQ9 to DQ16) Write enable input Output enable input +3.3 V power supply Ground No connect Fine Pitch BGA 64K x 16-Bump Configuration 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B DQ16 UB A3 A4 DQ1 C DQ14 DQ15 A5 A6 DQ2 DQ3 D V SS DQ13 NC A7 DQ4 V DD E V DD DQ12 NC NC DQ5 V SS F DQ11 DQ10 A8 A9 DQ7 DQ6 G DQ9 NC A10 A11 WE DQ8 H NC A12 A13 A14 A15 NC 6 mm x 8 mm, 0.75 mm Bump Pitch (Package U) Top View A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 DQ4 V DD V SS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 NC TSOP-II 64K x 16-Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Top view 44-pin TSOP II 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 V SS V DD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC Package TP Rev: 1.10 1/2013 1/13 2001, GSI Technology

Block Diagram A0 Address Input Buffer Row Decoder Memory Array A15 Column Decoder WE OE Control UB I/O Buffer DQ1 DQ16 Truth Table OE WE LB UB DQ1 to DQ8 DQ9 to DQ16 V DD Current H X X X X Not Selected Not Selected ISB1, ISB2 L L Read Read L L H L H Read High Z L X L H L High Z Read L L Write Write L H Write Not Write, High Z H L Not Write, High Z Write IDD L H H X X High Z High Z L X X H H High Z High Z Note: X: H or L Rev: 1.10 1/2013 2/13 2001, GSI Technology

Absolute Maximum Ratings Parameter Symbol Rating Unit Supply Voltage VDD 0.5 to +4.6 V Input Voltage VIN 0.5 to V DD +0.5 ( 4.6 V max.) V Output Voltage VOUT 0.5 to V DD +0.5 ( 4.6 V max.) V Allowable power dissipation PD 0.7 W Storage temperature TSTG 55 to 150 o C Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage for -7/-8/-10/-12 V DD 3.0 3.3 3.6 V Input High Voltage VIH 2.0 V DD +0.3 V Input Low Voltage VIL 0.3 0.8 V Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range TAc 0 70 o C TAI 40 85 o C Notes: 1. Input overshoot voltage should be less than V DD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than 2 V and not exceed 20 ns. Capacitance Parameter Symbol Test Condition Max Unit Input Capacitance CIN V IN = 0 V 5 pf Output Capacitance COUT V OUT = 0 V 7 pf Notes: 1. Tested at TA = 25 C, f = 1 MHz 2. These parameters are sampled and are not 100% tested. Rev: 1.10 1/2013 3/13 2001, GSI Technology

DC I/O Pin Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current IIL VIN = 0 to V DD 1 ua 1uA Output Leakage Current ILO Output High Z VOUT = 0 to V DD 1 ua 1uA Output High Voltage VOH I OH = 4 ma 2.4 Output Low Voltage VOL I LO = +4 ma 0.4V Power Supply Currents Parameter Symbol Test Conditions 0 to 70 C 40 to 85 C 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns Operating Supply Current IDD VIL All other inputs V IH or VIL Min. cycle time I OUT = 0 ma 145 ma 125 ma 100 ma 85 ma 150 ma 130 ma 105 ma 90 ma Standby Current ISB1 V IH All other inputs V IH or VIL Min. cycle time 25 ma 20 ma 20 ma 15 ma 30 ma 25 ma 25 ma 20 ma Standby Current ISB2 V DD 0.2 V All other inputs V DD 0.2 V or 0.2 V 2 ma 5 ma Rev: 1.10 1/2013 4/13 2001, GSI Technology

AC Test Conditions Parameter Conditions DQ Output Load 1 Input high level VIH = 2.4 V Input low level VI L= 0.4 V 50Ω 30pF 1 Input rise time tr = 1V/ns VT = 1.4 V Input fall time tf = 1 V/ns Input reference level 1.4 V Output Load 2 Output reference level 1.4 V 3.3 V Output load Fig. 1& 2 DQ 589Ω Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tlz, thz, tolz and tohz 5pF 1 434Ω Rev: 1.10 1/2013 5/13 2001, GSI Technology

AC Characteristics Read Cycle Parameter Symbol -7-8 -10-12 Min Max Min Max Min Max Min Max Unit Read cycle time trc 7 8 10 12 ns Address access time taa 7 8 10 12 ns Chip enable access time () tac 7 8 10 12 ns Byte enable access time (UB, LB) tab 3 3.5 4 5 ns Output enable to output valid (OE) toe 3 3.5 4 5 ns Output hold from address change toh 3 3 3 3 ns Chip enable to output in low Z () Output enable to output in low Z (OE) Byte enable to output in low Z (UB, LB) Chip disable to output in High Z () t t t t LZ OLZ BLZ HZ * 3 3 3 3 ns * 0 0 0 0 ns * 0 0 0 0 ns * 3.5 4 5 6 ns Output disable to output in High Z (OE) t * 3 3.5 4 5 ns OHZ Byte disable to output in High Z (UB, LB) t BHZ * 3 3.5 3.5 3.5 * These parameters are sampled and are not 100% tested. Read Cycle 1: = OE = V IL, WE = V IH, UB and, or LB = V IL Address trc toh Data Out Previous Data Data valid taa Rev: 1.10 1/2013 6/13 2001, GSI Technology

Read Cycle 2: WE = V IH trc Address taa UB, LB tlz tac tab thz OE tblz tbhz Data Out tolz High impedance toe tohz Data valid Write Cycle Parameter Symbol -7-8 -10-12 Min Max Min Max Min Max Min Max Unit Write cycle time twc 7 8 10 12 ns Address valid to end of write taw 5 5.5 7 8 ns Chip enable to end of write tcw 5 5.5 7 8 ns Byte enable to end of write tbw 5 5.5 7 8 ns Data set up time tdw 3.5 4 5 6 ns Data hold time tdh 0 0 0 0 ns Write pulse width twp 5 5.5 7 8 ns Address set up time tas 0 0 0 0 ns Write recovery time (WE) twr 0 0 0 0 ns Write recovery time () twr1 0 0 0 0 ns Output Low Z from end of write twlz * 3 3 3 3 ns Write to output in High Z twhz * 3 3.5 4 5 ns * These parameters are sampled and are not 100% tested. Rev: 1.10 1/2013 7/13 2001, GSI Technology

Write Cycle 1: WE control twc Address taw twr OE tcw tbw UB, LB WE tas twp Data In Data Out twhz tdw tdh Data valid twlz High impedance Write Cycle 2: control twc Address taw twr1 OE UB, LB tas tcw tbw WE twp Data In tdw Data valid tdh Data Out High impedance Rev: 1.10 1/2013 8/13 2001, GSI Technology

Write Cycle 3: UB, LB control twc Address taw twr1 OE UB, LB tas tcw tbw WE twp Data In tdw Data valid tdh Data Out High impedance Rev: 1.10 1/2013 9/13 2001, GSI Technology

44 Pin, 400 mil TSOP-II 44 D 23 c Dimension in inch Dimension in mm Symbol min nom max min nom max A 0.047 1.20 A1 0.002 0.05 E HE A A2 0.037 0.039 0.041 0.95 1.00 1.05 B 0.01 0.014 0.018 0.25 0.35 0.45 c 0.006 0.15 1 22 e B D 0.721 0.725 0.729 18.31 18.41 18.51 E 0.396 0.400 0.404 10.06 10.16 10.26 e 0.031 0.80 A A1 A2 y HE 0.455 0.463 0.471 11.56 11.76 11.96 L 0.016 0.020 0.024 0.40 0.50 0.60 L1 0.031 0.80 L1 L y 0.004 0.10 Detail A Q Q 0 o 5 o 0 o 5 o Notes: 1. Dimension D& E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Controlling dimension: mm Rev: 1.10 1/2013 10/13 2001, GSI Technology

6 mm x 8 mm Fine Pitch BGA Bottom View pin A1 index 1.20(max) pin A1 index Top View 6 5 4 3 2 1 0.22 ± 0.05 A B C D E F G H 0.75(typ). 0.36(typ) 3.75 5.25 8.00 ± 0.10 D 6.00 ± 0.10 Ball Dia. 0.35 Pitch 0.75 0.10 units: mm Rev: 1.10 1/2013 11/13 2001, GSI Technology

Ordering Information Part Number * Package Access Time Temp. Range GS71116AGP-7 RoHS-compliant 400 mil TSOP-II 7 ns Commercial GS71116AGP-8 RoHS-compliant 400 mil TSOP-II 8 ns Commercial GS71116AGP-10 RoHS-compliant 400 mil TSOP-II 10 ns Commercial GS71116AGP-12 RoHS-compliant 400 mil TSOP-II 12 ns Commercial GS71116AGP-7I RoHS-compliant 400 mil TSOP-II 7 ns Industrial GS71116AGP-8I RoHS-compliant 400 mil TSOP-II 8 ns Industrial GS71116AGP-10I RoHS-compliant 400 mil TSOP-II 10 ns Industrial GS71116AGP-12I RoHS-compliant 400 mil TSOP-II 12 ns Industrial GS71116AU-7 6 mm x 8 mm Fine Pitch BGA 7 ns Commercial GS71116AU-8 6 mm x 8 mm Fine Pitch BGA 8 ns Commercial GS71116AU-10 6 mm x 8 mm Fine Pitch BGA 10 ns Commercial GS71116AU-12 6 mm x 8 mm Fine Pitch BGA 12 ns Commercial GS71116AU-7I 6 mm x 8 mm Fine Pitch BGA 7 ns Industrial GS71116AU-8I 6 mm x 8 mm Fine Pitch BGA 8 ns Industrial GS71116AU-10I 6 mm x 8 mm Fine Pitch BGA 10 ns Industrial GS71116AU-12I 6 mm x 8 mm Fine Pitch BGA 12 ns Industrial GS71116AGU-7 RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 7 ns Commercial GS71116AGU-8 RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 8 ns Commercial GS71116AGU-10 RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 10 ns Commercial GS71116AGU-12 RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 12 ns Commercial GS71116AGU-7I RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 7 ns Industrial GS71116AGU-8I RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 8 ns Industrial GS71116AGU-10I RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 10 ns Industrial GS71116AGU-12I RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 12 ns Industrial Note: Customers requiring delivery in Tape and Reel should add the character T to the end of the part number. For example: GS71116AGP-8T. Rev: 1.10 1/2013 12/13 2001, GSI Technology

1Mb Asynchronous Datasheet Revision History Rev. Code: Old; New Types of Changes Format or Revision 71116A_r1 Creation of new datasheet 71116A_r1; 71116_r1_01 Added 6 ns speed bin to entire document 71116A_r1_01; 71116A _r1_02 71116A_r1_02; 71116A _r1_03 71116A_r1_03; 71116A _r1_04 71116A_r1_04; 71116A _r1_05 71116A_r1_05; 71116A_r1_06 71116A_r1_06; 71116A_r1_07 71116A_r1_07; 71116A_r1_08 71116A_r1_08; 71116A_r1_09 71116A_r1_09; 71116A_r1_10 /Format /Format Updated all power numbers Changed 6 mm x 10 mm FPBGA package designator from U to X Updated Recommended Operating Conditions table on page 4 Changed FPBGA package from 6 x 10 to 6 x 8 (package U) Updated Read Cycle AC Characteristics table Removed 6 ns speed bin from entire document Added 7 ns speed bin to entire document Updated timings for tbhz (Read Cycle) for 10 ns and 12 ns Updated format Added RoHS-compliant information for TSOP-II package Added RoHS-compliant information for FP-BGA package Added RoHS-compliant 400 mil SOJ Updated to MP in ordering information table Rev.1.09a Removed Status column from Ordering Information table. Removed reference to 400 mil, 44 pin SOJ package from entire document Removed 5/6-RoHS TSOP-II references due to EOL Rev: 1.10 1/2013 13/13 2001, GSI Technology

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