FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 1 of 13
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1 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM FEATURES Fast access time : 55ns ow power consumption: Operating current : 20/18mA (TYP.) Standby current : 2µA (TYP.) Single 2.7V ~ 5.5V power supply All inputs and outputs TT compatible Fully static operation Tri-state output Data byte control : B# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 2.0V (MIN.) ead free and green package available Package : 44-pin 400 mil TSOP-II 48-ball 6mm x 8mm TFBGA GENERA DESCRIPTION The is a 2,097,152-bit low power CMOS static random access memory organized as 131,072 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The operates from a single power supply of 2.7V ~ 5.5V and all inputs and outputs are fully TT compatible PRODUCT FAMIY Product Operating Power Dissipation Range Speed Family Temperature Standby(ISB1,TYP.) Operating(Icc,TYP.) (I) -40 ~ ~ 5.5V 55ns 2µA 20/18mA FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 1 of 13
2 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM FUTIONA BOCK DIAGRAM PIN DESCRIPTION Vss A0-A16 DQ0-DQ7 ower Byte DQ8-DQ15 Upper Byte DECODER I/O DATA CIRCUIT 128Kx16 MEMORY ARRAY COUMN I/O SYMBO A0 - A16 DQ0 DQ15 OE# B# UB# VCC VSS DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input ower Byte Control Upper Byte Control Power Supply Ground OE# B# UB# CONTRO CIRCUIT FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 2 of 13
3 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM PIN CONFIGURATION A A5 A A6 A A7 A OE# A UB# 6 39 B# DQ DQ15 DQ1 DQ2 DQ3 Vss DQ4 DQ5 DQ6 DQ DQ14 DQ13 DQ12 Vss DQ11 DQ10 DQ9 DQ8 A B C D E B# DQ8 DQ9 Vss OE# UB# DQ10 DQ11 DQ12 A0 A3 A5 A1 A4 A6 A7 A16 A2 DQ1 DQ3 DQ4 DQ0 DQ2 Vss A16 A A8 A9 F DQ14 DQ13 A14 A15 DQ5 DQ6 A A10 G DQ15 A12 A13 DQ7 A A11 A8 A9 A10 A11 A TSOP II TFBGA ABSOUTE MAIMUN RATINGS* PARAMETER SYMBO RATING UNIT Voltage on VCC relative to VSS VT1-0.5 to 6.5 V Voltage on any other pin relative to VSS VT2-0.5 to VCC+0.5 V Operating Temperature TA -40 to 85(I grade) Storage Temperature TSTG -65 to 150 Power Dissipation PD 1 W DC Output Current IOUT 50 ma Soldering Temperature (under 10 sec) TSODER 260 *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 3 of 13
4 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM TRUT TABE Standby MODE OE# B# UB# Output Disable Read Write Note: = VI, = VI, = Don't care. DC EECTRICA CARACTERISTICS I/O OPERATION DQ0-DQ7 DQ8-DQ15 igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z D OUT igh Z igh Z D OUT D OUT D IN igh Z D IN D OUT igh Z D IN D IN SUPPY CURRENT ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 PARAMETER SYMBO TEST CONDITION MIN. TYP. *4 MA. UNIT Supply Voltage VCC V Input igh Voltage VI * VCC+0.3 V Input ow Voltage VI * V Input eakage Current II VCC = > VIN = > VSS µa Output eakage VCC = > VOUT = > VSS, IO Current Output Disabled µa Output igh Voltage VO IO = -1mA V Output ow Voltage VO IO = 2mA V Average Operating Power supply Current Standby Power Supply Current ICC ICC1 ISB1 Notes: 1. VI(max) = VCC + 3.0V for pulse width less than 10ns. 2. VI(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. O Typical values are measured at VCC = VCC(TYP.) and TA = 25 C CAPACITAE (TA = 25 O C Cycle time = Min., II/O = 0mA =0.2V, ma Others at 0.2V or VCC-0.2V Cycle time = 1µs = 0.2V, II/O = 0mA ma Other pins at 0.2V or VCC - 0.2V = > VCC - 0.2V Others at 0.2V or VCC - 0.2V µa, f = 1.0Mz) PARAMETER SYMBO MIN. MA UNIT Input Capacitance CIN - 6 pf Input/Output Capacitance CI/O - 8 pf Note : These parameters are guaranteed by device characterization, but not production tested. FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 4 of 13
5 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM AC TEST CONDITIONS Input Pulse evels 0.2V to VCC - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference evels 1.5V Output oad C = 30pF + 1TT, IO/IO = -2mA/4mA AC EECTRICA CARACTERISTICS (1) READ CYCE PARAMETER SYM. -55 UNIT MIN. MA. Read Cycle Time trc 55 - ns Address Access Time taa - 55 ns Chip Enable Access Time tace - 55 ns Output Enable Access Time toe - 30 ns Chip Enable to Output in ow-z tcz* 10 - ns Output Enable to Output in ow-z toz* 5 - ns Chip Disable to Output in igh-z tcz* - 20 ns Output Disable to Output in igh-z toz* - 20 ns Output old from Address Change to 10 - ns B#, UB# Access Time tba - 55 ns B#, UB# to igh-z Output tbz* - 25 ns B#, UB# to ow-z Output tbz* 10 - ns (2) WRITE CYCE PARAMETER SYM. -55 UNIT MIN. MA. Write Cycle Time twc 55 - ns Address Valid to End of Write taw 50 - ns Chip Enable to End of Write tcw 50 - ns Address Set-up Time tas 0 - ns Write Pulse Width twp 45 - ns Write Recovery Time twr 0 - ns Data to Write Time Overlap tdw 25 - ns Data old from End of Write Time td 0 - ns Output Active from End of Write tow* 5 - ns Write to Output in igh-z twz* - 20 ns B#, UB# Valid to End of Write tbw 50 - ns *These parameters are guaranteed by device characterization, but not production tested. FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 5 of 13
6 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM TIMING WAVEFORMS READ CYCE 1 (Address Controlled) (1,2) Address trc taa to Dout Previous Data Valid Data Valid READ CYCE 2 ( and OE# Controlled) (1,3,4,5) Address trc taa B#,UB# tace OE# tba tbz tcz toz toe to toz tbz tcz Dout igh-z Data Valid igh-z Notes : 1.is high for read cycle. 2.Device is continuously selected OE# = low, = low, B# or UB# = low. 3.Address must be valid prior to or coincident with = low, B# or UB# = low transition; otherwise taa is the limiting parameter. 4.tCZ, tbz, toz, tcz, tbz and toz are specified with C = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tcz is less than tcz, tbz is less than tbz, toz is less than toz. FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 6 of 13
7 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM WRITE CYCE 1 ( Controlled) (1,2,3,5,6) Address twc taw B#,UB# tcw tbw tas twp twr twz T OW Dout (4) igh-z (4) tdw td Din Data Valid WRITE CYCE 2 ( Controlled) (1,2,5,6) twc Address taw tas twr B#,UB# tbw tcw twp Dout twz (4) igh-z tdw td Din Data Valid FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 7 of 13
8 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM WRITE CYCE 3 (B#,UB# Controlled) (1,2,5,6) Address twc taw twr B#,UB# tas tcw tbw twp Dout (4) twz igh-z tdw td Din Data Valid Notes : 1.,, B#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low, low, B# or UB# = low. 3.During a controlled write cycle with OE# low, twp must be greater than twz + tdw to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the, B#, UB# low transition occurs simultaneously with or after low transition, the outputs remain in a high impedance state. 6.tOW and twz are specified with C = 5pF. Transition is measured ±500mV from steady state. FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 8 of 13
9 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM DATA RETENTION CARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. MA. UNIT VCC for Data Retention VDR > = VCC - 0.2V V VCC = 2.0V Data Retention Current IDR > = VCC - 0.2V µa Other pins at 0.2V or VCC-0.2V Chip Disable to Data See Data Retention tcdr ns Retention Time Waveforms (below) Recovery Time tr trc * - - ns trc * = Read Cycle Time DATA RETENTION WAVEFORM ow Data Retention Waveform (1) ( controlled) > VDR = 2.0V (min.) (min.) tcdr VI > = -0.2V tr VI ow Data Retention Waveform (2) (B#, UB# controlled) > VDR = 2.0V (min.) (min.) B#,UB# tcdr VI B#,UB# > = -0.2V tr VI FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 9 of 13
10 θ January FEBRUARY K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM PACKAGE OUTINE DIMENSION 44-pin 400mil TSOP-Ⅱ Package Outline Dimension SYMBOS DIMENSIONS IN MIMETERS DIMENSIONS IN MIS MIN. NOM. MA. MIN. NOM. MA. A A A b c D E E e ZD y Θ 0 o 3 o 6 o 0 o 3 o 6 o FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 10 of 13
11 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM 48-ball 6mm 8mm TFBGA Package Outline Dimension FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 11 of 13
12 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM ORDERING INFORMATION Alliance Organization VCC Range Package Operating Temp Speed ns -55ZIN 128K x V 44pin TSOP II Industrial ~ -40 F - 85 F 55-55BIN 128K x V 48ball TFBGA Industrial ~ -40 F - 85 F 55 PART NUMBERING SYSTEM AS6C N Device Number Package Option Temperature Range low power 20 = 2M Access 44pin TSOP II I = Industrial S RAM prefix 16 =x16 Time 48ball TFBGA (-40 to + 85 C) N = ead Free RoS compliant part FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 12 of 13
13 128K 16 BIT OW 512K POWER 8CMOS BIT OW SRAMPOWER CMOS SRAM Alliance Memory, Inc 511 Taylor Way, San Carlos, CA 94070, USA Phone: Fax: Copyright Alliance Memory All Rights Reserved Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks ofalliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to thisdocument and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The datacontained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at anytime, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information inthis product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of anyproduct described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability orwarranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to inalliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance'sTerms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion ofalliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against allclaims arising from such use. FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 13 of 13
MARCH/2008, V 1.0 Alliance Memory Inc. Page 1 of 12
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