Question Microprocessor is the example of architecture. Princeton Von Neumann Rockwell Harvard nswer Question bus is unidirectional. ata ddress ontrol None of these nswer Question Use of isolates PU form frequent accesses to main memory. Local I/O controller Expansion bus interface ache structure System bus nswer Question buffers data transfer between system bus and I/O controllers on expansion bus.
Local I/O controller Expansion bus interface ache structure None of these nswer Question Timing involves a clock line. Synchronous synchronous symmetric None of these nswer Question -----timing takes advantage of mixture of slow and fast devices, sharing the same bus Synchronous asynchronous symmetric None of these nswer Question In 1 st generation language was used to prepare programs. Machine ssembly High level programming
Pseudo code nswer Question The transistor was invented at laboratories. T &T T &Y M &T T &M nswer Question is used to control various modules in the system ontrol us ata us ddress us ll of these nswer Question The disadvantage of single bus structure over multi bus structure is Propagation delay ottle neck because of bus capacity oth and Neither nor nswer
Question provide path for moving data among system modules ontrol us ata us ddress us ll of these nswer Question Microcontroller is the example of architecture. Princeton Von Neumann Rockwell Harvard nswer Question computer with more than one PU allows instruction from different program to be executed simultaneously is called as Microprocessor Miniprocessor super processor multiprocessor nswer Question The compact combination of PU, memory and IO circuits
in one System is called Microcomputer Minicomputer Supercomputer None of above nswer Question computer system with one PU or microprocessor is generally referred to Mainframe Microcomputer Large computer None of above nswer Question Performance of system and execution time of system are proportional to each other. irectly Inversely Equally None of the above nswer Question In pipelined processing common steps involved in instruction processing are overlapped
partially completely Randomly None of the above nswer Question In non pipelined PU, instructions are executed in sequence overlapped any fixed None of the above nswer Question omputers main or primary memory M is ROM RM PROM None of the above nswer Question Supercomputers mainly used in scientific calculations involving large amounts of vectors and matrix calculations are some times referred as
super processor Vector processor Parallel processor Scientific processor nswer Question control signal can be Memory read Memory write I/ O read ll of these nswer Question1 In Von Neumann Machine feature was responsible for performance bottleneck. Stored program Separate memory for data and code I/O access None of these nswer Question2 PU Means
ontrol Processing Unit ontrol Programming Unit entral Processing Unit entral Programming Unit nswer Question3 Key concept of stored program was introduced by Safwat G. Zaky John Von Neumann j. Hays Stalling William nswer Question4 Which of the following operation are involved in an instruction cycle? Opcode decoding Instruction execution Instruction fetching ll of these nswer Question5 stores address of next instruction to be executed. R P IR
nswer Question6 keep track of execution of a program. Program ounter Instruction Register General Purpose Register Memory ddress Register nswer Question7 contains the data to be written into or read out of address location. MR P MR IR nswer Question8 In IS actual word transfer take place between memory and R R IR nswer
Question9 ata register of IS is wide. 16-bit 20-bit 40-bit 48-bit nswer Question1 0 nswer Question1 1 nswer R in IS is wide. 12-bit 14-bit 16-bit 18-bit Program control unit of IS fetches instruction simultaneously. Two Three Four Six Question1 In IS machine, IR stores instruction.
2 Immediately executable Later executable urrently executing borted type nswer Questions 13 nswer Question1 4 nswer Question1 5 In IS machine, IR stores instruction. Immediately executable Later executable urrently executing borted type rchitecture shows separate memory banks for data and programs. Princeton Harvard Von Neumann Rockwell Harvard architecture shows features of executing instruction in instruction cycle than von Neumann.
More ouble Reduced Exactly half nswer Question1 6 nswer Question1 7 nswer Question1 8 rchitecture uses both RIS and IS architectures. Von Neumann Harvard abbage None of these In IS machine, program control unit fetches.. instructions simultaneously from memory One Two Three four IS machines are designed to process all bits of binary numbers.. Randomly Simultaneously
Serially None of the above nswer Question1 9 nswer Question2 0 nswer Question2 1 2048,16 4096,20 4096,60 In PU of IS computer who issues control signals to data processing unit, memory and other circuits for execution of instruction? Program ounter P Program ontrol Unit PU ccumulator Instruction Register IR In IS omputer fetches and interprets the instruction in memory and causes them to be executed. LU ontrol Unit ccumulator Program counter In original Von Neumann Machine, memory unit consists of storage location of bits each.
4096,40 nswer Question2 2 nswer In Original IS Machine,storage location was referred to as yte Word igit Number Question2 3 nswer In IS machine, data and code have memory. Same Separate istinct More Question1 The three main parts of a stored programmed computer are PU, memory, I/ O Register, memory control unit PU, register, LU PU, I/ O, control unit
nswer Question2 nswer Question3 nswer PU takes time to obtain word from memory than one of its internal register Same longer Lesser Zero If performance of system is 2times the performance of system then execution times for system is as of execution time for system. half 2 times same None of above Question4 To enhance the speed of processor, small memory unit placed between PU and main memory M is called Program memory Stack memory ache memory ynamic memory
nswer Question5 ache memory can store Only instructions Instructions and data Only data None of the above nswer Question6 ache memory is usually than main memory. bigger smaller faster () and () both nswer Question7 Most I/O operation are memory operation easier faster slower None of the above nswer
Question8 Major component of most I/O system is set of memory devices secondary primary cache None of the above nswer Question9 nswer Question1 0 nswer Question 1 I/O devices are attached to host computer by means of I/O ports Memory slots ontrol bus None of the above In early supercomputer parallel processing was heavily depend on Sequential processing Random processing Pipeline processing Nonpipeline processing ollection of data, address and control us is usually referred as.
Processor bus system bus local bus complete bus nswer Question 2 nswer Question 3 nswer Question 4 ddress bus is. multidirectional bidirectional unidirectional and both In a single bus structure can communicate with each other at a time Over a single bus. only 2 units no unit all the units None of the above PU can read data from memory and I/O nd write data to memory and I/O with data bus. multidirectional unidirectional
bidirectional none of the above nswer Question 5 nswer Question 6 nswer Question 7 Performance of computer system with single bus structure if large number of devices are connected to common System bus. decreases increases remains same none of the above When the same bus is used for more than one function at different time zone it is alled as. shared bus common bus system bus multiplexed bus The occurrence of one event on a bus follows and depends on occurrence of previous event in. synchronous timing asynchronous timing shared timing
none of the above nswer Question 8 nswer bus is used to connect major computer components. ddress ata ontrol System Question 9 nswer Question 10 ata us is Unidirectional idirectional Unidirectional &idirectional None of these bus width decides the number of bits transferred a time ata ddress ontrol system
nswer Question 11 nswer Question 12 nswer bus width decides the range of locations that can be accessed ata ddress ontrol system What is the benefit of physically dedicated bus? cheaper less bus contention overall system size decreases none of these Question What is connected between processors bus &high speed 13 bus? SSI LN ridge local bus nswer
Question 14 nswer Question 15 nswer Question 16 nswer What is the Specialty of high performance bus architecture over traditional bus architecture? Expansion bus local bus high speed bus none of these What is the impact if the width of data bus is increased? reduced speed of data transfer Greater no of bits transferred at one time Greater range of memory location referenced none of these What is the impact of increasing address bus width? Speedy data transfer large no of data transfer increased addressing capacity decreased addressing capacity
Question1 0 to 127 255 to 127 0 to 255 nswer Question2 nswer Question3 nswer For unsigned 8-bit binary numbers the decimal range is None of these Forming the 2 s complement of a number involves 1 to the 1's complement of the number. multiplying subtracting adding both () and () 1's complement representation is nothing but bit-by-bit operation' OR N EX-OR NOT Question4 2's complement of (11001)2 is
(00111)2 (00110)2 (11000)2 ll the above nswer Question5 2's complement of (11000100)2 is 00111100 00111011 11001100 10111011 nswer Question6 1's complement of (01011011)2 is 10100100 00111000 10111011 None of these nswer Question7 The highest positive decimal number represented in signed binary numbers is the highest positive decimal number for unsigned binary numbers of a fixed number of bits. double equal
half triple nswer Question8 nswer The configuration of cascaded connection of n full adder, where the catties must Propagate through this cascade, it called. n-bit ripple carry adder m-bit ripple carry adder (n+1)-bit ripple carry adder (m+1)- bit ripple carry adder Question9 LS of a number means Low Sequence it Low Sequence yte Least Significant it Least Significant yte nswer Question1 1's complement + = 2's complement 0 1 2 3-1
nswer Question1 1 nswer Question1 2 nswer In 1's complement subtraction when carry is generated it is ignored added to final result subtracted from final result ignored and 1's complement of final result is done" In 2's complement subtraction when carry is generated it is ignored added to final result subtracted from final result ignored and 1's complement of final result is done" Question1 To solve Problem of representation of negative exponent in floating Point number, is added to the true exponent' packed bias value unpacked bias value bias value
scaling factor nswer Question2 bits are reserved for signed exponent in IEEE 754 standard for a double-precision representation of floating numbers. 8 16 11 18 nswer Question3 bits are reserved for mantissa in IEEE 754 standard for a single-precision presentation of floating point numbers. 16 20 23 32 nswer Question4 bits are reserved for mantissa in IEEE 754 standard for a double-precision representation of floating point numbers. 16 32
52 64 nswer Question5 nswer In integer numbers, radix point is assumed to be to the of the right most digit. right left a or b none of these Question6 nswer Floating point number system allows the representation of number having. integer part fractional part integer and fractional part integer or fractional part Question1 ooth's algorithm generates bit product for n-bit multiplication. n 2n 3n
4n nswer Question2 11110001 1101110001 1001110001 1001110 nswer What is the product of following multiplication: -13 * +11 in binary? Question3 Using bit pair recoding technique, what is the multiplier (-6) 10 in bit pair recorded form [-1 +1] [-1 0] [-1-2] [+1-2] nswer Question4 entify worst case multiplier according to ooth's algorithm. 10101010 10000000 10111111 11100000 nswer
Question5 it pair recording form for multiplication 111010 is [0 +1-2] [0-1 -2] [0-1 +2] [0 +1 +2] nswer Question6 In ooth s algorithm, if Q 0 = 0 and Q -1 = 0 in multiplier Q then it will perform which operation next? =-M =+M rithmetic right shift of, Q and Q -1 nswer =M- Question7 In ooth s algorithm, if Q 0 =1 and Q -1 = 1 of multiplier Q then it will perform which operation next? =-M =+M =M-
rithmetic right shift of, Q and Q -1 nswer Question8 In ooth s algorithm, if Q 0 = 1 and Q -1 = 0 of multiplier Q, then it will perform which operation next? =-M =+M rithmetic right shift of, Q and Q -1 nswer =M- Question9 In ooth s algorithm, if Q 0 =0 and Q -1 =1 of multiplier Q then it will perform which operation next. =-M =+M rithmetic right shift of, Q and Q -1 nswer =M- Question10 In ooth s bit-pair recoding, what version of multiplicand M
0*M nswer Question11 will be selected if consecutive multiplier bits are 001? +1*M -1*M +2*M 0*M nswer Question12 In ooth s bit-pair recoding, what version of multiplicand M will be selected if consecutive multiplier bits are 010? +1*M -1*M +2*M 0*M In ooth s bit-pair recoding, what version of multiplicand M will be selected if consecutive multiplier bits are 011? +1*M -1*M
nswer Question13 +2*M 0*M nswer Question14 In ooth s bit-pair recoding, what version of multiplicand M will be selected if consecutive multiplier bits are 100? +1*M +2*M -2*M 0*M nswer In ooth s bit-pair recoding, what version of multiplicand M will be selected if consecutive multiplier bits are 101? +1*M -1*M +2*M
Question15 0*M nswer Question16 In ooth s bit-pair recoding, what version of multiplicand M will be selected if consecutive multiplier bits are 110? +1*M -1*M +2*M 0*M nswer Question17 In ooth s bit-pair recoding, what version of multiplicand will be selected if consecutive multiplier bits are 111? +1*M -1*M +2*M 1100110010 1110110010 Using ooth's lgorithm, multiply +13 and -6. What is product?
101100111 110110011 nswer Question18 1100110010 1110110010 101100111 1110110101 nswer Question19 1001111100 1101111100 1101111101 101111101 nswer Using ooth's lgorithm, multiply +15 and -5. What is product? Using ooth's lgorithm, multiply -12 and +11. What is product?
Question20 1101110001 1101110000 1001110001 1011100010 nswer Multiply the following numbers represented in 2's complement notation using ooth's lgorithm. Multiplicand= 10011, Multiplier = 01011